DepartmentofComput

er
SystemsEngineering

DigitalSystemDesign

Handout#02
VerilogOperators

LabLearningObjectives:

Aftercompletingthissession,studentshouldbeableto:
 useVerilogHDLoperatorswithease.

Note:Submitthelabreport(solvedactivitiesandexercises)beforethenextlab.
LabHardwareandSoftwareRequired:

1.Desktop/LaptopComputer with internet connection.

BackgroundTheory:

Every computer language has a set of predefined operators to perform arithmetic

andlogical operations. In this lab, you will explore numerous operators available in
VerilogHDL.Theseoperatorsare listedintable #1.

Table1:VerilogOperators
LabActivity:

You are required to make a hardware design that uses pre-defined operators in
VerilogHDL.Toachievethisgoal,youwillmakeamodulethattakessomeinputs,usessomeofth
eavailableoperators(listedintable#1),andproducesanoutput.Later,writeatest
benchprogramtoanalyzethebehaviorofyourhardwaredesignagainsttheinputtestvectors.Th
e usage of all the operators is explained in chapter#3 of the textbook. Please
usesyntaxesfromyourtextbook for thisactivity.

Exercise:

1. Explain the working of the four shift operators through a Verilog HDL design.
Youmayuse2places forshifting.

2. Makea2-bitsmaxcomparatorHDLdesignusing‘?’operator.Youmaytakethree2-bit
inputs (a, b, c), and a 2-bit output should be a max number of all the threeinputs.

Note:Youalsoneedtowriteatestbenchcodefortheaboveexercises.Pleaseprovideyourexplanationwithsupportin
gwaveformsobtainedfromyourdesign.
Testbench:

`timescale 1ns / 1ps

module lab_2_test;

reg a,b;
wire plus, sub, mul, div, mod, expo;
lab_2_des f1(.a(a),

.b(b),
.plus(plus),
.sub(sub),
.mul(mul),

.div(div),
.mod(mod),
.expo(expo)

);

initial begin

a=1'b0; b=1'b0;
#1;
a=1'b0; b=1'b1;
#1;
a=1'b1; b=1'b0;

#1;

a=1'b1; b=1'b1;
#1;
$finish;

end
endmodule

Design code:

`timescale 1ns / 1ps

module lab_2_des(
input wire a, b,

output wire plus, sub, mul, div, mod, expo

);

assign plus= a+b;

assign sub= a-b;
assign mul= a*b;

assign div= a/b;

assign mod= a%b;
assign expo= a**b;

endmodule
Shift operators:

Design code:

module shift_op_des(
input wire [3:0] data,

output wire [3:0] shift_left,

output wire [3:0] shift_right,

output wire [3:0] shift_right_arth,

output wire [3:0] shift_left_arth

);
assign shift_left =data << 2;

assign shift_right =data >> 2;

assign shift_left_arth =data <<< 2;

assign shift_right_arth =data >>> 2;

endmodule

Testbench:

`timescale 1ns / 1ps

module shift_op_test;
reg [3:0] data;

wire [3:0] shift_left, shift_right, shift_left_arth, shift_right_arth;

shift_op_des uut(
.data(data),
.shift_left(shift_left),
.shift_right(shift_right),
.shift_left_arth(shift_left_arth),

.shift_right_arth(shift_right_arth)

);
initial begin
data = 4'b1001;

#1;
data = 4'b1100;
#1;

data = 4'b1101;
#1;

data = 4'b0011;
#1;
$finish;

end

endmodule

Relational Operator:
Design code:

`timescale 1ns / 1ps

module relational_des(

input wire [3:0] a,b,

output wire less_than, greater_than, less_or_equal, greater_or_equal
);
assign less_than = (a<b);

assign greater_than = (a>b);

assign less_or_equal = (a<=b);

assign greater_or_equal = (a>=b);

endmodule

Testbench:

`timescale 1ns / 1ps

module relational_test;

reg [3:0] a, b;

wire less_than, greater_than, less_or_equal, greater_or_equal;

// Instantiate the design module

relational_des uut (

.a(a),

.b(b),
.less_than(less_than),
.greater_than(greater_than),

.less_or_equal(less_or_equal),
.greater_or_equal(greater_or_equal)
);

initial begin

a = 4'b1010; b = 4'b1011;

#1;

$display("a = %b, b = %b, less_than = %b, greater_than = %b, less_or_equal = %b, greater_or_equal =
%b", a, b, less_than, greater_than, less_or_equal, greater_or_equal);

$finish;

end

endmodule
Equality:

Design code:

`timescale 1ns / 1ps

module relational_des(
input wire [3:0] a,

input wire [3:0] b,

output wire equal,

output wire equal_not,

output wire case_equal,

output wire case_equal_not

);

assign equal = (a == b);

assign equal_not = (a != b);

assign case_equal = (a === b);

assign case_equal_not = (a !== b);

endmodule

Testbench:

`timescale 1ns / 1ps

module relational_test;

reg [3:0] a, b;

wire equal, equal_not, case_equal,case_equal_not;

// Instantiate the design module

relational_des uut (
.a(a),
.b(b),

.equal(equal),

.equal_not(equal_not),
.case_equal(case_equal),
.case_equal_not(case_equal_not)

);

initial begin

a = 4'b1010; b = 4'b1011;
#1;

$display("a = %b, b = %b, equal = %b, equal_not = %b,

case_equal = %b, case_equal_not = %b", a, b, equal,

equal_not, case_equal, case_equal_not);

$finish;
end
endmodule

Bitwise:
Design code:

`timescale 1ns / 1ps

module relational_des(
input wire [3:0] a,

input wire [3:0] b,

output wire [3:0] bitwise_and,

output wire [3:0] bitwise_or,
output wire [3:0] bitwise_neg,

output wire [3:0] bitwise_xor

);

assign bitwise_and = a & b;

assign bitwise_or = a | b;
assign bitwise_neg= ~a;
assign bitwise_xor= ^b;

endmodule

Testbench:

`timescale 1ns / 1ps

module relational_test;

reg [3:0] a, b;
wire [3:0] bitwise_and, bitwise_or, bitwise_neg, bitwise_xor;
// Instantiate the design module

relational_des uut (

.a(a),
.b(b),
.bitwise_and(bitwise_and),

.bitwise_or(bitwise_or),

.bitwise_neg(bitwise_neg),
.bitwise_xor(bitwise_xor)

);

initial begin

a = 4'b1010; b = 4'b0101;
#1;
$display("a = %b, b = %b, bitwise_and = %b, bitwise_or = %b, bitwise_neg

= %b, bitwise_xor = %b", a, b, bitwise_and, bitwise_or, bitwise_neg,

bitwise_xor);

$finish;
end
endmodule

Reduction:

Design code:

module relational_des(

input wire [3:0] a,

output wire and_reduce,

output wire or_reduce,

output wire xor_reduce

);

assign and_reduce = &a; // AND reduction

assign or_reduce = |a; // OR reduction

assign xor_reduce = ^a;

endmodule
Testbench:

`timescale 1ns / 1ps

module relational_test;

reg [3:0] a;

wire and_reduce, or_reduce, xor_reduce;

// Instantiate the design module
relational_des uut (

.a(a),
.and_reduce(and_reduce),
.or_reduce(or_reduce),

.xor_reduce(xor_reduce)

);

initial begin

a = 4'b1111;

#1;

$display("a = %b, and_reduce = %b, or_reduce = %b, xor_reduce = %b, ", a, and_reduce,
or_reduce, xor_reduce);

$finish;
end

endmodule
Conditional:
Design code:

assign cond = (a > b) ? a : b;

endmodulemodule relational_des(

input wire [3:0] a,

input wire [3:0] b,
output wire [3:0] cond

);

assign cond = (a > b) ? a : b;

endmodule

Testbench:

`timescale 1ns / 1ps module relational_test;

reg [3:0] a, b;

wire [3:0] cond;

relational_des uut (
.a(a),

.b(b),

.cond(cond)
);

initial begin

a = 4'b1010; b = 4'b0101;
#1;

$finish;

end

endmodule
Logical operator:
Design code:

module relational_des(
input wire [3:0] a,

input wire [3:0] b,

output wire logical_and,

output wire logical_or,

output wire logical_neg

);

assign logical_and = a && b;

assign logical_or = a || b;

assign logical_neg = !a;

endmodule

Testbench:

module relational_test;

reg [3:0] a, b;

wire logical_and, logical_or, logical_neg;

relational_des uut (

.a(a),

.b(b),
.logical_and(logical_and),

.logical_or(logical_or),

.logical_neg(logical_neg)

);
initial begin

a = 4'b1010; b = 4'b0000;

#1;

$finish;

end
endmodule

Concatenation Operation:
Design code:
module relational_des(
input wire [3:0] a,
input wire [3:0] b,
output wire [7:0] concat
);
assign concat = {a, b};
endmodule
Testbench:
`timescale 1ns / 1ps

module relational_test;
reg [3:0] a, b;
wire [7:0] concat;

relational_des uut (

.a(a),

.b(b),
.concat(concat)
);

initial begin
a = 4'b1010; b = 4'b0101;
#1;

$finish;
end
endmodule