IET Power Electronics

Research Article

Simple digital algorithm for improved ISSN 1755-4535

Received on 12th April 2018
Revised 8th November 2018
performance in a boost PFC converter Accepted on 11th January 2019
E-First on 7th February 2019
operating in CCM doi: 10.1049/iet-pel.2018.5250
www.ietdl.org

Harish Sudhakaran Nair1 , Lakshmi Narasamma1

1Department of Electrical Engineering, Indian Institute of Technology Madras, Chennai, India
E-mail: [email protected]

Abstract: In power factor correction (PFC) converters, achieving both good steady-state input current waveform and fast output
dynamic response is a challenge. This is due to the effect of the double-line frequency ripple present in the sensed output
voltage signal which tends to distort the reference current applied to the current controller, thus leading to a distorted input
current waveform. Low bandwidth (BW) voltage loop designs to reduce this input current distortion make the output dynamic
response very sluggish. A digital control algorithm for the estimation of the average value of the sensed output voltage is
proposed in this study to achieve low total harmonic distortion input current and fast dynamic response with a higher BW voltage
loop. The proposed algorithm is computationally less intensive and requires no additional sensors or circuitry. The effectiveness
of the proposed control algorithm is validated through simulation and experimental tests on a 300 W boost PFC converter
prototype operating in continuous conduction mode.

1 Introduction dynamic performance and maintaining unity input power factor is a

challenge due to the pulsating nature of the single-phase AC input
Power factor correction (PFC) converters are extensively used to power [4]. The input power pulsation causes a ripple at the double-
ensure that the current drawn by the converter from the input AC line frequency (100 Hz ripple for input line of 50 Hz) in the output
mains is sinusoidal and in phase with the input sinusoidal voltage voltage waveform which gives rise to input current distortions [5,
while maintaining the output voltage regulated for the load or the 6]. This current distortion occurs because the reference current gets
downstream converter. As a consequence, the PFC front end distorted as the double-line frequency ripple (second harmonic
converter helps the equipment to meet the harmonic standards such ripple) in the sensed output voltage enters the feedback loop along
as EN61000-3-2 [1]. Among the various PFC topologies, the boost with the DC component of the sensed output voltage. To achieve
converter based topologies are widely used [2] due to their low total harmonic distortion (THD) input current and unity input
continuous input current, ground referenced switch and voltage power factor, the voltage loop bandwidth (BW) is kept generally
step up capability. Among the control strategies, average current low [5, 7], typically around 5–10 Hz. This results in poor output
mode control is well suited for boost PFC converters [3]. Average dynamic response. Apart from the slow dynamic response due to
current mode control of the boost PFC converter requires a two- the low BW, the converter components are subjected to substantial
loop control structure [3]. The circuit diagram of the boost PFC stress due to the undershoots and overshoots occurring during
converter with the two-loop average current mode control method transients [8].
feeding a resistive load is given in Fig. 1. Various methods have been researched over the years to achieve
The control objectives in the boost PFC converter include the both high quality input current waveform and fast output dynamic
tight regulation of the output voltage and input current shaping. response in PFC converters. Among them, one of the options is to
These converters are usually designed to operate under a wide AC have a downstream DC–DC converter [9] which regulates the
input voltage range. In addition to tight output voltage regulation output voltage with a fast feedback loop; this leads to additional
under all conditions for the load, fast dynamic performance is components and converter control requirements. To reduce the
desired. The input being single-phase AC, achieving good output number of components, single stage topologies are proposed in [10,
11], however, the DC-link capacitor experiences high stress and the
converter control becomes complex [3]. In [12], an auxiliary
flyback circuit is used to suppress the output voltage ripple in an
isolated full-bridge boost PFC converter.
Control methods are proposed in [3, 4, 13–25] to nullify the
effects of the double-line frequency ripple component. Load
current feedforward based control techniques for dynamic
performance improvement are employed in [13, 14] where the load
current is sensed and given as a feedforward to the control loop.
However, these methods require additional sensors for load current
sensing or require load estimation and need proper tuning of the
feedforward gain, which may not be the optimal gain for all the
operating conditions for a converter subjected to a wide range of
line/load variations [3]. A sample and hold based method is used to
obtain the average output voltage by sampling at the zero crossing
instant of the input voltage [15]. This method requires accurate
zero-crossing detection of the input voltage.
Fig. 1 Implementation of average current control on a boost PFC
Digital notch filters are proposed in [16, 17], wherein the notch
converter
frequency is placed at the output voltage ripple frequency. Such a
filter eliminates the double-line frequency component before it

IET Power Electron., 2019, Vol. 12 Iss. 5, pp. 1102-1113 1102

© The Institution of Engineering and Technology 2019
 17554543, 2019, 5, Downloaded from https://ietresearch.onlinelibrary.wiley.com/doi/10.1049/iet-pel.2018.5250 by Readcube (Labtiva Inc.), Wiley Online Library on [01/05/2024]. See the Terms and Conditions (https://onlinelibrary.wiley.com/terms-and-conditions) on Wiley Online Library for rules of use; OA articles are governed by the applicable Creative Commons License
reaches the voltage controller. Implementation of accurate notch i. The proposed algorithm is fully digital and is computationally
filters in analog is a challenge due to component tolerances and less intensive. It could be implemented on the same processor
ageing. In digital implementations, notch filter requires accurate without any additional sensing circuits, sensors or signal
design; the notch filters are designed to filter only the double-line conditioning circuits.
frequency ripple component and not its multiples. A comb filter is ii. It does not require any additional sampling channels in the
proposed in [8] to remove the harmonic components corresponding DSP processor.
to the multiples of the double-line frequency. However, the comb iii. Consistent improved converter performance is obtained under
filter implementation complexity increases if higher order wide operating conditions.
multiples of the ripple frequency are to be eliminated. Moving iv. The algorithm does not involve digital loop design.
average filters (MAFs) are proposed in [18, 19] for boost PFC v. The proposed algorithm is independent of the single-phase
converters. In [18], an FPGA-based MAF is used where, the output PFC converter topology/model.
voltage waveform is integrated over a fixed interval and the result
of integration is passed on to a running average computation. The The proposed algorithm is validated on a 300 W CCM boost
integration is done continuously over a fixed time interval and PFC converter. The improvement in the input current waveform
same is repeated every ripple cycle. MAF has the advantage of quality and output dynamic performance by employing the
filtering the ripple frequency components and its multiples as well. proposed algorithm is analysed and validated using simulation and
The concern of MAF is that the computational complexity and experimental results.
memory requirements depend on the length of the averaging This paper is presented as follows. Section 2 analyses the
window considered. problems associated with the 100 Hz ripple present in the output
Dynamic performance improvement is achieved by sampling voltage and highlights the motivation for this work. The issues are
the maximum peak values of the output voltage ripple [20]. explained and analysis is presented. In Section 3, the proposed
Sampling at the maximum peaks ensures the removal of the ripple algorithm is presented and is verified with simulation results. The
component; this method controls the maximum peak value of the experimental results are given in Section 4 along with the
output voltage ripple rather than the average value of output comparison of the proposed algorithm with the popular, relevant
voltage. Hence, the actual output voltage average value changes control methods from the literature. The conclusion is given in
with load. Both the maximum and the minimum peaks of the ripple Section 5.
are simultaneously sampled in [20]. Sliding mode based control
methods for improving dynamic response are presented in [21, 22].
Suitable sliding functions are derived to achieve fast dynamic 2 Motivation
response and high input power factor. Non-linear control methods PFC converters are controlled using a two-loop average current
require higher computation time and hence, remain as a bottleneck control structure [3] as shown in Fig. 1. The inner current loop has
for converters which are operated at high switching frequencies. higher BW to track the reference current obtained by multiplying
In ripple estimation and cancellation techniques [3–6, 23–25], the output of the voltage controller with the input sine profile. The
the output voltage ripple is estimated based on a template and outer voltage loop is generally a slow loop, the implications of
subtracted from the sensed output voltage signal to obtain the which are highlighted in this section.
ripple free average sensed voltage. A ripple cancellation method by A PFC converter operating at unity power factor has an output
sampling the output voltage 90° shifted to obtain the peak value of voltage vo(t) consisting of a DC component and a double-line
the output voltage is presented in [23]. An adaptive estimator is frequency component as given in [3, 4]. The output voltage vo(t) is
used to estimate the output voltage ripple and subtract it from the written in the form given below [4]:
sensed voltage signal in [5]. This method requires the measurement
of load current for ripple estimation and a phase locked loop. A vo(t) = V o + vor(t)
ripple estimation circuit with a bandpass filter and amplifier is (1)
proposed in [6]; it is prone to estimation errors due to its = V o − V orcos(2ωLt − θo)
uncertainties in parameter estimation. Certain ripple cancellation
methods are based on the system model, hence, there is a where V o and V or are the average value of output voltage and
requirement of an accurate value of output capacitance and load amplitude of the output voltage ripple, respectively, while
current [23]. A double injection compensation method is proposed θo = tan−1 ωLRC and ωL = 2π f L. The value of θo is ∼90° for PFC
in [24]. This method requires the sensing of diode current. Fast converters with large output capacitors for output ripple filtering
output dynamic performance is obtained by employing an analogue [4].
ripple estimation/cancellation network consisting of an amplitude To reduce the distortion on the input current, a low BW (5–10
tuner and phase shifter based on switched resistor circuits in [3, 4]. Hz) voltage loop is generally preferred. However, this leads to a
Ripple estimation is done using a phase locked loop and an poor dynamic performance on the output voltage. In practical
integrator in [25]. implementations, a high frequency pole is usually added to the
Digital control of converters is preferred due to the advantages voltage controller to attenuate the double-line frequency ripple
such as programmability, repeatability of results, lesser external component and thereby reduce the input current distortion [4, 13].
circuitry, no much ageing issues and availability of low-cost This makes the output dynamic response further sluggish. A boost
processors. Recent digital PFC control methods [22, 26–28], use a PFC converter is simulated in a MATLAB/Simulink environment
predictive or a non-linear current controller with a PI outer voltage using the specifications given in Table 1 to analyse the impact of
loop for accurate inductor current shaping. Predictive and non- the output double-line frequency ripple on the steady state and
linear current control methods for input current shaping are output dynamic performance. The steady state and dynamic
computation intensive when compared to conventional linear performance studies are performed with voltage controllers
control techniques. The ADC sampling and conversion, as well as designed for case (a) and case (b) as given in Table 1.
all the computations required for the current controller, voltage For the inner current control loop, the converter non-linear
controller and feedforward multiplier need to be completed within equations are averaged over the switching period and the linearised
the switching period. Therefore, the additional digital algorithms small-signal model is obtained. The small-signal duty to inductor
employed for double-line frequency ripple elimination from the current transfer function is approximated as V o /sL [8]. The
sensed output voltage signal must add only minimum additional
voltage controller design is based on the small-signal model for the
computational burden on the processor.
control signal to output voltage transfer function for the boost PFC
A digital algorithm for estimation of the average value of the
converter [29]. This outer voltage loop model is valid for
sensed output voltage for achieving fast output dynamic response
frequencies below the input line frequency since the averaging is
while maintaining low THD input current is proposed in this paper
done over the line period.
for a boost PFC converter application. The significant features of
Two cases are considered as given below:
the proposed algorithm are highlighted below:

IET Power Electron., 2019, Vol. 12 Iss. 5, pp. 1102-1113 1103

© The Institution of Engineering and Technology 2019
 17554543, 2019, 5, Downloaded from https://ietresearch.onlinelibrary.wiley.com/doi/10.1049/iet-pel.2018.5250 by Readcube (Labtiva Inc.), Wiley Online Library on [01/05/2024]. See the Terms and Conditions (https://onlinelibrary.wiley.com/terms-and-conditions) on Wiley Online Library for rules of use; OA articles are governed by the applicable Creative Commons License
i. Case (a): Lower voltage loop BW: The current control loop is component in vcv(t) gets multiplied with the input sine feedforward
designed for 5 kHz BW and 70° phase margin using a PI to transform into a third harmonic component in the generated
controller. A low BW voltage loop of 5 Hz and 60° phase reference current [3].
margin are designed using a PI controller. This low BW From the variants of control schemes for improved dynamic
voltage loop is a typical design to avoid input current distortion performance in PFC converters presented in the literature
due to the 100 Hz output voltage ripple. (compared in Table 3), it is evident that an improved digital
ii. Case (b): Higher voltage loop BW: The current controller is algorithm is imperative for improved performance with minimal
designed for the same specifications as case (a). The voltage implementation burden. Therefore, the proposed algorithm for the
loop is designed for higher BW of 30 Hz (six times of that in estimation of the average value of the sensed output voltage signal
case (a)) and 60° phase margin. is presented and is detailed in the next section.

The Bode plots of the uncompensated current loop transfer 3 Proposed algorithm
function T uc(s), current controller Gcc(s) and compensated current
loop transfer function T cc(s) are given in Fig. 2a. In this section, the proposed algorithm for estimation of the
average of the sensed output voltage is derived and its performance
The Bode plots of the uncompensated voltage loop transfer
is verified with simulation results. A boost PFC converter
function T uv(s), voltage controller Gcv(s), and compensated voltage
operating in CCM is considered. The proposed algorithm is
loop transfer function T cv(s) are given in Figs. 2b and c for the implemented in the ‘V o avgEstimation’ block before the
designed voltage controllers for case (a) and case (b), respectively. computation of the output voltage error as shown in Fig. 5. The
The steady state and dynamic performance with the quantities ii(t), vi(t) and vo(t) are sampled once every switching
conventional control for case (a) and case (b) are analysed with
frequency as usual, to obtain the signals ii[n], vi[n] and vo[n]. The
help of simulation results. The output of voltage controller with
higher BW, i.e. case (b) depicts a higher magnitude 100 Hz ripple output voltage waveform vo(t) with the double-line frequency
compared to case (a) as shown in Fig. 3. The impact of the same on ripple is illustrated in Fig. 6.
the steady-state input current and dynamic performance is observed The following assumptions are made for further discussions:
for case (a) and case (b) in Fig. 4. The voltage loop with higher
BW (case (b)) gives a good dynamic performance with a distorted i. The current loop controller (linear controller, predictive or
input current, whereas a voltage loop with low BW gives a low non-linear controller) is designed suitably to make the inductor
THD input current but a poor dynamic performance as shown in current accurately track the reference current.
Table 2. ii. It is further assumed that, as a consequence of the previous
The distortion in the input current in case (b) with conventional assumption, the input current ii(t) is sinusoidal and in phase
control is caused due to the very presence of 100 Hz component in with the sinusoidal input voltage vi(t).
the output voltage. This is because the double-line frequency

Table 1 Specifications of boost PFC converter

Parameter Specification
input AC voltage range, V i 90–260 V
nominal input AC voltage range, V i, nom 230 V
input line frequency, f L 50 Hz
nominal DC output voltage, V o 400 V
rated output power, Po, max 300 W
switching frequency, f s 100 kHz
load resistance, Rmin at Po, max 533 Ω
boost inductance, L 2.1 mH
output capacitance, C 360 μF
control scheme controller average current control
Case (a)
PI current controller 5 kHz BW, 70° PM
PI voltage controller 5 Hz BW, 60° PM
Case (b)
PI current controller 5 kHz BW, 70° PM
PI voltage controller 30 Hz BW, 60° PM

Fig. 2 Bode plots for the boost PFC converter for average current control (T uc(s): uncompensated current loop gain, Gcc(s): current controller transfer
function, T cc(s): compensated current loop gain, T uv(s): uncompensated voltage loop gain, Gcv(s): voltage controller transfer function, T cv(s): compensated
voltage loop gain)
(a) 5 kHz BW current loop, (b) 5 Hz BW voltage loop, (c) 30 Hz BW voltage loop

1104 IET Power Electron., 2019, Vol. 12 Iss. 5, pp. 1102-1113

© The Institution of Engineering and Technology 2019
 17554543, 2019, 5, Downloaded from https://ietresearch.onlinelibrary.wiley.com/doi/10.1049/iet-pel.2018.5250 by Readcube (Labtiva Inc.), Wiley Online Library on [01/05/2024]. See the Terms and Conditions (https://onlinelibrary.wiley.com/terms-and-conditions) on Wiley Online Library for rules of use; OA articles are governed by the applicable Creative Commons License
3.1 Analysis of the proposed algorithm an even number. For the explanation of the algorithm, four points
a1, a2, a3, a4 are considered at the instants ta1, ta2, ta3, ta4 in the 100
The objective of the proposed algorithm is to estimate the average
value of the sensed output voltage. The algorithm requires N Hz cycle (say mth cycle) of the output voltage waveform vo(t) as
number of symmetric points in each double-line frequency cycle of given in Fig. 6. These instants will be hereafter referred to as
output voltage waveform. Since symmetric points are required, N is computation instants in each double-line frequency cycle. Each
computation instant is 1/2 f L N seconds apart. At the end of the
first double-line frequency cycle, the output voltage average is
computed as given below:

a1 + a2 + a3 + a4
V o avgta4 = (2)
4

where V o avgta4 is the average of vo(t) at the computation instant ta4.

This value is used for the computation of the average output
voltage in the subsequent computation instant. Hereafter, the output
voltage average is updated at each of the instants ta5, ta6, ta7, ta8 and
so on

V o avgta5 = V o avgta4 − a1 + a5 (3)

V o avgta6 = V o avgta5 − a2 + a6 (4)

V o avgta7 = V o avgta6 − a3 + a7 (5)

Similarly, at the subsequent points, the average output voltage is

computed at each of the computation instants. These computed
average values are used in the voltage feedback loop for evaluating
the voltage error. At steady state, the signal vo est[n] is free from any
line harmonic ripple components. In general, (2)–(5) are
represented at the kth point as (6) and (7).
Fig. 3 Voltage controller output at 230 V input and full load with For the first cycle
conventional average current control for
(a) 5 Hz voltage loop BW, (b) 30 Hz voltage loop BW

Fig. 4 Simulation results for a boost PFC converter at 230 V input with conventional average current control
(a) Steady-state performance at 5 Hz voltage loop BW, (b) Output dynamic performance for 50% step load change at 5 Hz voltage loop BW, (c) Steady-state performance at 30 Hz
voltage loop BW, (d) Output dynamic performance for 50% step load change at 30 Hz voltage loop BW

Table 2 Simulation results with conventional control (Fig. 1) at 230 V input

Case THD, % Settling time, ms Undershoot, V
(a) 2.30 210 21.5
(b) 12.03 43 7.4

IET Power Electron., 2019, Vol. 12 Iss. 5, pp. 1102-1113 1105

© The Institution of Engineering and Technology 2019
 17554543, 2019, 5, Downloaded from https://ietresearch.onlinelibrary.wiley.com/doi/10.1049/iet-pel.2018.5250 by Readcube (Labtiva Inc.), Wiley Online Library on [01/05/2024]. See the Terms and Conditions (https://onlinelibrary.wiley.com/terms-and-conditions) on Wiley Online Library for rules of use; OA articles are governed by the applicable Creative Commons License
Table 3 Comparison of methods to avoid effects of the double-line frequency component
Method Computations Remarks
conventional low BW loop No additional computations Poor output dynamic response
notch filter [16, 17] Minimum four multiplication and addition operations required for Accurate digital design of filter required
the digital notch filter
moving average algorithm [18, One subtraction, one addition, one division, shifting operation at 1. More arithmetic operations than the
19] every computation point. Forbes et al. [19] also require integration proposed algorithm
2. Memory requirements depend on the
length of the window
ripple estimation techniques [3, Implemented in analogue circuitry. External circuit required for ripple
4] estimation and cancellation
Digital implementation is processor time demanding
load current feedforward [13, Minimum one multiplication and addition 1. Load current sensor required
14] 2. Loop design needed and depends on
converter topology
proposed algorithm Two additions and one subtraction (4 instruction cycle each) at 1. Less intensive computation
every computation instant
One division operation (28 instruction cycles) once in each half line 2. No additional sensors or circuitry
cycle 3. No digital design involved
4. Independent of single-phase PFC
topology

Fig. 6 Illustration of vo(t) for (7)

Fig. 5 Digital implementation of average current control with the

proposed algorithm on a boost PFC converter

V o avgtak = vo(tak), for 1 ≤ k ≤ (N − 1)

N (6)
∑i = 1 ai
V o avgtak = , for k = N
N
Fig. 7 Response of (7) for a step input signal with N = 4
For subsequent cycles

V o avgtak = V o avgtak − 1 − ak − N + ak, for all k (i) Accurate average estimation in steady state is to be ensured by
(7)
the algorithm.
(ii) Zero steady-state error after a transient.
The average computation by (7) in the proposed algorithm is valid
(iii) Less computationally intensive.
during the steady-state operation of the converter. The average
computation involves one division operation in the beginning and
Equation (7) satisfies conditions (i) and (iii) of above. Equation
one addition and subtraction operations at each computation
(7) is modified by computing the N point average at the end of
instants thereafter. The algorithm is computationally less intensive.
every double-line frequency cycle and also this value is used for
The robustness of (7) is verified for transient conditions such as
updating the average at each of the computation instants in the next
a sudden load change or any disturbance input by applying a step
double-line frequency cycle. The modification in the proposed
signal as the input to the algorithm with N = 4. The output of the
algorithm is explained below.
algorithm with such an input signal is shown in Fig. 7.
As explained previously, N points are taken in one double-line
It is seen that (7) responds to the step change in the very next
frequency cycle. This is illustrated in Fig. 8. Let the samples at the
computation instant after the step change has occurred. However,
computation instants be named as a11, a12, a13, a14 for the first cycle
the output settles to a wrong value after the step change. The
algorithm given by (7) is modified to satisfy the following and a21, a22, a23, a24 for the second cycle, and similarly for the
conditions: subsequent cycles. At the instant ta14

1106 IET Power Electron., 2019, Vol. 12 Iss. 5, pp. 1102-1113

© The Institution of Engineering and Technology 2019
 17554543, 2019, 5, Downloaded from https://ietresearch.onlinelibrary.wiley.com/doi/10.1049/iet-pel.2018.5250 by Readcube (Labtiva Inc.), Wiley Online Library on [01/05/2024]. See the Terms and Conditions (https://onlinelibrary.wiley.com/terms-and-conditions) on Wiley Online Library for rules of use; OA articles are governed by the applicable Creative Commons License
a11 + a12 + a13 + a14
V o avgta14 = (8)
4

where V o avgta14 is the average of the first cycle with N = 4. This

value is used at each of the computation instants ta21, ta22, ta23, ta24 in
the subsequent cycle. The average voltage computation and
updation occurs at each of the computation instants within each
double-line frequency cycle

V o avgta21 = V o avgta14 − a11 + a21 (9)

V o avgta22 = V o avgta14 − a12 + a22 (10)

Fig. 8 Illustration of vo(t) for (18)
V o avgta23 = V o avgta14 − a13 + a23 (11)

a21 + a22 + a23 + a24

V o avgta24 = (12)
4

For the next cycle, V o avga24 is used for the computing and updating
the average at each computation instants using the following
equations:

V o avgta31 = V o avgta24 − a21 + a31 (13)

V o avgta32 = V o avgta24 − a22 + a32 (14)

V o avgta33 = V o avgta24 − a23 + a33 (15) Fig. 9 Response of (18) for a step input signal with N = 4

a31 + a32 + a33 + a34 100 Hz cycle, there could be non-sinusoidal output voltage ripple,
V o avgta34 = (16) but the proposed algorithm is self-balancing and hence, within
4
typically two-three ripple frequency cycles, assumption 2 holds
The generalised equation for the average output voltage at the good.
kth point in the mth 100 Hz cycle is given by (17) and (18). The simulations are carried out for a boost PFC converter using
For the first cycle the average current control with the proposed algorithm (18)
enabled. Fig. 10 shows the simulated input current and output
V o avgta1k = vo(ta1, k), for 1 ≤ k ≤ (N − 1) voltage waveforms for a 50% step load change at 230 V AC input,
400 V DC output with 30 Hz BW for N = 4 and N = 16. The PI
N (17) controller parameters used for evaluating the converter
∑i = 1 a1i
V o avgta1k = , for k = N, n = 1 performance with the proposed algorithm are same as case (b) as
N
given in Table 1. It is seen that distortion in the input current at
For the subsequent cycles steady state is minimised compared to the conventional control.
This is evident from the input current THD values given in Table 4
V o avgtamk = V o avgta(m − 1)N − a(m − 1)k + amk, for 1 ≤ k ≤ (N − 1) with 12.03% for conventional control and <2.5% for proposed
control. The time required by the output voltage to reach steady
N (18) state after a transient is found to be higher for lower values of N. At
∑i = 1 ami
V o avgtamk = , for k = N lower values of N, higher input current distortion during transients
N
is observed. This could be attributed to the delay in response by the
algorithm and large changes in the output of the algorithm with low
To verify the robustness of (18), a step signal is applied as input to
N values. It is observed that THD does not significantly vary with
the algorithm in simulation as shown in Fig. 9. The output responds
the choice of N.
to the input within a time delay of 1/2 f LN seconds. It is observed
that, the output signal exhibits an oscillatory response and settles
3.2 Choice of number of points N
within the end of the next double-line frequency cycle with a zero
steady-state error since the input step change occurs in the middle It is detailed in the previous subsection that the modified algorithm
of the 1/2 f L period in this case. If the step change in input occurs given by (18) gives low THD input current waveforms and fast
within 1/2 f LN seconds from the beginning of the mth cycle, then dynamic performance. In each double-line frequency cycle, N
there will be no oscillatory response at the output. Since the points (computation instants) are taken for computation of the
algorithm is employed in PFC converters, the input signal to the average value of output voltage. The choice of the appropriate
algorithm changes at a much slower rate compared to a step signal value of N is important for the effectiveness of the proposed
and hence, the algorithm operation is not degraded. algorithm.
The N point average of the samples obtained at the computation The proposed algorithm is derived assuming symmetric output
instants in each double-line frequency cycle need not be computed voltage ripple. Therefore, only symmetrically computation instants
at the end of each cycle, rather, it is sufficient to compute once in need to be considered. Hence, this places a constraint that N must
few cycles using the points sampled at the computation instants in be an even number. Since the double-line frequency ripple cycle is
that latest double-line frequency cycle. Equation (18) is divided into N equal spaced segments, the duration of each of these
computationally simple and the algorithm is evaluated N times in segments should not be a recurring decimal. From the simulation
each double-line frequency cycle. results, it is noted that during transients, there is distortion in the
Assumption 2 made initially is valid provided the ripple from input current waveform immediately after the load change for
the output voltage entering into the feedback loop is a symmetrical lower values of N. This is because the computation of average
waveform. This is ensured by the proposed algorithm. For the first voltage is performed N times in a double-line frequency cycle.

IET Power Electron., 2019, Vol. 12 Iss. 5, pp. 1102-1113 1107

© The Institution of Engineering and Technology 2019
 17554543, 2019, 5, Downloaded from https://ietresearch.onlinelibrary.wiley.com/doi/10.1049/iet-pel.2018.5250 by Readcube (Labtiva Inc.), Wiley Online Library on [01/05/2024]. See the Terms and Conditions (https://onlinelibrary.wiley.com/terms-and-conditions) on Wiley Online Library for rules of use; OA articles are governed by the applicable Creative Commons License
Fig. 10 Simulation results showing the dynamic response for a boost PFC converter with 30 Hz BW voltage loop at 230 V input for 50% step load change
using the proposed algorithm with
(a), (b)N = 4 points, (c), (d) N = 16 points

Table 4 Input current THD from simulation results (at 230 V input, full load, 30 Hz BW)
Control method THD, %
conventional average current control 12.03
average current control with the proposed algorithm, N = 4 2.22
average current control with the proposed algorithm, N = 8 2.22
average current control with the proposed algorithm, N = 16 2.22

Hence, if N is low, the computed average value vo est[n] changes conventional control. The experimentally obtained results are
less number of times (N times) and each change in vo est[n] is large summarised in Table 5.
during transients. This causes sudden and larger changes in iref [n]
which distort the input current waveform. Therefore, a higher value 4.1 Conventional average current control
of N is preferred. The designed 300 W PFC boost converter prototype shown in
The criteria for choice of N is summarised below: Fig. 11 is operated with conventional control and the results are
presented in this subsection. The steady-state waveforms when the
i. N is an even number. N = 2p, where p = 1, 2, 3, …. converter is operated at 230 V input, full load condition with case
ii. 1/2 f LN is a non-recurring decimal. (a) 5 Hz voltage loop BW and case (b) 30 Hz voltage loop BW
iii. Higher N preferred for better input current waveform during using conventional control is shown in Figs. 12a and c. The
transients. dynamic performance when the converter is subjected to a 50%
load increase with case (a) and case (b) using conventional control
For f L = 50 Hz, the possible values of N are 4, 8, 10, 16, 20 etc. at 230 V input is given in Figs. 12b and d.
N = 16 is a reasonable choice considering the input current quality It is observed from Figs. 12a and b that, at 5 Hz BW, the input
during transients and typical processor memory requirements for current distortion is low at <5%, however, the dynamic
hardware implementation. The proposed algorithm is implemented performance is poor with settling time of about 213 ms. With a
on a 300 W boost PFC converter and the experimental results are higher voltage loop BW, the output dynamic response (Fig. 12d) is
presented in the next section. much faster with settling time of ∼46 ms. The input current
distortion is higher with 12.40% THD (Fig. 12c) due to the
presence of the third harmonic component in the input current as a
4 Experimental results and discussion
result of the higher voltage loop BW. To achieve the improved
In this section, the proposed algorithm for average output voltage steady-state input current waveforms and good dynamic
estimation is validated by experimental results obtained from the performance, the proposed algorithm is employed. The
300 W boost PFC converter prototype shown in Fig. 11 and the experimental results with the proposed algorithm are presented in
performance is compared with the conventional average current the next subsection.
control. The specifications of the experimental prototype are the
same as that given in Table 1. For a digital implementation, the 4.2 Average current control with the proposed algorithm
Texas Instruments TMS320F28335 DSP, which has a system clock
of 150 MHz is used. The dynamic response under a step load The 100 Hz component in vo(t) leads to distorted input current in
change and the steady-state figures of merit such as THD and case (b) design with conventional control. The designed 300 W
power factor at the salient operating conditions are experimentally boost PFC converter prototype shown in Fig. 11 is operated with
obtained with the proposed algorithm (given by (18)) and the proposed algorithm given by (18) enabled in the voltage loop

1108 IET Power Electron., 2019, Vol. 12 Iss. 5, pp. 1102-1113

© The Institution of Engineering and Technology 2019
 17554543, 2019, 5, Downloaded from https://ietresearch.onlinelibrary.wiley.com/doi/10.1049/iet-pel.2018.5250 by Readcube (Labtiva Inc.), Wiley Online Library on [01/05/2024]. See the Terms and Conditions (https://onlinelibrary.wiley.com/terms-and-conditions) on Wiley Online Library for rules of use; OA articles are governed by the applicable Creative Commons License
Fig. 11 300 W boost PFC converter hardware prototype with the TMS320F28335 DSP board

Table 5 Summary of observations from experimental results

Control method/ Operating condition Observations
experimental test ii(t) THD (at full Power factor (at vo(t) settling time vo(t) undershoot (50%
load), % full load) (50% step load step load change), V
change), ms
conventional average 230 V input, 5 Hz BW 3.77 0.997 213.0 23.00
current control (Fig. 12) 230 V input, 30 Hz BW 12.40 0.979 46.0 10.60
average current control with 230 V input, 30 Hz BW, N = 2.98 0.998 50.0 10.62
proposed algorithm 4
(Figs. 13–15) 230 V input, 30 Hz BW, N = 2.85 0.998 48.0 10.60
8
230 V input, 30 Hz BW, N = 2.79 0.998 46.6 10.60
16
wide input variation 90–260 V input, full load lower THD with the proposed algorithm at lower and higher BWs
(Figs. 16 and 17a)
wide load variation 230 V input, 50–100% load, lower THD and higher power factor with the proposed algorithm
(Figs. 17b and c) 30 Hz BW
various BW designs 230 V input, full load lower THD with the proposed algorithm
(Fig. 17d)
proposed algorithm validity 230 V input, full load, 30 Hz no steady-state error under small output voltage ripple
(Figs. 18a and b) BW, 360 µF
230 V input, full load, 30 Hz no steady-state error under large output voltage ripple
BW, 180 µF

for eliminating the effect of double-line frequency ripple 4.2.2 Dynamic performance: The dynamic performance of the
component in the voltage loop. The experimental results with converter operated with the proposed algorithm is given in Fig. 15
average output voltage estimation using the proposed algorithm is for various values of N at 30 Hz BW when the converter is
presented in this subsection for analysing the converter subjected to a 50% load change at 230 V input.
performance in steady state, dynamic conditions and under wide The time required by vo(t) to settle to its final steady-state value
operating conditions. is ∼50 ms for N = 4, about 48 ms for N = 8 and 46.6 ms for N = 16,
respectively. For N = 4, the input current during transients has a
4.2.1 Steady-state performance at nominal condition: The sudden jump as indicated in Fig. 15a. This is due to large changes
experimental results at steady state for the boost PFC converter in the estimated value of average output voltage when there are few
operated with the average current mode control along with the computation instants in the proposed algorithm. It is observed as
proposed algorithm at 30 Hz BW with 230 V input and full load for the value of N increases, distortion in ii(t) during the transient
N = 4, N = 8 and N = 16 are given in Figs. 13a–c, respectively. period decreases. A large N implies that the change in sensed
The harmonic spectrum of the input current obtained by employing voltage seen by the algorithm at each computation instant is small
conventional average current control and the average current and hence, there is a smooth variation in the algorithm output. For
control with the proposed algorithm at 230 V input and full load is N = 8 and N = 16, ii(t) waveform during the transient duration is
shown in Fig. 14. improved compared to N = 4 condition as shown in Fig. 15.
The input current THD obtained with the proposed algorithm is
much lower compared to that obtained from the conventional 4.2.3 Performance under wide operating conditions: The
control and is at 2.79% for N = 16. There is a slight improvement performance analysis is presented for wide input voltage variation,
in the input current THD as the value N increases (Fig. 13). A load variation and also for voltage control loop designed for
lower input current THD achieved proves that the proposed various BWs.
algorithm is effective in eliminating the double-line frequency The steady-state converter waveforms with the proposed
component from the sensed output voltage signal by average algorithm under wide input voltage range are verified with an input
estimation. It is seen from Fig. 14 that the third harmonic content voltage of 90 and 260 V at full load as shown in Figs. 16a and b,
in the input current is 22 mA with the proposed algorithm and is respectively. The variation in input current THD for variation in
about 85% lower compared to 156 mA obtained with the input voltage is given in Fig. 17a at full load condition. The input
conventional control. current THD obtained by employing the proposed algorithm is
lower for 5 Hz BW, as well as for 30 Hz voltage loop BW

IET Power Electron., 2019, Vol. 12 Iss. 5, pp. 1102-1113 1109

© The Institution of Engineering and Technology 2019
 17554543, 2019, 5, Downloaded from https://ietresearch.onlinelibrary.wiley.com/doi/10.1049/iet-pel.2018.5250 by Readcube (Labtiva Inc.), Wiley Online Library on [01/05/2024]. See the Terms and Conditions (https://onlinelibrary.wiley.com/terms-and-conditions) on Wiley Online Library for rules of use; OA articles are governed by the applicable Creative Commons License
marginally higher at lower load conditions due to the occurrence of
discontinuous conduction mode (DCM) regions in the inductor
current waveform. A higher input power factor of 0.998 is obtained
at high load conditions using the proposed algorithm.
Fig. 17d shows the variation in input current THD with voltage
loop BW when the converter is operated with conventional control
and the proposed algorithm at 230 V input and full load condition.
The control with the proposed algorithm gives consistently low
THD for the variation in designed BW, which further shows that
the proposed algorithm is effective in eliminating the double-line
frequency component from the sensed output voltage. The input
current THD with the conventional control, however, increases
with voltage loop BW.
In order to verify that the inclusion of the proposed algorithm
with average current control does not cause any steady-state error
in the vo(t), the converter waveforms are observed by changing the
converter control from the conventional control method to the
proposed control method as shown in Fig. 18a. Once the proposed
algorithm is enabled, it takes maximum one half-line cycle
duration to improve the ii(t) waveform. This time is required to
compute the average output voltage in the first double-line
frequency cycle after the algorithm is enabled. Thereafter, the input
current THD reduces, thus obtaining a nearly sinusoidal input
current waveform without affecting the average value of vo(t).
Further, the converter is tested with 180 µF capacitance, which is
half the designed capacitance value, to verify the validity of the
proposed algorithm at a higher magnitude of output voltage ripple.
The experimental result with 180 µF at 230 V input, full load
condition, 30 Hz BW is given in Fig. 18b and it is observed that no
steady-state error occurs when the proposed algorithm is enabled.
Therefore, the proposed algorithm is effective in estimating the
output voltage average value at higher output ripple magnitudes as
well.
The experimental results and inferences are summarised in
Table 5. It is observed from Table 5 that the proposed algorithm is
effective in eliminating the detrimental effects of the double-line
frequency component present on the output voltage.

4.2.4 Digital implementation aspects of the proposed

algorithm: A flowchart depicting the digital implementation of the
proposed algorithm in the TMS320F28335 DSP is given in Fig. 19.
A Timer Interrupt present internally in the DSP is used for
transferring the DSP execution flow at each of the N computation
instants to the function block which performs the computations
required for the proposed algorithm. At each of the m half line
cycles, the proposed algorithm execution flow for the kth interrupt
is shown in the flowchart. A variable sum holds the sum of the
values of output voltage sampled at the computation instants up to
the kth instant in that half cycle. The average voltage estimated at
the kth computation instant is updated for the error computation
and PI voltage controller computation.
The proposed algorithm is implemented in a 150 MHz
TMS320F28335 DSP (6.67 ns instruction cycle). This processor
performs addition/subtraction operations in typically 4 to 5
instruction cycles (minimum 1 instruction cycle) and division
operation requires typically 28 instruction cycles (minimum 24
instruction cycles) [30]. The proposed algorithm requires two
Fig. 12 Experimental results (scale – CH1 (vi(t)): 150 V/div for a and c; addition and one subtraction operations at each computation
200 V/div for b and d, CH2 (ii(t)): 1.5 A/div for a and c; 3 A/div for b and d, instant. One division operation is required once in every half cycle.
CH3 (io(t)): 500 mA/div, CH4 (vo(t)): 50 V/div, time 10 ms/div) for boost This division operation could also be alternatively done once in
PFC converter at 230 V input, full load condition with few half-cycles if a lower rate of updation of the half-cycle output
(a), (b) Conventional control, 5 Hz BW, (c), (d) Conventional control, 30 Hz BW voltage average is sufficient.
A comparison of the features and digital implementation
controller designs. The input current THD is, however, much aspects between the proposed algorithm and the control algorithms/
higher over the entire input voltage range for the conventional schemes presented in the literature [3, 4, 13, 14, 16–19] for
control with 30 Hz BW. This is due to the effect of the double-line removing the double-line frequency component in the voltage loop
frequency component. (to achieve fast dynamic response without affecting current quality)
The input current THD variation and power factor variation is given in Table 3. The proposed algorithm is computationally less
with variation in load is given in Figs. 17b and c, respectively, for intensive and puts minimal additional computation burden in
230 V input and 30 Hz voltage loop BW. As expected, the input digital implementations alongside linear/non-linear/predictive
current THD obtained using the proposed algorithm is lower current controllers for any single-phase PFC topology. It is seen
compared to that obtained by conventional control. The THD is from the experimental results that the proposed algorithm is

1110 IET Power Electron., 2019, Vol. 12 Iss. 5, pp. 1102-1113

© The Institution of Engineering and Technology 2019
 17554543, 2019, 5, Downloaded from https://ietresearch.onlinelibrary.wiley.com/doi/10.1049/iet-pel.2018.5250 by Readcube (Labtiva Inc.), Wiley Online Library on [01/05/2024]. See the Terms and Conditions (https://onlinelibrary.wiley.com/terms-and-conditions) on Wiley Online Library for rules of use; OA articles are governed by the applicable Creative Commons License
Fig. 13 Experimental results (scale – CH1 (vi(t)): 150 V/div, CH2 (ii(t)): 1.5 A/div, CH3 (io(t)): 1 A/div, CH4 (vo(t)): 50 V/div, time 10 ms/div) for boost PFC
converter at 230 V input, full load condition with the proposed algorithm at 30 Hz BW for
(a) N = 4, (b) N = 8, (c) N = 16

Fig. 14 Experimentally obtained input current harmonic spectrum of a boost PFC converter at 230 V input, full load, 30 Hz BW with
(a) Conventional control, (b) Proposed algorithm

Fig. 15 Experimental results (scale – CH1 (vi(t)): 200 V/div, CH2 (ii(t)): 3 A/div, CH3 (io(t)): 500 mA/div, CH4 (vo(t)): 50 V/div, time 20 ms/div) for boost
PFC converter at 230 V input with 50% step load change with the proposed algorithm for
(a) N = 4, (b) N = 8, (c) N = 16

Fig. 16 Experimental results (scale – CH1 (vi(t)): (a) 200 V/div, (b) 150 V/div, CH2 (ii(t)): (a) 3 A/div, (b) 1.5 A/div, CH3 (io(t)): (a) 500 mA/div, (b) 1 A/div,
CH4 (vo(t)): 50 V/div, time 10 ms/div) for boost PFC converter with the proposed algorithm for N = 16, at full load, 30 Hz BW and
(a) 90 V input, (b) 260 V input

effective in average output voltage estimation resulting in 5 Conclusion

improved steady state and dynamic performance while being
simple and less computation intensive. The steady-state input current in PFC converters is affected by the
double-line frequency component in the sensed output voltage,
thereby leading to a low BW voltage loop design which eventually

IET Power Electron., 2019, Vol. 12 Iss. 5, pp. 1102-1113 1111

© The Institution of Engineering and Technology 2019
 17554543, 2019, 5, Downloaded from https://ietresearch.onlinelibrary.wiley.com/doi/10.1049/iet-pel.2018.5250 by Readcube (Labtiva Inc.), Wiley Online Library on [01/05/2024]. See the Terms and Conditions (https://onlinelibrary.wiley.com/terms-and-conditions) on Wiley Online Library for rules of use; OA articles are governed by the applicable Creative Commons License
Fig. 17 Experimental results for boost PFC converter showing a variation of
(a) Input current THD with the input voltage at full load, (b) Input current THD with the load variation at 30 Hz BW, (c) Input power factor with the load variation at 30 Hz BW, (d)
Input current THD with voltage loop BW

Fig. 19 Proposed algorithm flow at the kth timer interrupt in the mth
Fig. 18 Experimental results (scale – CH1 (vi(t)): 150 V/div, CH2 (ii(t)): double-line frequency cycle (for m > 1)
1.5 A/div, CH3 (enable signal): 5 V/div, CH4 (vo(t)): 50 V/div, time 20 ms/
div) showing effect of the proposed algorithm (N = 16) on converter distortion in the input current with higher voltage loop BW
performance for boost PFC converter at 230 V, full load condition, 30 Hz designs.
BW The performance of the proposed algorithm is validated with
(a) With 360 μF capacitance, (b) With 180 µF capacitance simulation and experimental results. A 300 W PFC boost converter
prototype is tested with the conventional average current control
causes the converter to give a poor dynamic performance. and average current control with the proposed algorithm activated.
Achieving low steady-state input current THD and good dynamic The steady-state input current THD is significantly lower at higher
performance is a challenge. In this paper, a less computation BWs with the proposed control as compared to the conventional
intensive, a digital algorithm for estimating the average value of control designed for the same BW. Improved steady-state and
the sensed output voltage is proposed and presented with detailed dynamic performance is obtained for wide variations in line
analysis and results. The equations governing the proposed voltage, load and voltage loop BW designs.
algorithm are derived and the criteria for choosing the number of
computation instants in each double-line frequency cycle is
explained. The estimation of the average value of the sensed output
voltage eliminates the effect of the double-line frequency
component in the feedback loop, thereby achieving reduced

1112 IET Power Electron., 2019, Vol. 12 Iss. 5, pp. 1102-1113

© The Institution of Engineering and Technology 2019
 17554543, 2019, 5, Downloaded from https://ietresearch.onlinelibrary.wiley.com/doi/10.1049/iet-pel.2018.5250 by Readcube (Labtiva Inc.), Wiley Online Library on [01/05/2024]. See the Terms and Conditions (https://onlinelibrary.wiley.com/terms-and-conditions) on Wiley Online Library for rules of use; OA articles are governed by the applicable Creative Commons License
6 References [16] Prodic, A., Chen, J., Maksimovic, D., et al.: ‘Digitally controlled low-
harmonic rectifier having fast dynamic responses’. Proc. APEC Seventeenth
[1] EN 61000-3-2: ‘Harmonic current emissions: guidelines to the standard EN Annual IEEE Applied Power Electronics Conf. and Exposition, Dallas, TX,
61000-3-2 Eur. Power supply manuf. Assoc.’, 2010 USA, 2002, pp. 476–482
[2] Garcia, O., Cobos, J.A., Prieto, R., et al.: ‘Single phase power factor [17] Buso, S., Mattavelli, P., Rossetto, L., et al.: ‘Simple digital control improving
correction: a survey’, IEEE Trans. Power Electron., 2003, 18, (3), pp. 749– dynamic performance of power factor preregulators’, IEEE Trans. Power
755 Electron., 1998, 13, (5), pp. 814–823
[3] Leung, K.H., Loo, K.H., Lai, Y.M.: ‘A family of ripple estimation [18] Ghosh, R., Narayanan, G.: ‘A simple method to improve the dynamic
cancellation methods based on switched-resistor circuits and their application response of single-phase PWM rectifiers’, IEEE Trans. Ind. Electron., 2008,
in fast-response PFC preregulator’, IEEE Trans. Power Electron., 2017, 32, 55, (10), pp. 3627–3634
(4), pp. 2608–2621 [19] Forbes, J., Ordonez, M., Anun, M.: ‘Improving the dynamic response of
[4] Leung, K.H., Loo, K.H., Lai, Y.M.: ‘Unity-power-factor control based on power factor correctors using simple digital filters: moving average filter
precise ripple cancellation for fast-response PFC preregulator’, IEEE Trans. comparative evaluation’. Proc. 2013 IEEE Energy Conversion Congress and
Power Electron., 2016, 31, (4), pp. 3324–3337 Exposition, Denver, CO, 2013, pp. 4814–4819
[5] Wall, S., Jackson, R.: ‘Fast controller design for practical power-factor [20] de Castro, A., Zumel, P., Garcia, O., et al.: ‘Concurrent and simple digital
correction systems’. Proc. of the IECON ‘93, Maui, HI, 1993, pp. 1027–1032 controller of an AC/DC converter with power factor correction based on an
[6] Spiazzi, C., Mattavelli, P., Rossetto, L.: ‘Power factor preregulators with FPGA’, IEEE Trans. Power Electron., 2003, 18, (1), pp. 334–343
improved dynamic response’, IEEE Trans. Power Electron., 1997, 12, (2), pp. [21] Rossetto, L., Spiazzi, G., Tenti, P., et al.: ‘Fast-response high-quality rectifier
343–349 with sliding mode control’, IEEE Trans. Power Electron., 1994, 9, (2), pp.
[7] Lamar, D.G., Fernandez, A., Arias, M., et al.: ‘A unity power factor 146–152
correction preregulator with fast dynamic response based on a low-cost [22] Mohanty, P.R., Panda, A.K.: ‘Fixed-frequency sliding-mode control scheme
microcontroller’, IEEE Trans. Power Electron., 2008, 23, (2), pp. 635–642 based on current control manifold for improved dynamic performance of
[8] Prodic, A., Chen, J., Maksimovic, D., et al.: ‘Self-tuning digitally controlled boost PFC converter’, IEEE J. Emerg. Sel. Top. Power Electron., 2017, 5, (1),
low-harmonic rectifier having fast dynamic response’, IEEE Trans. Power pp. 576–586
Electron., 2003, 18, (1), pp. 420–428 [23] Pandey, A., Singh, B., Kothari, D.P.: ‘A simple fast voltage controller for
[9] Dranga, O., Chu, G., Tse, C.K., et al.: ‘Stability analysis of two-stage PFC single-phase PFC converters’. Proc. IEEE 2002 28th Annual Conf. of the
power supplies’. Proc. IEEE Power Electronics Specialists Conf., Jeju, 2006, Industrial Electronics Society, IECON 02, Sevilla, Spain, 2002, pp. 1235–
pp. 1–5 1237
[10] Wu, T.-F., Liang, S.-A., Chen, Y.-K.: ‘High-power-factor single-stage [24] Yang, Z., Paresh, C.S.: ‘A novel technique to achieve unity power factor and
converter with robust controller for universal off-line applications’, IEEE fact transient response in AC-to-DC converters’, IEEE Trans. Power
Trans. Power Electron., 1999, 14, (6), pp. 1078–1085 Electron., 2001, 16, (6), pp. 764–775
[11] Siu, K.W., Lee, Y.S., Tse, C.K.: ‘Analysis and experimental evaluation of [25] Chiang, H., Lin, F., Chang, J., et al.: ‘Control method for improving the
single-switch fast-response switching regulators with unity power factor’, response of single-phase continuous conduction mode boost power factor
IEEE Trans. Ind. Appl., 1997, 33, (5), pp. 1260–1266 correction converter’, IET Power Electron., 2016, 9, (9), pp. 1792–1800
[12] Wang, X., Ben, H., Meng, T.: ‘An auxiliary flyback circuit with output [26] Park, J.H., Kim, D.J.: ‘Predictive control algorithm including conduction
voltage ripple suppression for single-phase isolated full-bridge boost PFC mode detection for PFC converter’, IEEE Trans. Ind. Electron., 2016, 63, (9),
converter’. Proc. IECON 2017–43rd Annual Conf. of the IEEE Industrial pp. 5900–5911
Electronics Society, Beijing, 2017, pp. 4433–4437 [27] Marcos-Pastor, A., Vidal-Idiarte, E., Cid-Pastor, A., et al.: ‘Interleaved digital
[13] Figueres, E., Benavent, J.M., Garcera, G., et al.: ‘A control circuit with load- power factor correction based on the sliding-mode approach’, IEEE Trans.
current injection for single-phase power-factor-correction rectifiers’, IEEE Power Electron., 2016, 31, (6), pp. 4641–4653
Trans. Ind. Electron., 2007, 54, (3), pp. 1272–1281 [28] Dias, J.C., Lazzarin, T.B.: ‘A family of voltage-multiplier unidirectional
[14] Bai, L., Ren, X., Hui, Q., et al.: ‘Dynamic response optimization for single-phase hybrid boost PFC rectifiers’, IEEE Trans. Ind. Electron., 2018,
interleaved boost PFC converter with improved dual feedforward control’. 65, (1), pp. 232–241
Proc. 2017 IEEE Energy Conversion Congress and Exposition (ECCE), [29] Ridley, R.B.: ‘Average small signal analysis of the boost power factor
Cincinnati, OH, 2017, pp. 5280–5286 correction circuit’, Virginia Power Electronics Seminar, Blacksburg, VA,
[15] Rajagopalan, J., Cho, J.G., Cho, B.H., et al.: ‘High performance control of USA, 1989
single-phase power factor correction circuits using a discrete time domain [30] ‘C28x floating point unit fastRTS library, SPRCA75’ (Texas Instruments,
control method’. Proc. Applied Power Electronics Conf. and Exposition, 2010, V1.00)
Dallas, TX, 1995, pp. 647–653

IET Power Electron., 2019, Vol. 12 Iss. 5, pp. 1102-1113 1113

© The Institution of Engineering and Technology 2019