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Digital Circuits Exercise Sheet 3

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5 views

sheet3_annotated

Digital Circuits Exercise Sheet 3

Uploaded by

shamsmmonem
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Vig 2 VOD Wid a Vin 2 eg Vv, v in | DD Vpp/2 > Wis Figure: 1 1. For the three inverter voltage transfer characteristics (VTC) shown in Fig. 1: - a. Which has r/B=1, r/B>1 and r/B<1? b. Estimate graphically Vin, Viz, Vors Vous Vit c. Hence deduce NMz and NMu. a) Ged for TCA EA oka weover PMOS WIZ B <* CAA LIGA ANOS wed 9 byvic2t CVs, Yon) = GaN pg 0.14 bp) =O049S, a s ga, (Yer Net) = Co.25\ o SAS > L= NYCI? vyyy, r= © sos SFN55) —t Y “AL a 2. Fig. 2 shows two cascaded inverters with their voltage transfer characteristics VTC eurves. NMH and NML for b. If VASVB and VC ote Vel\n Zz Nada, Ors Or Nyp_Va? O \%-Ost YO L VEZO We ZO. Ove f OF VC From S\oRR ws NAZO’ Figure 3 3. By mistake, a student connected a CMOS inverter as shown Fig. 3. IT he/she used acntos nm, We = 500 nm, 4= 0, and y= 1 - What is logical function generated by the circuit? a, b. 9) degenesste. bufer assuppe gros Segurohion ips |= \gp CgL- oO. 5) UepLz0 5 lps ZO ze OSSUMA PSS olf —r ~e u Xe2S 4 Now AYume pd sain —h 2 ing = ee © 2.5-Vyy-—0-S) \os =O Ve 2 00 4. A CMOS inverter is designed with mnie Vin = V4 = 0, and Vop=2.5 V Note that a. What is the inverter gate switching threshold voltage Vu? b. By what factor would the pMOS width multiplied to get an optimun{ Vn} en S —_ noise margin point of view? OSA 2) fiw =3rid PO Woere mm ¥ o)_ los TON Vout yp =05V.2 . + cS e ovid chee assumnalinn . 2 SDs = aCVin ~ an) CQs—Yinp = Vert) Y rn = Vo! = Vout) ( ‘D avis =O ngs Jue 4 o4V US\ _ 2 S La Ores he hn Fn 235 Woz OAV) Nowti= Voc, I~ § Cv. DSA my} 7 4 AX Spor SC 2.S—\y) SDp Vin FAV vn Vine soos oa Vigne neds $C) Nin= Suateinty 5. Fig 4 shows two implementations of MOS inverters. The first inverter uses only NMOS) transistor fF/um’. Vs, a. Calculate Vor, Vor, Vor for each case, b. Compare the two inverters in terms of noise margin. Vp" 25V M: | Vv al M Vv (a) ‘WIL=0.3750.25 Vour WIL=0.750.25 vge? aN Nov ~ 2su —d Vo 4 | ov Figure. 4 Vs, C= 0.86 Vpn" 2.5V, asv Mg W/L=0.7510.25 vey sy M; W/L=0.375/0.25 Vv (>) a) be Magy een Uy oats Guha OSUMmLE MOS “SORTS stoma FHS 9 = Al CZS-0-S MESVowh) Ss dec +Kasos5 | 2 Vout, 5° Vout = 25\ 2su __| Vi Ww o wx — lp= es asia aNESs deeptyads “ + . \ = = e —O% 1 Sk eRe fOr + BSed...0.345 Nes WAV = OE OSS B ‘) 280 J AO-FS asv j My OTS, M2 Saturation Ee za int ‘IpgeO= 2K, (AS =Nad)~08) af yy New, =2n Nag = OS —L = N b vow} ; J . Z \! = —-V —O (Nok =Ol ee Vonks Ry soma over Os Zen CV iO s) ~ 2K _ [@s anys, Vnwvot | Ug = 25] VN 6. For the resistor-load inverter shown in Fig. 5, Vrs =0.5 V, tin = 800 cm*/Vs, Cx = 0.86 fF /jun?, Cp = Ca=Cs=104F jum and 2= 0. a. Choose a value qe that b. What is the value of Vou? c. Compare the inverter to a conventional CMOS inverter in terms of noise margin. . Comment on the effect of the R, value on the noise margin and area of the inverter. WL= 1510.5 Figure. 5 as Ja when Vin 25 agund Pa WA Wide o.2 Vv TyeLaVol = 2:5 “6 E Que Gay Qs 29325 QL Vea wn uy 0 Pro GrKr Tos =O VeeeS ) - B_ Whee OS 0

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