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PDF&Rendition=1

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Sagar Halkarni
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School of Electronics & Communication Engineering

EC- VLSI DESIGN AND TECHNOLOGY - V SEM


MINOR –II TIME TABLE DEC 2024
Date Exam Timings Subject
16-12-2024 8.30 am to 9.45 am CMOS
(Monday)
1.30 pm to 2.45 pm EFW
17-12-2024 8.30 am to 9.45 am Control System
(Tuesday) 3.00 pm to 4.15 pm ML
8.30 am to 9.45 am AICD
18-12-2024
3.00 pm to 4.00 pm (Vikas)-Arithmetical
(Wednesday)
Thinking &
Analytical Reasoning
19-12-2024 8.30 am to 9.45 am DSP Architecture
(Thursday)
12.15 pm to 1.30 pm MATHS
(Lateral Entry)

NOTE:

1) Only calculators are permitted; no other electronic devices should be brought into the exam hall.

2) For the 'Vikas' exam, calculators are also not allowed.

3) Students are required to be seated in roll number order at least 15 minutes prior to the start of the exam.

CoME HOS

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