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ALU

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1 views

ALU

Uploaded by

gladysvera12380
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Date: April 12, 2024 ALU.

v Project: ALU

1 //programa principal //
2 module ALU(
3 input [3:0] A,
4 input [3:0] B,
5 input [2:0] C,
6 output [3:0] S,
7 output Cout);
8
9 wire [3:0] and1,orex2,comp10,suma,op1,op2;
10 wire co1,co2,co3;
11
12 assign and1 = A & B;
13 assign orex2 = A ^ B;
14 //complemento a 10//
15 fulladd4 fac10 (~B,4'b1011,1'b0, comp10, co1);
16 //suma a+b//
17 fulladd4 fasum (A, B, 1'b0, suma, co3);
18 //operacion aritmetica//
19 fulladd4 faop1 (B, 4'h1, 1'b0, op1, co1);
20 fulladd4 faop2 (A,~op1,1'b1,op2,co1);
21 // mux de seleccion //
22 mux8_1 allu (C,and1,orex2,comp10,suma,op2,4'h0,4'h0,4'h0,S);
23 assign Cout = co3;
24 endmodule
25
26
27 module mux8_1(
28 input [2:0] vs,
29 input [3:0] I0,
30 input [3:0] I1,
31 input [3:0] I2,
32 input [3:0] I3,
33 input [3:0] I4,
34 input [3:0] I5,
35 input [3:0] I6,
36 input [3:0] I7,
37 output reg [3:0] M);
38
39 always @(vs, I0,I1,I2,I3,I4,I5,I6,I7)
40 case (vs)
41 3'h0: M = I0;
42 3'h1: M = I1;
43 3'h2: M = I2;
44 3'h3: M = I3;
45 3'h4: M = I4;
46 3'h5: M = I5;
47 3'h6: M = I6;
48 default: M = I7;
49 endcase
50 endmodule
51
52 module fulladd4(
53 input [3:0] a,
54 input [3:0] b,
55 input cin,
56 output [3:0] s,
57 output co);
58
59 wire co1,co2,co3;
60
61 fulladd1 fa0 (a[0], b[0], cin, s[0], co1);
62 fulladd1 fa1 (a[1], b[1], co1, s[1], co2);
63 fulladd1 fa2 (a[2], b[2], co2, s[2], co3);
64 fulladd1 fa3 (a[3], b[3], co3, s[3], co);
65
66 endmodule

Page 1 of 2 Revision: ALU


Date: April 12, 2024 ALU.v Project: ALU

67
68
69 module fulladd1(
70 input a,
71 input b,
72 input cin,
73 output s,
74 output cout);
75 assign s = a ^ b ^ cin;
76 assign cout = a & b | a & cin | b & cin;
77
78 endmodule
79

Page 2 of 2 Revision: ALU

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