LM3842A (1)
LM3842A (1)
Vcc
5V
VREF ⑧ Reference
Undervoltage
Lockout
R
VREF
Undervoltage
R Lockout ⑦ Vcc
RT/CT ④ Oscillator
Latching ⑥ Output
PWM
+
VFB ② - ⑤ Ground
Error
Amplifie ③ Current
COMP ① r
Sense
Input
HTC
−2−
CURRENT MODE PWM CONTROLLER LM3842A/3A/4A/5A
Note: 1. Adjust Vcc above the start threshould before setting at 15V.
2. Parameter measured at trip point of latch with VFB - 0.
3. Comparator Gain defined as:
A = ΔV Output Compensation(pin FB) ;
ΔV Current Sanseinput(pin CS)
VREF
RT
2N
4.7K 2222 A
V1
1 COMP VREF 8
100K 0.1
1K
E/A 2 VFB VC 7 1K/1W
ADJUST
5K
LM3842A 0.1
ISENSE ISENSE
3 OUTPUT 6
ADJUST
OUTPUT
4.7K
4 RT/CT GND 5
CT
High peak currents associated with capacitive loads necessitate careful grounding techniques
Timing and bypass capacitors should be connected close to pin 5 in a single point ground.
The transistor and 5KΩ potentiometer are used to sample the oscillator waveform and apply an
adjustable ramp to pin 3.
LM3842A LM3843/5A
< 15mA
VON 16V 8.4V
VOFF 10V 7.6V
< 1mA
VCC
VOFF VON
During Under-Voltage Lock-Out, the output driver is biased to a high impedance state.
Pin 6 should be shunted to ground with a bleeder resistor to prevent activating the power switch
with output leakage current.
HTC
−3−
CURRENT MODE PWM CONTROLLER LM3842A/3A/4A/5A
Fig.3 Error Amp Configuration 2.5V
0.5mA
VFB
Zi 2 -
Zf 1
COMP
COMP R 1V CURRENT
1 SENSE
CURRENT
SENSE COMPARATOR
R
3
C
RS
GND
5
IS(MAX) ~ 1.0V
RS
RT
INTERNAL CLOCK
RT/CT 4
CT LARGE RT
SMALL CT V4
GND 5
INTERNAL CLOCK
HTC
−4−
CURRENT MODE PWM CONTROLLER LM3842A/3A/4A/5A
duty cycle. Charge and discharge times are determined by the formulas:
tc ~ 0.55 RT CT
0.0063 RT - 2.7
td ~ RT CT ∫n( )
0.0063 RT - 4
Frequency, then, is: f = (tc + td) -1
1K
8 VREF
1 COMP
330Ω 3 ISENSE
SHUTDOWN
500Ω
SHUTDOWN
TO CURRENT
SENSE-RESISTOR
Shutdown of the LM3842A can be accomplished by two methods; either raise pin 3 above 1V or
pull pin 1 below a voltage two diode drops above ground. Either method causes the output of the
PWM comparator to be high (refer to block diagram). The PWM latch is reset dominant so that
the output will remain low until the next clock cycle after the shoutdown condition at pins 1 and/or 3
is removed. In one example, an externally latched shutdown may be accomplished by adding an
SCR which will be reset by cycling VCC below the lower UVLO threshold. At this point the
reference turns off, allowing the SCR to reset.
VREF 8
0.1μF
RT
RT/CT 4
LM3842A
CT
R1 ISENSE
R2
ISENSE 3
RSENCE
C
HTC
−5−
CURRENT MODE PWM CONTROLLER LM3842A/3A/4A/5A
A fraction of the oscillator ramp can be resistively summed with the current sense signal to
provide slope compensation for converters requiring duty cycles over 50%.
Note that capacitor, C, forms a filter with R2 to suppress the leading edge switch spikes.
80 CT=100nF
RT, Timing Resister (kΩ
50 CT=200pF
CT=47nF
CT=10nF CT=100pF
30
CT=5.0nF CT=22nF
RT(kΩ)
20 CT=2.0nF
CT=1.0nF CT=10nF
8.0 CT=500pF
CT=4.7nF
5.0 10
2.0 CT=2.2nF
CT=10nF
0.8
10k 20k 50k100k 200k 500k 1.0M
3
fosc, Frequency (kHz) 100 1k 10k 100k 1M
fosc, Frequency(Hz)
80 0
VSAT, Output Saturation Voltage (V
4
Gain
40 -90
2 Phase
20 -135
1 SOURCE (V
CC-VOH)
SINK (VOL)
0 -180
0
10-3 2 4 6 8 10-1 2 4 6 8
HTC
−6−