DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

(CYBER SECURITY)

Certified that this is a bonafied record of work done

by Selvan / Selvi______________________________________ SPR No.____________

of________________Semester_____________________________________Department

for_______________________________________________________________________

in the academic year _________________________

Staff –in – charge Head of the Deportment

Reg. No.

Submitted for the University Practical Examination held on ____________________

Internal Examiner External Examiner

 ACADEMIC YEAR 2024 – 2025 ODD SEMESTER

Department Name CSE (CYBER SECURITY)

Year & Semester II & 3rd Semester
Name of the Lab Course DIGITAL PRINCIPLES AND COMPUTER ORGANIZATION
Name of the Evaluator Mrs.M.Saranya ,AP/ Cyber
Name of the Student
Marks Scored out of 40

RUBRICS ASSESSMENT FOR LAB COURSE

Performance Index (PIs)

Performance Factors Level 1 Level 2 Level 3 Level 4
PIs
/ Description 1 Mark 2 Marks 3 Marks 4 Marks

The fundamental The fundamental The fundamental The fundamental

understanding of understanding of pre- understanding of understanding of
Basic Knowledge of pre-lab questions lab questions and pre-lab questions and pre-lab questions and
PI-1
the Experiment and objectives of objectives of the objectives of the objectives of the
the exercise is not exercise is Partially exercise is exercise is Highly
Satisfactory Satisfactory Satisfactory Satisfactory

The fundamental The fundamental The fundamental The fundamental

understanding of understanding of understanding of understanding of
program like program like algorithm, program like program like
Writing Code /
PI-2 algorithm, flowchart flowchart and algorithm, flowchart algorithm, flowchart
Program
and execution of the execution of the and execution of the and execution of the
exercise is not exercise is Partially exercise is exercise is Highly
Satisfactory Satisfactory Satisfactory Satisfactory
Test Case of the Test Case of the
Test Case of the Test Case of the
program feed to the program feed to the
program feed to the program feed to the
input from low, input from low,
Test Case input from low, input from low,
PI-3 average and high average and high
Verification average and high average and high
values of the values of the exercise
values of the exercise is values of the exercise
exercise is not is Highly
Partially Satisfactory is Satisfactory
Satisfactory Satisfactory
Viva voce / Oral Viva voce / Oral Viva voce / Oral Viva voce / Oral
Viva voce / Oral presentation of the presentation of the presentation of the presentation of the
PI-4
Presentation exercise is not exercise is Partially exercise is exercise is Highly
Satisfactory Satisfactory Satisfactory Satisfactory
Awareness of the Awareness of the usage Awareness of the Awareness of the
Usage of this
usage of this of this exercise into usage of this exercise usage of this
experiment into the
PI-5 exercise into the the real time into the real time exercise into the real
Real Time
real time application application is Partially application is time application is
Application
is not Satisfactory Satisfactory Satisfactory Highly Satisfactory
 ASSESSMENT SHEET
Ex. PI- PI- PI- PI- PI- staff
Date Name of the experiment Total sign
No. 1 2 3 4 5
(a)Study of logic gates
(b)Verification of Boolean
1
theorems using logic gates
Average
Design and implementation of
2 Combinational circuits using
Gates for Arbitrary functions
Design and implementation of half
3
/ full adder and subtractor
Design and implementation of
4
code converters using logic gates
(a)Design and implantation of 4-
bit binary adder/subtractor
(b)Implementation of BCD adder
5 (c)Implementation of Encoder
(d)Implementation of Decoder
Average
Implementation of functions using
6
Multiplexers
Design And Implementation Of
7
Synchronous Counters
Implementation Of Universal Shift
8
Register
Simulator based study of
9
Computer Architecture
Total marks

Internal Marks = (Total marks / No. of experiment) X 2

Marks Scored out of 40 =

Signature of the Evaluator

Ex no: 01 (a)
STUDY OF BASIC GATES
Date:

AIM:

To study the functions of the basic logic gates.

SOFTWARE REQUIRED:

Logisim Tool – Logisim is an open-source program that helps you make and simulate logic circuits.

THEORY:
The basic elements that make up a digital system are Logic Gates. The most common gatesare
AND, OR, NOT, NAND, NOR, EX-OR and EX-NOR gates. The NAND and NOR gates are called as
the universal gates because all the other gates can be implemented using these two gates. A simple logic
element whose binary output is a Boolean function (AND, OR...) of the input is known as a GATE.

PROCEDURE:
1. Make connections as per the logic diagram by clicking the Gates and drop in the workspacethose
needed gates in the given workspace.
2. Give inputs as per truth table.
3. Verify the corresponding outputs for the given inputs, using the truth table of AND gate.
4. Verify the truth tables for all the other gate.

BOOLEAN FUNCTION:
AND GATE:
In AND gate, the output Y is the product of the two inputs A and B. Hence, even if one input is
zero, the output becomes zero. If both the inputs are equal to one then the output is also one.

SYMBOL: Y= A. B
OR GATE:
In OR gate, the output Y is the sum of the two inputs A and B. Hence, even if any one of the input si
one or both the input is one the output becomes one. The output becomes zero only when both the inputs
are zero.
OR GATE: Y= A + B

NOT GATE:
In NOT gate, the output Y is the complement of the input A. Hence, the output is one when
the input is zero and vice versa.

Y = A'
NOT GATE:
SYMBOL:

NAND GATE:
In NAND gate, the output Y is the complement of the product of two inputs A and B. Hence,
the output is one if any one of the input is zero. The output is zero if both the inputs are one.
SYMBOL: Y = (A B)’
NOR GATE:

In NOR gate, the output Y is the complement of the sum of two inputs A and B. Hence, if
anyone of the input is one, the output is zero and if both inputs are zero, the output is one.

Y = (A + B)’

EXCLUSIVE OR GATE:
In EX-OR gate, the output Y is zero when both the inputs A and B are same (Both are zero
or bothare one) otherwise the output is one.

Y=A B
SYMBOL:

EXCLUSIVE NOR GATE:

In EX-NOR gate, the output Y is one when both the inputs A and B are same(Both are
zero orboth are one) otherwise the output is zero.

Y = (A B)’
SYMBOL:

RESULT:

Thus the basic logic gates are implemented and their functions are verified.
Ex no: 01 (b) VERIFICATION OF BOOLEAN THEOREMS USING
Date: BASIC GATES

AIM:

To draw the logic diagram and write the truth table for the following laws and rules of
Boolean algebra and verify the truth table.

SOFTWARE REQUIRED:

Logisim Tool – Logisim is an open-source program that helps to make and simulate logic circuits

PROCEDURE:
1. Give connections as per the logic equation using tool.
2. Give inputs as per truth table.
3. Verify the corresponding truth table.

LAWS OF BOOLEAN ALGEBRA

COMMUTATIVE LAW TAUTOLOGY LAW

(a) A + B = B + A (a) A + A = A
(b) A .B = B. A (b) A A = A
(c) (A + B) + C = A + (B + C) INVOLUTION LAW
(d) (A .B). C = A. (B. C) (a) (A’)’=A
DISTRIBUTIVE LAW ABSORPTION LAW
(a) (B + C) = A. B + A .C (a) A + A B = A
(b) A + (B. C) = (A + B). (A + C) (b) A (A + B) = A
(c) A+A’B=A+B
(d) A(A’+B)=AB

UNION LAW CONSENSUS LAW

(a) 1 + A = 1 (a) AB+A’C+BC=AB+A’C
(b) 0 .A = 0 (b) (A+B).(A’+C).(B+C)= (A+B).(A’+C)
IDENTITY LAW
(a) A+0=A
(b) A.1=A
COMPLEMENTARY LAW
(a) A+A’=1
(b) A.A’=0
DEMORGAN’S LAW
(a) (A+B)’=A’.B’
(b) (AB)’=A’+B’

LOGIC DIAGRAMS:
RESULT:

Thus the laws and rules of Boolean algebra are verified using the logic circuit and the
truth table.
Ex no: 02 DESIGN AND IMPLEMENTATION OF ARBITRARY
Date: FUNCTIONUSING LOGIC GATES

AIM:
To design and implement an arbitrary function using logic gates.

SOFTWARE REQUIRED:

Logisim Tool

PROCEDURE:

1. Give connections as per the logic diagram.

2. Give inputs as per truth table.

3. Verify the corresponding truth table.

FUNCTION:
A = ∑m(11,12)+ ∑d(0,1,2,13,14,15)

K-Map for A

A = X1 X2 + X3 X4 X1
LOGIC DIAGRAM:

TRUTH TABLE:

X3 X2 X1 X0 A
0 0 0 0 X
0 0 0 1 X
0 0 1 0 X
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 1
1 1 0 1 X
1 1 1 0 X
1 1 1 1 x

RESULT:

Thus the arbitrary function is designed and implemented using logic gates.
 Ex no: 03 DESIGN AND IMPLEMENTATION OF HALF / FULL
Date: ADDER AND SUBTRACTOR

AIM:

To design and implementation the following combinational circuits

using logic gates.

A. Half Adder

B. Half Subtractor

C. Full Adder

D. Full Subtractor.

THEORY:

4 BIT BINARY ADDER:

A binary adder is a digital circuit that produces the arithmetic sum

of two binary numbers. It can be constructed with full adders connected in cascade, with the
output carry from each full adder connected to the input carry of next full adder in chain.
The augends bits of ‘A’ and the addend bits of ‘B’ are designated by subscript numbers from
right to left. With subscript 0 denoting the least significant bits. The carries are connected in
chain through the full adder. The input carry to the adder is C0 and it ripples through the full
adder to the output carryC4.

4-BIT BINARY SUBTRACTOR:

The circuit for subtracting A-B consistence of an adder with
inverts, placed between each data input ‘B’ and the corresponding input of full adder. The
input carry C0. Must be equal to 1 when performing subtraction.

4-BIT BINARY ADDER/SUBTRACTOR:

The addition and subtraction operation can be combined into one
circuit with one common binary adder. The mode input M controls the operation. When
M=0, the circuit is adder circuit. When M=1, it becomes subtractor.
PROCEDURE:
1. Connections were given as per circuit diagram.
2. Logical inputs were given as per truth table.
3. Observe the logical output and verify with the truth tables.

HALF ADDER:

TRUTH TABLE:
A B CARRY SUM

0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

K-Map for SUM: K-Map for CARRY:

SUM = A’B + AB’ CARRY = AB

=A B

LOGIC DIAGRAM:
 FULL ADDER

TRUTH TABLE:
A B C CARRY SUM

0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

K-Map for SUM: K-Map for CARRY:

SUM = A’B’C + A’BC’ + AB’C’ + ABC CARRY = AB + BC + AC

= A’ (B’C+BC’) +A (B’C’+BC) =A’BC+AB’C+ABC+ABC’
=A’(B C)+A(B C)’ =AB (C+C’)+C(A’B+AB’)
=A B C

LOGIC DIAGRAM:
 HALF SUBTRACTOR

TRUTH TABLE:
A B BORROW DIFFERENCE
0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0

K-Map for DIFFERENCE: K-Map for BORROW:

DIFFERENCE = A’B + AB’ BORROW = A’B

=A B

LOGIC DIAGRAM:

FULL SUBTRACTOR
TRUTH TABLE:
A B C BORROW DIFFERENCE

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
K-Map for Difference:

Difference = A’B’C + A’BC’ + AB’C’ + ABC

= A’(B’C+BC’)+A(B’C’+BC)
=A’(B C)+A(B C)’
=A B C
K-Map for Borrow:

Borrow = A’B + BC + A’C

LOGIC DIAGRAM:

RESULT:

Thus the half adder, half subtractor, full adder and full subtractor circuits are
designed, implementedand verified successfully.
 Ex no: 04 DESIGN AND IMPLEMENTATION OF CODE
Date: CONVERTERS USING LOGIC GATES

AIM:
To design and implement the following code converters using logic gates.

i. Binary to gray code converter

ii. Gray to binary code converter

iii. BCD to excess-3 code converter

iv. Excess-3 to BCD code converter

SOFTWARE REQUIRED:

Logisim tool
THEORY:
The availability of large variety of codes for the same discrete elements of
information results in the use of different codes by different system. A conversion circuit
must be inserted between the two systems if each uses different codes for same information.
Thus, code converter is a circuits that makes the two systems compatible even though each
different binary code.
The bit combination assigned to binary code to gray code. Since each code use four
bits to represent a decimal digit. There are four inputs and four outputs. Gray code is a non-
weighted code. The input variable are designed as B3,B2,B1,B0 and the output variable are
designated as C3,C2,C1,C0. From the truth table, combinational circuit is designed. The
Boolean functions are obtained from K-map for each output variable.
A code converter is a circuit that makes the two systems compatible even through
each uses different binary code. To convert from binary code to Excess-3 code and the output
lines generate the corresponding bit combination of code. Each one of the four maps
represents one of the four outputs of the circuits as a function of the four input variables.
A two-level logic diagram may be obtained directly from the Boolean expressions
derived by the maps. These are various possibilities for logic diagram that implementation
this circuit.

PROCEDURE:
1. Give connections as per the logic diagram.
2. Give inputs as per truth table.
3. Verify the corresponding truth table.
 BINARY TO GRAY CODE CONVERTER:

K-MAP:

LOGIC DIAGRAM:
 GRAY CODE TO BINARY CONVERTER:

K-MAP:

LOGIC DIAGRAM:
 BCD TO EXCESS-3 CONVERTER

K-MAP:

LOGIC DIAGRAM:
 EXCESS-3 TO BCD CONVERTER:

K-MAP:

LOGIC DIAGRAM:

RESULT:

Thus the code converter was implemented and verified successfully.

 Ex no: 5 (a) DESIGN AND IMPLENTATION OF 4-BIT BINARY
Date: ADDER/SUBTRATOR

AIM:

To design and implement 4-bit binary Adder/Subtractor.

SOFTWARE REQUIRED: LOGISIM TOOL

Logisim tool

THEORY:

4-BIT BINARY ADDER:

A binary adder is a digital circuit’s that produces the arithmetic sum of two binary
members. It can be constructed with full adders connected in cascade, with the output carry
from each full adder connected to the input carry of next full adder in chain. The augends
bits of ‘A’ and the added bits of ‘B’ are designated by subscript numbers from right to left,
with subscript 0 denoting the least significant bits. The carries are connected in chain
through the full adder. The input carry to the adder is C0 and it ripple through the full adder
to the full adder to the output carry C4.
4-BIT BINARY SUBTRACTOR:
The circuit for subtracting A –B consists of an adder with inverters. Placed between
each data input ‘B’ and the corresponding input of full adder. The input carry Co must be
equal to 1 when performing subtraction.
4-BIT BINARY ADDER / SUBTRACTOR:
The addition and subtraction operation can be combined into one circuit with one
common binary adder. The mode input M controls the Operation. When M=0, the circuit is
adder circuit. When M=1, it becomes subtractor.

PROCEDURE:

1. Design a full adder circuit and using this circuit draw the 4 bit binary Adder/
Subtractor circuit using Add Circuit menu under the main circuit
2. Give connections as per the logic diagram.
3. Give inputs as per truth table.
4. Verify the corresponding truth table.
TRUTH TABLE:

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 1 0 1 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

LOGIC DIAGRAM:

EXAMPLE:

X0 = 0 X1 = 0 X2 = 1 Y0 = 1 Y1 = 1 & Y2 = 0 For K=0:

Y0⨁K=Y0 and Cin=K=0 So,
from first Full-Adder
S0 = X0+Y0+Cin
S0=0+1+0
S0=1
C0=0
Similarly,
S1 = X1+Y1+C0 S1 = 0+1+0 S1=1 and C1=0
Similarly,
S2 = X2+Y2+C1 S2 = 1+0+0 S2=1 and C2=0
Thus,
X= 100 =4
Y = 011 = 3
Sum = 0111 = 7
For K=1
Y0⨁K=Y0' and Cin=k=1 So,
S0 = X0+Y0'+Cin S0 = 0+0+1
S0=1 and C0=0
Similarly,
S1 = X1+Y1'+C0 S1 = 0+0+0 S1=0 and C1=0
Similarly,
S2 = X2+Y2'+C1 S2 = 1+1+0 S2=0 and C2=0
Thus,
X = 010 = 4
Y = 011 = 3
Difference = 001 = 1

RESULT:

Thus the 4-bit binary Adder/Subtractor circuit is designed, implemented and verified
successfully.
 Ex no: 5 (b)
IMPLEMENTATION OF BCD ADDER
Date:

AIM:
To implement BCD Adder using logic gates

SOFTWARE REQUIRED:

Logisim Tool
PROCEDURE:

1. Give the Connections as per the logic diagram.

2. Apply the inputs as per the truth table.
3. Verify the outputs for the given inputs.
4-BIT ADDER SYMBOL DIAGRAM:

We are adding “0110” (=6) only to the second half of the table.
The conditions are:
1. If C’ = 1 (Satisfies 16-19)
2. If S3′.S2′ = 1 (Satisfies 12-15)
3. If S3′.S1′ = 1 (Satisfies 10 and 11)
So, our logic is C' + S3'.S2' + S3'.S1' = 1
TRUTH TABLE:
LOGIC DIAGRAM:

RESULT:

Thus the BCD adder is designed and implemented using two 4-bit binary adders
and its output is verified successfully.
 Ex no: 5 (c)
IMPLEMENTATION OF ENCODER
Date:

AIM:
To implement the encoder using logic gates.

SOFTWARE REQUIRED:
Logisim Tool
PROCEDURE:
1. Give the Connections as per the logic diagram.
2. Apply the inputs as per the truth table.
3. Verify the outputs for the given inputs.

THEORY:
The combinational circuits that change the binary information into N output lines are
known as Encoders. The binary information is passed in the form of 2N input lines. The
output lines define the N-bit code for the binary information. In simple words, the Encoder
performs the reverse operation of the Decoder. At a time, only one input line is activated for
simplicity. The produced N-bit output code is equivalent to the binary information.
Block diagram:

4 TO 2 LINE ENCODER:
In 4 to 2 line encoder, there are total of four inputs, i.e., Y0, Y1, Y2, and Y3, and two
outputs, i.e., A0 and A1. In 4-input lines, one input-line is set to true at a time to get the respective
binary code in the output side. Below are the block diagram and the truth table of the 4 to 2 line
encoder.
Block diagram:
TRUTH TABLE:

The logical expression of the term A0 and A1 is as follows:

A1=Y3+Y2
A0=Y3+Y1

LOGICAL CIRCUIT OF THE ABOVE EXPRESSIONS:

RESULT:
Thus the 4:2 encoder is designed and implemented using logic gates and its output
is verifiedsuccessfully.
 Ex no: 5 (d)
IMPLEMENTATION OF DECODER
Date:

AIM:
To implement the decoder using logic gates

SOFTWARE REQUIRED:
Logisim Tool
PROCEDURE:
1. Give the Connections as per the logic diagram.
2. Apply the inputs as per the truth table.
3. Verify the outputs for the given inputs.

THEORY:
The combinational circuit that change the binary information into 2N output lines is
known as Decoders. The binary information is passed in the form of N input lines. The
output lines define the 2N-bit code for the binary information. In simple words, the Decoder
performs the reverse operation of the Encoder. At a time, only one input line is activated for
simplicity. The produced 2N-bit output code is equivalent to the binary information.

2 to 4 line decoder:
In the 2 to 4 line decoder, there is a total of three inputs, i.e., A0, and A1 and E and
four outputs, i.e., Y0, Y1, Y2, and Y3. For each combination of inputs, when the enable 'E'
is set to 1, one of these four outputs will be 1. The block diagram and the truth table of the
2 to 4 line decoder are given below.
TRUTH TABLE:

The logical expression of the term Y0, Y0, Y2, and Y3 is as follows:

Y3=E.A1.A0
Y2=E.A1.A0'
Y1=E.A1'.A0
Y0=E.A1'.A0'

Logical circuit of the above expressions:

RESULT:

Thus the 2 to 4 line decoder is designed and implemented successfully.

 Ex no: 6 IMPLEMENTATION OF FUNCTION USING
Date: MULTIPLEXERS

AIM:
To design and implement multiplexer using logic gates. Also implement Boolean
function using multiplexer IC.

SOFTWARE REQUIRED:
Logisim tool
PROCEDURE:
1. Give connections as per the logic diagram.
2. Give inputs as per truth table.
3. Verify the corresponding truth table.
THEORY:
MULTIPLEXER:
A multiplexer (MUX) is a combinational circuit that takes multiple input signals and
selects one of them to pass as the output, based on a control signal or selection lines.
Essentially, it channels many inputs into one output, determined by the selection lines.
Inputs: A multiplexer typically has 2^n input lines, where n is the number of selection lines.
Selection Lines: The selection lines control which input will be passed to the output. If there
are n selection lines, they can select between 2^n inputs.
Output: A single output, which corresponds to the selected input signal.

4:1 USING LOGIC GATES:

4:1 multiplexer (MUX) is a combinational logic circuit that selects one of the four input
data lines and directs it to a single output line based on the values of two selection lines.
Components of a 4:1 MUX:
4 Inputs: D0, D1, D2, D3
2 Selection Lines: S1, S0
 1 Output: Y
BLOCK DIAGRAM:

FUNCTION TABLE:

TRUTH TABLE:

S1 S0 Y = OUTPUT
0 0 D0
0 1 D1
1 0 D2
1 1 D3

Y=S1’S0’D0+S1’S0D1+S1S0’

LOGIC DIAGRAM:

RESULT:

Thus the 2 to 4 line decoder is designed and implemented using logic gates and its
output is verified successfully.
 Ex no: 7 DESIGN AND IMPLEMENTATION OF
Date: SYNCHRONOUS COUNTERS

AIM:
To design and implement 4-bit synchronous counter using flip flop.
SOFTWARE REQUIRED:
LOGISIM TOOL
THEORY:
SYNCHRONOUS COUNTER:
A synchronous counter is a type of digital counter in which all the flip-flops are
triggered by the same clock signal simultaneously. This is different from asynchronous
counters, where the flip-flops are triggered at different times due to the propagation delay.
Synchronous counter, the clock signal is fed into all the flip-flops at the same time.
As a result, the flip-flops change states simultaneously when a clock pulse is received,
avoiding the ripple effect seen in asynchronous counters. The states of the flip-flops
represent a binary number that counts upwards or downwards depending on the design

4-BIT SYNCHRONOUS COUNTER:

A 4-bit synchronous counter is a type of counter that counts up or down using 4 flip-
flops, typically D or JK flip-flops. Each flip-flop represents one bit, and together, the 4 bits
can represent 16 different states (from 0000 to 1111 in binary, equivalent to 0 to 15 in
decimal).

WORKING PRINCIPLE:
In a 4-bit synchronous counter, all flip-flops are driven by the same clock signal, so
they all change states simultaneously with each clock pulse.
Flip-flop Arrangement:
 Each flip-flop corresponds to a bit in a 4-bit binary number.
 The least significant bit (LSB) is toggled with every clock pulse.
 The next flip-flop toggles when the one before it has completed a full cycle (from 1
to 0).
 The counter will count through a sequence of binary values from 0000 to 1111 (0 to
15 in decimal).
  After reaching 1111 (15 in decimal), the counter will reset to 0000 on the next clock
pulse if it's an up-counter.
DESIGN OF A 4-BIT SYNCHRONOUS UP COUNTER USING JK FLIP-FLOPS:
 Flip-Flops: Use 4 JK flip-flops (or D flip-flops).
 Connections: The clock signal is connected to all the flip-flops.
 For each flip-flop: The J and K inputs are tied to logic high (1) so that the flip-
flop toggles on every clock pulse.
 The first flip-flop toggles with every clock pulse.
 The second flip-flop toggles only when the first one is 1 (i.e., at every second
pulse).
 The third flip-flop toggles when both the first and second flip-flops are 1, and so
on.
BLOCK DIADRAM:

CHARACTERISTICS TABLE:
Q Qt+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
TRUTH TABLE:

K-MAP:
LOGIC DIAGRAM:

4-BIT SYNCHRONOUS UP COUNTER:-

It can be seen above, that the external clock pulses (pulses to be counted) are fed
directly to each of the T flip-flops in the counter chain and that T Flip Flops inputs are all
tied together in toggle mode, but only in the first flip-flop, flip-flop FFA (LSB) are they
connected HIGH, logic “1” allowing the flip-flop to toggle on every clock pulse. Then the
synchronous counter follows a predetermined sequence of states in response to the common
clock signal, advancing one state for each pulse.

T inputs of flip-flop FFB are connected directly to the output QA of flip-flop FFA,
but the T inputs of flip-flops FFC and FFD are driven from separate AND gates which are
also supplied with signals from the input and output of the previous stage. These
additional AND gates generate the required logic for the T inputs of the next stage. If we
enable each T flip-flop to toggle based on whether or not all preceding flip-flop outputs (Q)
are “HIGH” we can obtain the same counting sequence as with the asynchronous circuit but
without the ripple effect, since each flip-flop in this circuit will be clocked at exactly the
same time.
LOGIC DIAGRAM:-
BINARY 4-BIT SYNCHRONOUS DOWN COUNTER:-

As synchronous counters are formed by connecting flip-flops together and any

number of flip-flops can be connected or “cascaded” together to form a “divide-by-n” binary
counter, the module’s or “MOD” number still applies as it does for asynchronous counters
so a Decade counter or BCD counter with counts from 0 to 2n-1 can be built along with
truncated sequences. All we need to increase the MOD count of an up or down synchronous
counter is an additional flip-flop and AND gate across it.

LOGIC DIAGRAM:-

EXCITATION TABLE:-
PROCEDURE:

1. Make connections as per the logic diagram.

2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
4. Give Clock pulse one by one and verify the corresponding outputs for the given
inputs.

RESULTS:

Thus the synchronous up/down counter implemented and verified

successfully
 Ex no: 8 IMPLEMENTATION OF UNIVERSAL SHIFT
Date: REGISTER

AIM:
To design and implement Universal shift register using flip flop.

SOFTWARE REQUIRED:
LOGISIM TOOL
PROCEDURE:
1. Make connections as per the logic diagram.

2. Give input signals.

3. Give Clock pulse one by one and verify the corresponding outputs for the given

inputs using the indication lamps.

THEORY:
A Universal shift register is a register which has both the right shift and left shift
with parallel load capabilities. Universal shift registers are used as memory elements in
computers.
A Unidirectional shift register is capable of shifting in only one direction. A
bidirectional shift register is capable of shifting in both the directions. The Universal shift
register is a combination design of bidirectional shift register and a unidirectional shift
register with parallel load provision.
i. A shift-right control to enable the shift-right operation and the serial input and output
lines associated with the shift-right.
ii. A shift-left control to enable the shift-left operation and the serial input and output
lines associated with the shift-left.
iii. A parallel-load control to enable a parallel transfer and the n input lines associated
with the parallel transfer.
iv. n parallel output lines.
v. A clear control to clear the register to 0.
vi. A CLK input for clock pulses to synchronize all operations.
vii. A control state that leaves the information in the register unchanged even though
clock pulses are continuously applied.
EXCITATION TABLE:

S1 s0 Register operation

0 0 No changes

0 1 Shift right

1 0 Shift left

1 1 Parallel load

DIGITAL LOGIC DIAGRAM:

RESULT:

Thus the 4-bit shift register is designed and implemented using flip flops and its
output is verified successfully.
 Ex no: 9
SIMULATOR BASED STUDY OF COMPUTER
Date: ARCHITECTURE

AIM:
To study the various simulators available for implementing computer architecture.

SIMULATOR TOOL:
LOGISIM TOOL

THEORY:
Logisim is a simple software which can be used for implementing circuits with basic
gates. Users of this simulator can draw the circuits using the tool box available. The circuit
automatically propagates circuit values through the circuit by selecting the suitable tool and
the user can toggle the input conditions to learn how the circuit behaves in other situations.
Students themselves were able to understand how to connect basic gates to make simple as
well as complex circuits with the help of Logisim. With the help of this the user can simulate
the Arithmetic unit and Shift unit of a simple computer. The users can create the complete
circuit with Logisim and can run the simulation with any possible input and this gave an
experience as they were in the lab. Logisim is simple to follow.
CEDAR:
CEDAR is a powerful simulator in which the students can implement a complete
computer and will be able to understand the internal details of a computer more clearly.
Using CEDAR simulator can be used to
1. Build the entire computer hardware using fundamental logic gates.
2. Write an assembler to translate the test program into machine level program.
3. Load the program into the memory of the computer; and
4. Run the test program on the hardware. After the implementation user can see how
computer executes a program and what are the signals generated during each clock
pulse.

CPU SIM:
CPU Sim is an interactive simulation tool in which the user can specify the details
of the CPU to be simulated, such as register set, memory, set of microinstructions, set of
machine instructions and set of assembly language instructions. Users of the tool can write
their own machine or assembly language program and run on the CPU they have created. It
simulates the computer architecture at register transfer level so that the students will get a
better understanding about the system. User of the simulator has to specify the hardware
units and the microinstructions for the CPU and then create the set of machine instructions.
Corresponding to each machine instruction a sequence of microinstructions is to be formed.
Once the instruction set has been specified, students can write programs for their new CPU,
either in machine language or in assembly language. Simulator executes the given program
through repeated execution of machine cycles. Each machine cycle has two parts: Fetch
sequence and Execute sequence. In fetch sequence the next instruction to be executed is
loaded into the instruction register and then decodes it. In the execution sequence, CPU
executes the decoded instruction with the help of microinstruction which has already been
defined.

RESULT:
Thus the simulators such as Logisim, Cedar and CPU Sim available for
implementing computer architecture are explored.