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DS-SE-VHDL-2022

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kadrisami14
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DS-SE-VHDL-2022

Uploaded by

kadrisami14
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Exercice 1 (12 pts)

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

Entity ALU is
Port ( ENTREEA : in std_logic_vector (7 downto 0) ;
ENTREEB : in std_logic_vector (7 downto 0) ;
INALU : in std_logic ;
OPALU : in std_logic ;
START : in std_logic ;
LDFLAG : in std_logic ;
CLK : in std_logic ;
FLAG : out std_logic ;
RESULTAT : out std_logic_vector (7 downto 0));
end ALU ;

architecture arch of ALU is


Signal Temp : std_logic ;
Signal MUX_OUT : std_logic_vector (7 downto 0) ;
Signal FLALU : std_logic ;
Begin
MUX_OUT <= ENTREEB when INALU = ‘0’ else
X”00” ;

RESULTAT<= (ENTREEA + MUX_OUT) when OPALU = ‘0’ else


(ENTREEA – MUX_OUT) ;

FLALU <= ‘1’ when OPALU = ‘1’ else


‘0’ ;

DFF : process(CLK)
Begin
if (CLK’event AND CLK = ‘1’) then
if (START = ‘1’) then
if (LDFLAG = ‘1’) then
Temp <= FLALU ;
else
Temp <= Temp ;
end if;
end if;
end if;
end process ;

FLAG <= Temp ;

End arch;
Exercice 2 (8 pts)

1. Décrire en VHDL comportementale le fonctionnent du circuit compteur. (4pts)

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

Entity compteur is
Port ( H : in std_logic ;
Up : in std_logic ;
Down : in std_logic ;
Compteur_out : out std_logic_vector (3 downto 0));
end compteur ;

architecture arch of compteur is


Signal Temp : std_logic_vector (3 downto 0) := x"0" ;
Begin
Cp : process(H)
Begin
If (H’event AND H = ‘1’) then
if (Up = ‘1’) then
Temp <= Temp + x"1" ;
elsif (Down = ‘1’) then
Temp <= Temp - x"1";
else
Temp <= Temp ;
end if;
end if;
end process ;
Compteur_out <= Temp ;
End arch;

2. Décrire en VHDL comportementale le fonctionnement du circuit comparateur. (4pts)

library ieee;
use ieee.std_logic_1164.all;

Entity comparateur is
Port ( N_max : in std_logic_vector (3 downto 0) ;
Compteur_out : in std_logic_vector (3 downto 0) ;
PC : out std_logic ;
PD : out std_logic ) ;
end comparateur ;

architecture arch of comparateur is


Begin
PC <= ‘1’ when (Compteur_out >= N_max) else
‘0’ ;

PD <= ‘1’ when (Compteur_out < N_max) else


‘0’ ;

End arch;

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