Operating System Fundamentals

Prof. Santanu Chattopadhyay

IIT Kharagpur
Assignment 10 (Week 10)
Q1. Suppose in a three-level paging scheme with 64-bit logical address space, and the page
size is 4KB. The second outer page table size is 16MB, the outer page table size is 4MB, and
the inner page table is 4KB. Assuming that each entry in the page table consists of 4 bytes.
How many bits are required for the second outer page table, outer page table, inner page
table, and page offset?
(A) 32, 10, 10, 12
(B) 22, 20, 10, 12
(C) 42, 05, 05, 12
(D) 32, 15, 05, 12
(E) 12, 20, 20, 12
Ans: (B) 22, 20, 10, 12
The page size is 4KB = 212 bytes. So, the offset is 12. The inner page table size is 4KB =
210x22 bytes. So it needs 10 bits (every entry is of 4 Bytes = 22). The outer page table size is
4MB = 220 x 22 bytes. So it needs 20 bits. The second outer page table size is 16MB = 222 x
22 bytes. So it needs 22 bits.

Q2.

Suppose in a three-level paging scheme with 64-bit logical address space, and the page size is
4KB. The second outer page table size is 16MB, the outer page table size is 4MB, and the
inner page table is 4KB. Assuming that each entry in the page table consists of 4 bytes. If
100ns is needed for memory access, what is the Effective Access Time (EAT) if the hit ratio
is 80% (The percentage of times that a particular page number is found in the TLB)?

(A) 300ns
(B) 160ns
(C) 100ns
(D) 350ns
(E) 400ns

Ans: (B) 160ns

Here, a three-level paging scheme is used. Therefore, the EAT is 0.8 × 100 + (1 − 0.8) × (4 ×
100) = 160ns.
Q3. Suppose a computer system with a 256 bytes main memory runs a process with four
unequal size segments. The process is loaded in the main memory using the following
segment table.
Segment number Base Address (in decimal) Length (in bytes)
0 31 32
1 79 16
2 95 32
3 127 128

If the computer system uses the 9-bit addresses, what is the physical address corresponding
to the logical address 110011001?
(A) 10011000
(B) 10011100
(C) 11100100
(D) 11110100
(E) 11000100
Ans: (A) 10011000
Total number of segments is 4 = 22. Therefore, the initial 2 bits (the two most significant
bits) represent the segment number. If the logical address is 110011001, then the segment
number is 11, i.e., 3. The remaining 7 bits, i.e., 0011001 map to the actual physical
address. The decimal equivalent of 0011001 is 25. Segment 3 has a base address of 127
(decimal). Therefore, 0011001 represents the physical address 127+25 = 152, i.e.,
10011000.

Q4. In the context of the memory management process, the "valid/invalid" bit is used to
(A) signify whether the CPU is currently in a valid operational state
(B) determine if a CPU instruction is valid or invalid
(C) denote whether a particular page or memory segment is currently in the CPU cache
(D) indicate whether a page or memory segment is currently in main memory or not
(E) represent the status of the arithmetic logic unit
Ans: (D) indicate whether a page or memory segment is currently in main memory or not

Q5. Assume that a computer system uses hashed page tables for memory management. The
system has a virtual address space of 16 bits and a physical address space of 12 bits. The
hash function used is:
hash(virtual_page_number) = (virtual_page_number + 3) mod 17
What is the size of the hash table (number of entries), and each entry in the hash table (in
bits)?
(A) Hash table size: 15 entries, Entry size: 28 bits
(B) Hash table size: 17 entries, Entry size: 24 bits
(C) Hash table size: 19 entries, Entry size: 12 bits
(D) Hash table size: 20 entries, Entry size: 20 bits
(E) Hash table size: 17 entries, Entry size: 12 bits
Ans: (E) Hash table size: 17 entries, Entry size: 12 bits
The number of entries in the hash table is 17 (0 to 16, since the mod 17 is used). Each
entry in the hash page table is the address of a physical page. Since the physical address
space is 12 bits, we need 12 12-bit entries in the hash page table.
Q6. Assume that a computer system uses an inverted page table for memory management.
The physical address is the combination of
(A) index of the page table and offset
(B) index of the page table and virtual page number
(C) process id and virtual page number
(D) index of the page table and process id
(E) None of these
Ans: (A) index of the page table and offset

Q7. Assume that a computer system uses an inverted page table for memory management.
The system uses a 16-bit virtual address, and each virtual address is of the form <process id,
virtual page number, offset>. The size of process id, virtual page number, and offset are 4
bits, 6 bits, and 6 bits, respectively. Assume that system uses the physical address of 9 bits.
The page table of the system s given as follows.
Index (3 bits) Process id (4 bits) Virtual page number (6 bits)
000 0000 000000
001 1001 000001
010 0010 000010
011 1011 000011
100 0100 000100
101 1101 000101
110 0110 000110
111 1111 000111
If the CPU generates the virtual address 1101000101111111, what is the corresponding
physical address?
(A) 101111111
(B) 111111111
(C) 000111111
(D) 111111101
(E) 111101111
Ans: (A) 101111111
The virtual address is 1101000101111111. Therefore, pid is 1101. The vpn is 000101, and
the offset is 111111. The pid will give the index in the page table. Here, the pid is 1101, so
it indicates the index is 101. The physical address is <index||offset>, and so 101111111 is
the physical address.

Q8. Assume that a computer system uses 256MB of physical memory and 34-bit virtual
address space. Assuming that each entry in the page table consists of 4 bytes. If the page
size is 4KB, what is the size of the page table?
(A) 1MB
(B) 2MB
(C) 3MB
(D) 4MB
(E) 16MB
Ans: (E) 16 MB
Page size is 4KB = 212 bytes. The offset is 12 bits. The number of entries in the page table is
2(34-12) = 222. If the size of each entry is 4 bytes, then the size of the table is 222 x 22 bytes =
220 x 24 bytes = 16MB
Q9. What is the maximum size of a segment in the IA-32 architecture's 32-bit protected
mode?
(A) 1 MB
(B) 1GB
(C) 4 GB
(D) 8 GB
(E) 16 GB
Ans: (C) 4 GB

Q10. Intel IA-32 architecture supports

(A) 32-bit general-purpose registers
(B) 32-bit physical address space
(C) Two-level paging scheme
(D) segmentation model for memory management
(E) All of the above
Ans: (E) All of the above

Q11. The aspect of using the demand paging scheme is

(A) Efficient memory utilization
(B) enabling processes to have large virtual address spaces
(C) to reduce unnecessary disk I/O operations
(D) to enhance the protection of the physical memory
(E) All of the above
Ans: (E) All of the above

Q12. The ARM-based operating system,

(A) is widely used in smartphones and tablets
(B) is based on the Linux kernel
(C) supports 32-bit ARM cores
(D) supports 4KB to 16MB page size
(E) All of the above
Ans: (E) All of the above

Q13. Which of the following is not a part of the page-fault handling technique?
(A) CPU interrupts the execution of the current process
(B) OS identifies the virtual memory address corresponding to the fault-page
(C) OS verifies whether the virtual memory address is valid and belongs to the process
(D) OS finds the physical location of the page on the secondary storage
(E) The process that experienced the page fault is terminated abnormally
Ans: (E) The process that experienced the page fault is terminated abnormally

Q14. Which of the following is a key benefit of virtual memory management in operating
systems?
(A) Increased disk space utilization
(B) Improved CPU cache performance
(C) Enhanced process isolation and protection
(D) Reduced disk I/O operations
(E) Higher clock speeds for RAM
Ans: (C) Enhanced process isolation and protection

Q15. Which of the following statements is true for a hierarchical (multi-level) paging
scheme?
(A) It utilizes physical memory efficiently.
(B) It reduces the number of entries to be traversed during address translation.
(C) It incurs additional complexity to the page table management process.
(D) It involves additional memory access overhead.
(E) All of the above
Ans: (E) All of the above