Chapter 3

Basic Concept

教師: 陳銘志

Electronic Engineering, NKFUST 1

 Learning Objects
 Understand lexical conventions for operators, comments,
whitespace, numbers, strings, and identifiers.
 Define the logic value set and data types such as nets,
registers, vectors, numbers, simulation time, arrays,
parameters, memories, and strings.
 Identify useful system tasks for displaying and
monitoring information, and for stopping and finishing the
simulation.
 Learn basic compiler directives to define macros and
include files.

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 Lexical Conventions
 Verilog contains a stream of tokens. Tokens can
be comments, delimiters, numbers, strings,
identifiers, and keywords.
 Verilog HDL is a case-sensitive language. All
keywords are in lowercase.
 Whitespace:
 White space is ignored by Verilog except when it
separates tokens.
 White space is not ignored in strings.

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 Comments
 One-line: //
 Multiple-line: /* …*/, can not be nested.

a = b && c; // This is a one-line comment

/* This is a multiple line
comment */
/* This is /* an illegal */ comment */
/* This is //a legal comment */

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 Operators
 Three types: unary, binary, and ternary.

a = ~ b; // ~ is a unary operator. b is the operand

a = b && c; // && is a binary operator. b and c are operands

a = b ? c : d; // ?: is a ternary operator. b, c and d are operands

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 Number Specification (1)
 Size numbers: <size> ‘ <base format> <number>
 <size>: only decimal number, specifies the number of
bits in the number.
 <base format>: decimal (‘d or ‘D), hexadecimal (‘h or ‘H),
binary (‘b or ‘B) and octal (‘o or ‘O).
 <number>: 0,…9,a, …, f.

4'b1111 // This is a 4-bit binary number

12'habc // This is a 12-bit hexadecimal number
16'd255 // This is a 16-bit decimal number

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 Number Specification (2)
 Unsized numbers:
 <number>: specifies decimal numbers by default.
 ‘ <base format> <number>: specifies default number
of bits that is simulator- and machine-specific (at least
32).

23456 // This is a 32-bit decimal number by default

'hc3 // This is a 32-bit hexadecimal number
'o21 // This is a 32-bit octal number

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 Number Specification (3)
 x or z vaules:
 x: unknown
 z: high impedance

12‘h13x /*This is a 12-bit hex number; 4 least significant

bits unknown*/
6'hx // This is a 6-bit hex number
32'bz // This is a 32-bit high impedance number

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 Number Specification (4)
 Underscore characters and question marks:
 _ : is allowed anywhere in a number except the first
character. _ is only to improve readability.
 ? : alternative for z in the context of numbers.

12'b1111_0000_1010 /* Use of underline characters for

readability*/
4'b10?? // Equivalent of a 4'b10zz

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 Strings
 The restriction on a string is that it must be
contained on a single line, that is, without a
carriage return.

"Hello Verilog World" // is a string

"a / b" // is a string

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 Identifiers and Keywords
 Keywords are special identifies reserved to
define the language constructs. Keywords are in
lowercase.
 Identifiers start with an alphabetic character or
an underscore. They cannot start with a digit or
a $ sign.
reg value; // reg is a keyword; value is an identifier
input clk; // input is a keyword, clk is an identifier

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 Escaped Identifiers
 Escaped identifiers begin with the backslash(\)
character and end with whitespace (space, tab,
or newline).
\a+b-c
\**my_name**

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 Data Types
 Value level:

Value Level Condition in Hardware Circuits

0 Logic zero, false condition

1 Logic one, true condition
x Unknown logic value
z High impedance, floating state

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 Strength Levels (1)
 Strength levels:
 If two signals of unequal strengths are driven
on a wire, the stronger signal prevails. (ex:
strong1, weak0  strong1)
 If two signals of equal strengths are driven on
a wire, the result is unknown. (ex: strong1,
strong0  x)

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 Strength Levels (1)

Strength Level Type Degree

supply Driving strongest

strong Driving
pull Driving
large Storage
weak Driving
medium Storage
small Storage
highz High Impedance weakest

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 Nets
 Nets represent connections between hardware
elements.
 Net are declared primarily with the keyword wire.
(wire is net)
 The default value of a net is z.

wire a; // Declare net a for the above circuit

wire b,c; /* Declare two wires b, c for the
above circuit*/
wire d = 1'b0; /* Net d is fixed to logic value 0
at declaration*/

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 Registers
 Registers represent data storage elements.
 Registers retain value until another value is
placed onto them.
 In Verilog, register merely means a variable that
can hold a value. Unlike a net, a register does
not need a driver.
 Verilog registers do not need a clock as
hardware registers do.
 Value of registers can be changed anytime in a
simulation by assigning a new value to the
register. (reg: default value is x)

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 Example of Register
reg reset; // declare a variable reset that can hold its value
initial // this construct will be discussed later
begin
reset = 1'b1; //initialize reset to 1 to reset the digital circuit
#100 reset = 1'b0; // after 100 time units reset is deasserted
end

 Registers can also be declared as signed

variables.
reg signed [63:0] m; // 64 bit signed value
integer i; // 32 bit signed value

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 Vectors
 Vectors: Multiple bit widths of nets or reg.
 [high#, low#], or [low#, high#]: the left number is the
most significant bit (MSB).

wire a; // scalar net variable, default: 1-bit, z

wire [7:0] bus; // 8-bit bus
wire [31:0] busA,busB,busC; // 3 buses of 32-bit width
reg clock; // scalar register, default:1-bit, x
reg [0:40] virtual_addr; /* Vector register, virtual address 41
bits wide*/

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 Vector Part Select

busA[7] // bit # 7 of vector busA

bus[2:0]
/*Three least significant bits of vector bus,
using bus[0:2] is illegal because the significant bit should
always be on the left of a range specification*/

virtual_addr[0:1] // Two most significant bits of vector

virtual_addr //All 41 bits virtual address

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 Variable Vector Part Select (1)
 [<staring-bit>+: width]: part-select increments
from starting bit.
 [<staring-bit>-: width]: part-select decrements
from starting bit.

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 Variable Vector Part Select (2)
reg [255:0] data1; //Little endian notation
reg [0:255] data2; //Big endian notation
reg [7:0] byte;
//Using a variable part select, one can choose parts
byte = data1[31-:8]; //starting bit = 31, width =8 => data[31:24]
byte = data1[24+:8]; //starting bit = 24, width =8 => data[31:24]
byte = data2[31-:8]; //starting bit = 31, width =8 => data[24:31]
byte = data2[24+:8]; //starting bit = 24, width =8 => data[24:31]
/*The starting bit can also be a variable. The width has to be constant.
Therefore, one can use the variable part select in a loop to select all bytes of
the vector.*/
for (j=0; j<=31; j=j+1)
byte = data1[(j*8)+:8]; /*Sequence is [7:0], [15:8]... [255:248]. It can
initialize a part of the vector*/
data1[(byteNum*8)+:8] = 8'b0; //If byteNum = 1, clear 8 bits [15:8]
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 Interger, Real, and Time register Data
Types
 Registers: stores values as unsigned quantities.
 Integer: The default width is the host-machine
word size. (at least 32-bit)
 Integers: stores values as signed quantities.

integer counter; // general purpose variable used as a counter

initial
counter = -1; // A negative one is stored in the counter

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 Real
 Real number: decimal notation (e.g.: 3.14) or
scientific notation (e.g.: 3e6, which is 3x106)
 Default value is 0.

real delta; // Define a real variable called delta

initial
begin
delta = 4e10; // delta is assigned in scientific notation
delta = 2.13; // delta is assigned a value 2.13
end
integer i; // Define an integer i
initial
i = delta; // i gets the value 2 (rounded value of 2.13)
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 Time
 time: stores simulation time. (at least 64 bits)

time save_sim_time; // Define a time variable save_sim_time

initial
save_sim_time = $time; // Save the current simulation time

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 Array (1)
 Array are allowed in Verilog for reg., integer,
time, real, realtime.
 Arrays of nets can also be used to connect ports
of generated instances.

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 Array (2)
integer count[0:7]; // An array of 8 count variables
reg bool[31:0]; // Array of 32 one-bit boolean register variables
time chk_point[1:100]; // Array of 100 time checkpoint variables
reg [4:0] port_id[0:7]; // Array of 8 port_ids; each port_id is 5 bits wide
integer matrix[4:0][0:255]; // Two dimensional array of integers
reg [63:0] array_4d [15:0][7:0][7:0][255:0]; //Four dimensional array
wire [7:0] w_array2 [5:0]; // Declare an array of 8 bit vector wire
wire w_array1[7:0][5:0]; // Declare an array of single bit wires

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 Array vs. Vector (1)
 Vector: is a single element that is n-bits wide.
 Array: are multiple elements that are 1-bit or n-
bits wide.
count[5] = 0; // Reset 5th element of array of count variables
chk_point[100] = 0; // Reset 100th time check point value
port_id[3] = 0; // Reset 3rd element (a 5-bit value) of port_id array
matrix[1][0] = 33559; // Set value of element indexed by [1][0] to 33559
array_4d[0][0][0][0][15:0] = 0; /* Clear bits 15:0 of the register accessed
by indices [0][0][0][0] */

port_id = 0; // Illegal syntax - Attempt to write the entire array

matrix [1] = 0; // Illegal syntax - Attempt to write [1][0]..[1][255]

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 Array vs. Vector (2)
 Array: wire A[7:0]; /*eight A elements, 1 bit
per element.*/
 Vector: wire [3:0] A; /*one element, 4 bits
per element.*/
 Array: wire [3:0] A[7:0]; /*eight A elements,
4 bits per element.*/ Element
number
Bit
number

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 Memories
 A one-dimensional array of registers: model as
register files, RAMs, and ROMs.
 A single array index: an element or word.
 An element: one bit or more bits.

reg mem1bit[0:1023]; // Memory mem1bit with 1K 1-bit words

reg [7:0] membyte[0:1023]; /* Memory membyte with 1K 8-bit
words(bytes)*/
membyte[511] // Fetches 1 byte word whose address is 511

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 Parameters (1)
 Parameters cannot be used as variables.
 Parameters values for each module instance
can be overridden individually at compile time.
 Parameters can be changed at module
instantiation or by using the defparam statement.

parameter port_id = 5; // Defines a constant port_id

parameter cache_line_width = 256;
/* Constant defines width of cache line */

parameter signed [15:0] WIDTH;

/* Fixed sign and range for parameter WIDTH */
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 Parameters (2)
module or8(a, b, c);
parameter width=8;

input [1:width] a, b;
output [1:width] c;
`include “or8.v”
assign c = a | b; module or4(a, b, c);
parameter size = 4;
endmodule input [1:size] a, b;
output [1:size] c;

or8 o4(a, b, c);

Override width from 8 to 4 defparam o4.width=4;

endmodule

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 Parameters (3)
 localparam: is identical to parameter except it
cannot be directly modified with the defparam
statement or by the ordered or named parameter
value assignment.
 The localparam is used to define parameters when
their values should not be changed.
localparam state1 = 4'b0001,
state2 = 4'b0010,
state3 = 4'b0100,
state4 = 4'b1000;

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 String
 String can be stored in reg.
 Each character in the string takes up 8 bits.
 If the width of the reg > the size of the string,
Verilog fills bits to the left of the string with zeros,
else Verilog truncates the leftmost bits of the
string.
reg [8*18:1] string_value; // Declare a variable that is 18 bytes wide
initial
string_value = "Hello Verilog World";
// String cannot be all stored in variable

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 Special Characters
Escaped Characters Character Displayed
\n newline
\t tab
%% %
\\ \
\" "
\ooo Character written in 1–3 octal digits

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System Tasks and Compiler Directives

 All system tasks appear in the form $<keyword>.

 Display information:
 $display(p1, p2, p3, …, pn);
 pn: can be quoted strings or variables or expressions.

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 String Format Specifications
Format Display

%d or %D Display variable in decimal

%b or %B Display variable in binary
%s or %S Display string
%h or %H Display variable in hex
%c or %C Display ASCII character
%m or %M Display hierarchical name (no argument required)
%v or %V Display strength
%o or %O Display variable in octal
%t or %T Display in current time format

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 $display Task (1)
//Display the string in quotes
$display("Hello Verilog World");
-- Hello Verilog World
//Display value of current simulation time 230
$display($time);
-- 230
//Display value of 41-bit virtual address 1fe0000001c at time 200
reg [0:40] virtual_addr;
$display("At time %d virtual address is %h", $time, virtual_addr);
-- At time 200 virtual address is 1fe0000001c
//Display value of port_id 5 in binary
reg [4:0] port_id;
$display("ID of the port is %b", port_id);
-- ID of the port is 00101
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 $display Task (2)

//Display x characters
//Display value of 4-bit bus 10xx (signal contention) in binary
reg [3:0] bus;
$display("Bus value is %b", bus);
-- Bus value is 10xx

/*Display the hierarchical name of instance p1 instantiated under the

highest-level module called top. No argument is required. This
is a useful feature*/
$display("This string is displayed from %m level of hierarchy");
-- This string is displayed from top.p1 level of hierarchy

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 Special Characters
//Display special characters, newline and %
$display("This is a \n multiline string with a %% sign");
-- This is a
multiline string with a % sign

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 Monitoring information (1)
 $monitor(p1, p2, p3, …, pn):
 monitor a signal when its value changes.
 pn: can be variables, signal names, or quoted strings.
 continuously monitors the value of the variables or
signals specified in the parameter list and displays all
parameters in the list whenever the value of any one
variable or signal changes.
 Unlike $display, $monitor needs to be invoked only
once.
 If more than one $monitor appears in the code, the
last $monitor will be the active one. The earlier
$monitor will be overridden.

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 Monitoring information (2)
 $monitoron: enables monitoring
 $monitoroff: disables monitoring during a simulation.

Usage:
$monitoron;
…………..
$monitoroff;

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 Monitoring information (3)
/*Monitor time and value of the signals clock and reset clock
toggles every 5 time units and reset goes down at 10 time
units*/
initial
begin
$monitor($time, " Value of signals clock = %b reset = %b",
clock, reset);
end
//Partial output of the monitor statement:
-- 0 Value of signals clock = 0 reset = 1
-- 5 Value of signals clock = 1 reset = 1
-- 10 Value of signals clock = 0 reset = 0

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 Stopping and Finishing in a Simulation
 $stop:
 puts the simulation in an interactive mode.
 Wants to suspend the simulation and examine the
values of signals in the design.
 $finish: terminates a simulation.
/* Stop at time 100 in the simulation and examine the results.
Finish the simulation at time 1000. */
initial // to be explained later time = 0
begin
clock = 0;
reset = 1;
#100 $stop; // This will suspend the simulation at time = 100
#900 $finish; // This will terminate the simulation at time = 1000
end
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 Compiler Directive
 ‘define: is similar to #define in C.
//define a text macro that defines default word size
//Used as 'WORD_SIZE in the code
'define WORD_SIZE 32

//define an alias. A $stop will be substituted wherever 'S appears

'define S $stop;
//define a frequently used text string

'define WORD_REG reg [31:0]

// you can then define a 32-bit register as 'WORD_REG;

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 ‘include
 ‘include: include entire contents of a Verilog
source file in another Verilog file during
compilation. (#include in C)
// Include the file header.v, which contains declarations in the
// main verilog file design.v.
`include “header.v”
...
...
<Verilog code in file design.v>
...
...
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 Summary
 Verilog is similar in syntax to the C programming
language.
 Lexical conventions were discussed.
 Various data types are available in Verilog.
 Verilog provides useful system tasks to do
functions.
 Compiler directive ‘define is used to define text
macros, and ‘include is used to include other
Verilog files.

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