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Chapter 2

Uploaded by

Chang Max
Copyright
© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
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Chapter 2

Hierarchical Modeling Concepts

教師: 陳銘志

Electronic Engineering, NKFUST 1


Learning Objectives
 Understand top-down and bottom-up design
methodologies for digital design.
 Explain differences between modules and
module instances in Verilog.
 Describe four levels of abstraction – behavioral,
data flow, gate level, and switch level – to
represent the same module.
 Describe components required for the simulation
of a digital design. Define a stimulus block and a
design block. Explain two methods of applying
stimulus.

Electronic Engineering, NKFUST 2


Design Methodologies
 Three types: top-down, bottom-up, and
combination.
 Top-down: we define the top-level block and identify
the sub-blocks necessary to build the top-level block.
 Botton-up: we build bigger cells, using these building
blocks.
 Combination: Design architects define the
specifications of the top-level block. Logic designers
decide how the design should be structured by
breaking up the functionality into blocks and sub-
blocks. At the same time, circuit designers are
designing optimized circuits for leaf-level cells.

Electronic Engineering, NKFUST 3


Top-down Design Methodology

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Bottom-up Design Methodology

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4-bit Ripple Carry Counter
 Made up of negative edge-triggered toggle
flipflops. (T_FF)

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T_FF
 Made up from negative edge-triggered D-FF and
inverters.

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Hierarchical Fashion

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Modules
 A module is the basic building block in Verilog.
 A module can be an element or a collection of
lower-level design blocks.

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Four Level of Abstraction
 Behavioral or algorithmic level
 The highest level abstraction of Verilog, very similar to
C programming.
 Dataflow level
 The designer is aware of how data flows between
hardware registers and how the data is processed in
the design.
 Gate level
 The module is implemented in terms of logic gates and
interconnections between these gates.
 Switch level
 A module can be implemented in terms of switches,
storage nodes, and interconnections between them.
Electronic Engineering, NKFUST 10
Register Transfer Level
 Verilog allow the designer to mix and match all
four levels of abstractions in a design.
 RTL (Register Transfer Level) is used for a
Verilog description that uses a combination of
behavioral and dataflow constructs and is
acceptable to logic synthesis tools.
 The higher the level of abstraction, the more
flexible and technology-independent the design.

Electronic Engineering, NKFUST 11


Instances
 A module provides a template from which you
can creates a unique object from the template.
 Each object has its own name, variables,
parameters, and I/O interface.
 The process of creating objects from a module
template is called instantiation, and the objects
are called instances.

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Module
Instantiation

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Illegal Module Nesting
 In Verilog, it is illegal to nest modules.

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Components of a Simulation
 Stimulus block (test bench): the functionality of
the design block can be tested by applying
stimulus and checking results.
 It is a good practice to keep the stimulus and
design blocks separate.

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Stimulus Block Instantiates Design
Block
 The stimulus block instantiates the design block
and directly drives the signals in the design
block.

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Stimulus and Design Blocks
Instantiates in a Dummy Top-Level
Module
 The stimulus block interacts with the design
block only through the interface.

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Design Block (1)
 Ripple Carry Counter Top Block

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Design Block (2)
 Flip-flop T_FF:

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Design Block (3)
 Flip-flop D_F:

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Stimulus Block (1)
 Example:
 The cycle time fo clk : 10 units
 The reset signal stays up from time 0 to 15 and then
goes up again from time 195 to 205.
 Output q counts from 0 to 15.

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Stimulus Block (2)
 Output Waveforms

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reg clk;

Stimulus
Block (3)

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Output of the Simulation

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Summary
 A combination of top-down and bottom-up
design methodologies is used in today’s digital
design.
 Modules are basic building blocks in Verilog.
 Two distinct components in a simulation: a
design block and a stimulus block.
 A stimulus block is used to test the design block.
 There are two different styles of applying stimulus to a
design block.

Electronic Engineering, NKFUST 25

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