DNx-AI-256

Synchro/Resolver/LVDT/RVDT
Interface
—
User Manual

2-Channel Synchro/Resolver I/O Interface

and LVDT/RVDT I/O Interface Board
for the PowerDNA Cube and RACK Series Chassis

USPTO Patent: 7,957,942

May 2022
PN Man-DNx-AI-256

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 DNx-AI-256 Synchro/Resolver/LVDT/RVDT Interface i
Table of Contents

Table of Contents
Chapter 1 Introduction .................................................... 1
1.1 Organization of this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 AI-256 Board Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2.1 Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2.2 Environmental Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2.3 Software Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.5 Device Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Chapter 2 AI-256 Synchro / Resolver Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Synchro & Resolver Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1.1 Description of Synchros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1.2 Example Synchro Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.3 Description of Resolvers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1.4 Example Resolver Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2 AI-256 Synchro / Resolver Specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3 AI-256 Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.1 Synchro Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.2 Resolver Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.4 AI-256 Synchro / Resolver Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.5 Connecting Synchro / Resolver Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.5.1 Synchro Wiring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.5.2 Resolver Wiring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.5.3 Synchro Line-to-Line Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.5.4 Z-grounded Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.5.5 Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Chapter 3 AI-256 LVDT / RVDT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.1 LVDT / RVDT Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2 AI-256 LVDT / RVDT Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.3 AI-256 LVDT / RVDT Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.4 AI-256 LVDT / RVDT Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.4.1 LVDT / RVDT Analog Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.4.2 Simulator Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.4.3 Simulator Output to LVDT/RVDT Input Mode . . . . . . . . . . . . . . . . . . . . . . . . 37
3.5 Setting Operating Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Chapter 4 Programming with the High-level API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.1 About the High-level Framework. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.2 Creating a Session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.3 Configuring the Resource String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.4 Configuring for Synchro / Resolver Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

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 DNx-AI-256 Synchro/Resolver/LVDT/RVDT Interface ii
Table of Contents

4.5 Configuring for Simulated Synchro/Resolver Output . . . . . . . . . . . . . . . . . . . . . . . . 40

4.6 Configuring for LVDT /RVDT Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.7 Configuring for Simulated LVDT / RVDT Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.8 Configuring the Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.9 Reading Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.10 Writing Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.11 Cleaning-up the Session. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Chapter 5 Programming with the Low-level API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.1 About the Low-level API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.2 Low-level Programming Techniques. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.2.1 Data Collection Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.3 DNx-AI-256 Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.4 Programming AI-256 for Synchro/Resolver Devices . . . . . . . . . . . . . . . . . . . . . . . . 46
5.4.1 Synchro / Resolver Low-level Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.4.2 Configuring Synchro/Resolver Excitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.4.3 Configuring Synchro/Resolver Operational Modes . . . . . . . . . . . . . . . . . . . . 49
5.4.4 Enabling Synchro/Resolver Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.4.5 Reading Synchro or Resolver Inputs (Immediate Mode) . . . . . . . . . . . . . . . . 50
5.4.6 Writing Synchro or Resolver Simulated Outputs . . . . . . . . . . . . . . . . . . . . . . 51
5.5 Programming AI-256 for LVDT / RVDT Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.5.1 LVDT/RVDT Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.5.2 Configuring LVDT/RVDT Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . 53
5.6 Programming Power Monitor on AI‒256. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
A.1 Accessories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Appendix B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
A.1 Synchro Input Mode with Internal Excitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
A.2 Synchro Input Mode with External Excitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
A.3 Synchro Simulator Output Mode with Internal Excitation. . . . . . . . . . . . . . . . . . . . . 61
A.4 Synchro Simulator Output Mode with External Excitation . . . . . . . . . . . . . . . . . . . . 63
A.5 Synchro Simulator Output Mode with External Excitation & Z-grounding . . . . . . . . 65
A.6 Resolver Input Mode with Internal Excitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
A.7 Resolver Input Mode with External Excitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
A.8 Resolver Simulator Output Mode with Internal Excitation . . . . . . . . . . . . . . . . . . . . 68
A.9 Resolver Simulator Output Mode with External Excitation. . . . . . . . . . . . . . . . . . . . 69

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 DNx-AI-256 Synchro/Resolver/LVDT/RVDT Interface iii
List of Figures

List of Figures
Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1-1 Photo of DNR-AI-256 Board ..........................................................................................4
1-2 Block Diagram of DNx-AI-256 I/O Board .......................................................................5
Chapter 2 AI-256 Synchro / Resolver Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2-1 Internal Structure of Star Synchro (left) vs. Delta Synchro (right)..................................6
2-2 Synchro Transmitter and Receiver System ...................................................................8
2-3 Synchro Transmitter and Control Transformer System .................................................9
2-4 Synchro Waveforms at -30° Rotor Angle.....................................................................10
2-5 Brushless Resolver Control Transformer.....................................................................11
2-6 Magnitudes of SIN and COS Output RMS Voltages vs. Rotor Angle θ .......................12
2-7 SIN and COS Output Voltages vs. Rotor Angle ..........................................................13
2-8 AI-256 Resolver Waveforms at 30° Rotor Angle .........................................................14
2-9 AI-256 Resolver Waveforms at 45° Rotor Angle .........................................................14
2-10 AI-256 Resolver Waveforms at 135° Rotor Angle .......................................................15
2-11 Pinout Diagram for DNx-AI-256 ...................................................................................20
2-12 Peak-to-peak Voltage Measurement of Synchro .........................................................23
2-13 Connecting Star Synchro in Z-grounded Mode ...........................................................25
Chapter 3 AI-256 LVDT / RVDT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3-1 DNx-AI-256 LVDT/RVDT Pinout..................................................................................28
3-2 6-wire LVDT Device with AI-256 in Analog Input Mode, Internal Excitation ................31
3-3 6-wire LVDT Device with AI-256 in Analog Input Mode, External Excitation ...............32
3-4 6-wire LVDT Device with AI-256 in Simulator Output Mode, External Excitation ........33
3-5 4-wire LVDT Device with AI-256 in Simulator Mode, External Excitation ....................34
3-6 6-wire LVDT Device with AI-256 in Simulator Output Mode, External Excitation ........35
3-7 4-wire LVDT Device with AI-256 in Simulator Mode....................................................36
3-8 Ch1 Simulated Output Connected to Ch0 Analog Input (6-wire).................................37
Chapter 4 Programming with the High-level API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Chapter 5 Programming with the Low-level API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
A-1 Pinout and photo of DNA-STP-62 screw terminal panel..............................................55
Appendix B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
B-1 Star Synchro: Input Mode, Internal Excitation .............................................................57
B-2 Delta Synchro: Input Mode, Internal Excitation ...........................................................58
B-3 Star Synchro: Input Mode, External Excitation ............................................................59
B-4 Delta Synchro: Input Mode, External Excitation ..........................................................60
B-5 Star Synchro: Simulator Mode, Internal Excitation ......................................................61
B-6 Delta Synchro: Simulator Mode, Internal Excitation ....................................................62
B-7 Star Synchro: Simulator Mode, External Excitation.....................................................63
B-8 Delta Synchro: Simulator Mode, External Excitation ...................................................64
B-9 Star Synchro: Simulator Mode, External Excitation, Z-grounding................................65
B-10 Resolver: Input Mode, Internal Excitation ....................................................................66
B-11 Resolver: Input Mode, External Excitation...................................................................67
B-12 Resolver: Simulator Mode, Internal Excitation.............................................................68
B-13 Resolver: Simulator Mode, External Excitation............................................................69

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 DNx-AI-256 Synchro/Resolver/LVDT/RVDT Interface iv
List of Tables

List of Tables
Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1-1 AI-256 Indicators.........................................................................................................................4
Chapter 2 AI-256 Synchro / Resolver Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2-1 DNx-AI-256 Technical Specifications (Synchro/Resolver Mode)...............................................16
2-2 AI-256 Synchro Operational Modes...........................................................................................18
2-3 AI-256 Resolver Operational Modes.......................................................................................... 19
2-4 Synchro Connections for Operational Modes ............................................................................ 21
2-5 Resolver Connections for Operational Modes ........................................................................... 22
2-6 Z-grounded modes of operation from powerdna.h .................................................................... 25
Chapter 3 AI-256 LVDT / RVDT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3-1 DNx-AI-256 (LVDT/RVDT Mode) Specifications........................................................................27
3-2 AI-256 Modes of Operation.......................................................................................................30
Chapter 4 Programming with the High-level API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Chapter 5 Programming with the Low-level API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5-1 Summary of Low-level Synchro / Resolver API Functions for DNx-AI-256...............................46
5-2 AI-256 Modes of Operation.......................................................................................................49
5-3 AI-256 LVDT/RVDT Modes of Operation..................................................................................53
5-4 Return Values for Power Monitor............................................................................................... 54
Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Appendix B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

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508.921.4600
 DNx-AI-256 Synchro/Resolver/LVDT/RVDT Interface
Chapter 1 1
Introduction

Chapter 1 Introduction

This document outlines the feature set and use of the DNx-AI-256 synchro/
resolver/LVDT/RVDT interface board.
The following sections are provided in this chapter:
• Organization of this Manual (Section 1.1)
• AI-256 Board Overview (Section 1.2)
• Features (Section 1.3)
• Indicators (Section 1.4)
• Device Architecture (Section 1.5)

NOTE: UEI provides a fan unit (DNR-FAN-925) with each

DNR-AI-256 RACK-version board. Due to the high power output of the
AI-256, the fan unit should be placed in the slot adjacent to the
DNR-AI-256 board in the RACKtangle chassis.

1.1 Organization The DNx-AI-256 User Manual is organized as follows:

of this Manual • Introduction
Chapter 1 provides an overview of DNx-AI-256 features, device
architecture, connectivity, and logic.
• AI-256 Synchro / Resolver Functional Description
Chapter 2 provides an overview of the how synchros and resolvers
work, example waveforms, synchro/resolver modes of operations, and
the AI-256 synchro/resolver pinouts.
• AI-256 LVDT / RVDT Functional Description
Chapter 3 provides an descriptions of the AI-256 LVDT/RVDT modes of
operations and the AI-256 LVDT/RVDT pinout, along with pinouts for
connecting to LVDT/RVDT devices.
• Programming with the High-Level API
Chapter 4 provides an overview of the how to create a session,
configure the session, and interpret results with the Framework API.
• Programming with the Low-Level API
Chapter 5 is an overview of low-level API commands for configuring and
using the AI-256 series board.
• Appendix A - Accessories
This appendix provides a list of accessories available for use with the
DNx-AI-256 interface board.
• Appendix B - Connection Diagrams
This appendix contains connection diagrams for various operating and
synchro/resolver excitation modes of the DNx-AI-256 interface board.
• Index
This is an alphabetical listing of the topics covered in this manual.

NOTE: A glossary of terms used with the PowerDNA Cube/RACK and I/O
boards can be viewed or downloaded from www.ueidaq.com.

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 DNx-AI-256 Synchro/Resolver/LVDT/RVDT Interface
Chapter 1 2
Introduction

Manual Conventions
To help you get the most out of this manual and our products, please note that
we use the following conventions:

Tips are designed to highlight quick ways to get the job done or to reveal
good ideas you might not discover on your own.

NOTE: Notes alert you to important information.

CAUTION! Caution advises you of precautions to take to avoid injury, data loss,
and damage to your boards or a system crash.

Text formatted in bold typeface generally represents text that should be entered
verbatim. For instance, it can represent a command, as in the following
example: “You can instruct users how to run setup using a command such as
setup.exe.”
Bold typeface will also represent field or button names, as in “Click Scan
Network.”
Text formatted in fixed typeface generally represents source code or other text
that should be entered verbatim into the source code, initialization, or other file.

Examples of Manual Conventions

Before plugging any I/O connector into the Cube or RACKtangle, be

sure to remove power from all field wiring. Failure to do so may
cause severe damage to the equipment.

Usage of Terms
Throughout this manual, the term “Cube” refers to either a PowerDNA Cube
product or to a PowerDNR RACKtanglerack mounted system, whichever is
applicable. The term DNR is a specific reference to the RACKtangle, DNA to the
PowerDNA I/O Cube, and DNx to all chassis types.

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 DNx-AI-256 Synchro/Resolver/LVDT/RVDT Interface
Chapter 1 3
Introduction

1.2 AI-256 Board The DNx-AI-256 is a high performance, 2-channel synchro, resolver, or linear/
Overview rotational variable differential transformer (LVDT/RVDT) input or simulator
output interface. The DNx-AI-256 is physically a two board module with a base
board plus an AI-256-specific daughter board. It is suited for a wide variety of
industrial, military, and simulator applications.
The DNA-AI-256, DNR-AI-256, and DNF-AI-256 boards are compatible with the
UEI Cube, RACKtangle, and FLATRACK chassis respectively. These board
versions are electronically identical and differ only in mounting hardware. The
DNA version is designed to stack in a Cube chassis. The DNR/F versions are
designed to plug into the backplane of a RACK chassis.

1.2.1 Compatibility Functionally, the AI-256 is an extension of the AI-255 with higher current output
and lower voltage, and also provides LVDT/RVDT functions of the AI-254 with
much higher voltage and current capabilities.

1.2.2 Environmental As with all UEI PowerDNA boards, the DNx-AI-256 can be operated in harsh
Conditions environments and has been tested at 5g vibration, 50g shock, -40 to +85°C
temperature, and altitudes up to 70,000 feet. Each board provides 350 Vrms
isolation between channels and also between the board and its enclosure or any
other installed boards as well as electro-shock-discharge (ESD) isolation.

1.2.3 Software Software included with the DNx-AI-256 provides a comprehensive yet easy to
Support use API that supports all popular operating systems including Windows, Linux,
real-time operating systems such as QNX, RTX, VxWorks and more. The
UEIDAQ framework comes with bindings for various programming languages
such as C, C++, C#, VB.NET and scientific software packages such as
LabVIEW and Matlab, as well as supporting OPC servers.

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 DNx-AI-256 Synchro/Resolver/LVDT/RVDT Interface
Chapter 1 4
Introduction

1.3 Features The features of the DNx-AI-256 include:

• Two Synchro, Resolver, LVDT, or RVDT input or output channels in any
combination
• 16-bit resolution
• 3- / 4-wire (plus excitation) Synchro and 4-wire (plus excitation)
Resolver inputs
• Signal input voltage up to 28 Vrms
• Signal output voltage up to 19.8Vrms
• Reference (excitation) voltage up to 19.8Vrms at 3.0VA in 0.6mVrms
increments (16-bit output resolution)
• User-programmable excitation frequency (50Hz-10kHz)
• Automatic shutdown on overload in Synchro/Resolver mode
• Isolation up to 350 Vrms between channel and between I/Os and GND
• Tested to withstand 5g Vibration, 50g Shock, -40 to +85°C Temperature,
and Altitude up to 70,000 ft or 21,000 meters.
• Weight of 136 g or 4.79 oz for DNA-AI-256; 817 g or 28.8 oz with PPC5.

1.4 Indicators The AI-256 indicators are described in Table 1-1 and illustrated in Figure 1-1.

LED Name Description

RDY Indicates board is powered up and operational

STS Indicates which mode the board is running in:

• OFF: Configuration mode, (e.g., configuring channels,

running in point-by-point mode)
• ON: Operation mode

Table 1-1. AI-256 Indicators

DNR bus
connector

RDY LED
STS LED

DB-62 (female)
62-pin I/O connector

Figure 1-1 Photo of DNR-AI-256 Board

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Introduction

1.5 Device A block diagram of a DNx-AI-256 board is shown in Figure 1-2.

Architecture

Isolation
Out A±

DB-62 Analog I/O Connector

Out B±
D/A

Overvoltage Protection
or Avionics Equipment

Out C± Converters
Synchro / Resolver

32-bit 66-MHz bus

Out D±
Control
Logic
In A±
In B± A/D
In C± PGA Converters
In D±

Channel 0
Channel 1

Input and Output connections and I/O circuitry

are repeated for Channel 1.

Each channel is an independent system that is physically

isolated from the other.

Figure 1-2 Block Diagram of DNx-AI-256 I/O Board

Board logic is divided into isolated and non-isolated sections. The isolated side
handles all functions associated with the sensor input and output circuits, and
the non-isolated side handles all Cube or chassis-related operations.
Each AI-256 channel is designed with differential inputs and single-ended
outputs. The + side of the outputs (OutA+ through OutD+) are each driven by a
high-voltage, high-current operational amplifier.The - side of the outputs (OutA-
through OutD-) are connected to channel ground.

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Chapter 2 6
AI-256 Synchro / Resolver Mode

Chapter 2 AI-256 Synchro / Resolver Mode

The DNx-AI-256 can act as a 2-channel Synchro or Resolver input interface or

simulated output interface for UEI data acquisition systems.
This chapter provides the following information:
• Synchro & Resolver Overview (Section 2.1)
• AI-256 Synchro / Resolver Specification (Section 2.2)
• AI-256 Operational Modes (Section 2.3)
• AI-256 Synchro / Resolver Pinout (Section 2.4)
• Connecting Synchro / Resolver Hardware
(Section 2.5)

2.1 Synchro & Synchros and resolvers are electromechanical transducers that are used either
Resolver to detect and measure a rotary shaft position or to position a shaft at a desired
Overview angle. The devices can be further classified as transmitters, receivers,
differentials, or control transformers.

2.1.1 Description of A synchro consists of a single-phase rotor surrounded by a 3-phase stator. The
Synchros three stator coils are spatially arranged 120° apart but may be wired in either a
star or delta configuration, as illustrated in Figure 2-1.

Figure 2-1 Internal Structure of Star Synchro (left) vs. Delta

Synchro (right)

NOTE: Synchro stator terminals are commonly labeled X, Y, Z in practice, but

this manual will use the standard S1, S2, S3 notation moving forward.

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AI-256 Synchro / Resolver Mode

Although synchros may appear similar in construction to synchronous motors/

generators, the main difference between them is that the rotor of a synchro is
excited with an AC voltage rather than a DC voltage. Since the magnetic field
created by the synchro’s rotor changes with time, voltage is induced in the stator
even when the rotor is stationary. This allows a synchro transmitter to monitor
the rotor’s angular position, unlike a generator where rotor motion is required to
produce an output.
Transmitter
A synchro transmitter applies AC voltage to the rotor winding and induces AC
voltages in the three stator windings. The induced voltage is maximized when
the rotor and stator coil share an axis and minimized when the axes are
perpendicular. In general, the amplitudes are given by:
V  = kV R sin   + 30 
V  = kV R sin   + 150 
V  = kV R sin   + 270 
where
•  is the rotor angle measured clockwise from the reference position
shown in Figure 2-1.
• V  is the (time-varying) voltage across stator coil  .
• Star Synchro: V  = V S1 – V C
• Delta Synchro: V  = V S2 – V S1
• V R is the (time-varying) excitation voltage across the rotor.
V R = V R1 – V R2
• k is a constant which represents the maximum coupling transformation
ratio Vout/Vin.
Thus, the transmitter outputs a unique set of three voltages for each position of
the rotor throughout a 360° rotation. If the sine evaluates to a positive number,
the induced voltage is in time-phase with the excitation voltage. If the sine is
negative, the induced voltage is inverted (180° out of time-phase). Example
waveforms are shown in Figure 2-4.

NOTE: If the device uses a different reference shaft position from what’s shown
in Figure 2-1, θ will be offset by a constant.

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AI-256 Synchro / Resolver Mode

Receiver
A synchro receiver has the same physical construction as a synchro transmitter.
However, instead of functioning as an output device, the receiver moves its rotor
in response to input signals present on its stator windings.
In a typical application, a synchro transmitter and receiver are wired together so
that the angular position of the transmitter’s rotor is automatically reproduced in
the receiver’s rotor. As shown in Figure 2-2, the receiver’s rotor is excited in
parallel with the transmitter. When the transmitter and receiver rotors are in
alignment, stator voltages are equal and no current flows. If the transmitter rotor
is turned (relative to the receiver rotor), a force appears in the receiver, causing
the rotor to track the transmitter rotor. The torque produced is proportional to the
angle difference between the two rotors. Typical accuracy of such a system is 30
arc-minutes.
A single transmitter may be parallel-connected to multiple receivers, at the cost
of reducing accuracy and increasing power drain from the source.
C C
S2 S2
tor C C S
S3 S3
C C
Figure 2-2 Synchro Transmitter and Receiver System

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AI-256 Synchro / Resolver Mode

Control Transformer
A control transformer is another type of synchro that can be wired to a
transmitter. Unlike a receiver, the control transformer is not designed to directly
position a load. Instead, its rotor terminals are normally wired to a servo control
system that can drive higher torque loads.

Figure 2-3 Synchro Transmitter and Control Transformer System

When the transmitter rotor is turned, the transmitter outputs a new set of stator
voltages to the control transformer. This changes the magnetic field seen by the
control transformer rotor and induces a voltage if the two rotors are not aligned.
The voltage induced in the control transformer rotor is proportional to the sine of
the angle difference between the two rotors. (The control transformer rotor is
cylindrically shaped to keep the magnitude of its stator field constant, allowing
the induced voltage to depend only on the field direction.) Therefore, the control
transformer provides information about the transmitter rotor’s angular position.
In a typical application, the small but sensitive output signal from the control
transformer is amplified and sent to a motor. As the motor positions the load, it
mechanically turns the control transformer shaft in a negative feedback loop;
when the control transformer reaches the same angle as the transmitter, the
input to the motor decreases back to 0.

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AI-256 Synchro / Resolver Mode

2.1.2 Example When a synchro is used, the excitation and output voltages appear as shown in
Synchro Figure 2-4.
Waveforms

S1 (Cyan)

S2 (Blue)

S1 (Green)

Excitation

Figure 2-4 Synchro Waveforms at -30° Rotor Angle

The S1 coil output voltage (green line) is zero because the rotor is positioned
plus or minus 90° relative to the S1 stator winding and therefore produces
nothing. The S3 coil (blue line) shows a voltage in phase with excitation and with
the same polarity as the excitation voltage. The S2 coil (cyan line) shows a
voltage of polarity opposite to that of the excitation (or 180° out of phase).

NOTE: Coils on a synchro can be labeled in two different ways. Looking at the
synchro from the shaft side with S1 at the top, S2 and S3 may follow in
either a counterclockwise or clockwise direction depending on the
manufacturer.

NOTE: When using the AI-256 as a Synchro output for simulation, you can
attach a scope to the simulation outputs, ground the scope probes to
AGND and read voltages between S1 and AGND, S2 and AGND, and
S3 and AGND. Some synchros have the coil mid points between coils
brought out, but most do not.

Additional Information
Additional information and formulas for calculating the simulated positions are
provided in the PowerDNA API Reference Manual. Refer to the DqAdv255Write
and DqAdv255ConvertSim API.

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AI-256 Synchro / Resolver Mode

2.1.3 Description of A resolver is a rotary transformer in which the magnitude of the energy through
Resolvers the resolver varies sinusoidally with rotation of the shaft. A resolver control
transmitter has one primary winding (Excitation Winding) and two secondary
windings (the SIN and COS windings). The excitation winding is located on the
rotor and the SIN and COS windings are on the stator, displaced spatially by 90°.
If the resolver is a brushless type, current is applied through a rotary
transformer, which eliminates the problems of slip rings and brushes.
The connection arrangement of a brushless resolver control transformer is
illustrated below in Figure 2-5.

S4
COS
Winding kVr cos 

S2

R1
SIN
Vr Winding

R2
Rotary
S3
Transformer
 kVr sin 
0° S1

Figure 2-5 Brushless Resolver Control Transformer

The excitation winding on the rotor is typically excited by an AC voltage. The
induced voltages in the SIN and COS windings obey the following equations:
V SIN = kV R sin   
V COS = kV R cos   
where
•  is the rotor angle relative to the reference position shown in Figure 2-
5.
• V SIN is the (time-varying) voltage across the SIN winding.
V SIN = V S1 – V S3
• V COS is the (time-varying) voltage across the COS winding.
V COS = V S2 – V S4
• V R is the (time-varying) excitation voltage applied to the rotor.
V R = V R1 – V R2
• k is a constant which represents the maximum coupling transformation
ratio Vout/Vin.

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AI-256 Synchro / Resolver Mode

Figure 2-6 illustrates how the magnitudes of the output voltages vary with rotor
angle.
Resolver Output vs. Shaft Angle
SIN
1.5

1
COS

0.5
Output

CO
0
SI
0

0
30

60

90

12

15

18

21

24

27

30

33

36

39
-0.5

-1

-1.5
Shaft Angle

Figure 2-6 Magnitudes of SIN and COS Output RMS Voltages vs.
Rotor Angle θ
The induced voltage is maximized when the primary and secondary windings
share an axis and minimized when the axes are perpendicular. For example, at
θ=0° (first point on the graph), the rotor is in line with the COS winding. Since
cos(0°)=1, VCOS will have the maximum possible magnitude. Since sin(0°)=0,
there will be no output on VSIN. If the rotor is positioned at θ=45°, the SIN and
COS output waveforms will have equal magnitudes.
Note that the above graph in Figure 2-6 does not represent an oscilloscope
display. Refer to Figure 2-8, Figure 2-9 and Figure 2-10 for oscilloscope
displays of the SIN (S1), COS (S2), and excitation waveforms at rotor angles
30°, 45° and 135°.

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AI-256 Synchro / Resolver Mode

2.1.4 Example This section contains example waveforms of amplitudes, polarity, and phase vs
Resolver rotor angles for Resolver circuits.
Waveforms A sine wave AC Excitation voltage Vexc is applied between R1 and R2. The
voltage observed between S1 and S3 is Vsin = Vexc sin A, where A is the rotor
angle in radians. Similarly, the voltage observed between S2 and S4 is
Vcos = Vexc cos A, where A is the rotor angle in radians. The two output voltages
remain in phase with each other relative to the excitation voltage, but differ in
magnitude and/or polarity (relative to excitation) as the rotor angle changes, as
shown in Figure 2-7.

Figure 2-7 SIN and COS Output Voltages vs. Rotor Angle

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Chapter 2 14
AI-256 Synchro / Resolver Mode

The output waveforms in resolver simulation mode for the AI-256 are shown
at 30°, 45°, and 135° in Figures 2-8, 2-10, and 2-9 respectively.

COS output
SIN output

Excitation

Figure 2-8 AI-256 Resolver Waveforms at 30° Rotor Angle

COS output

SIN output

Excitation

Figure 2-9 AI-256 Resolver Waveforms at 45° Rotor Angle

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AI-256 Synchro / Resolver Mode

SIN output
COS output

Excitation

Figure 2-10 AI-256 Resolver Waveforms at 135° Rotor Angle

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 DNx-AI-256 Synchro/Resolver/LVDT/RVDT Interface
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AI-256 Synchro / Resolver Mode

2.2 AI-256 The technical specifications for the DNx-AI-256 board (synchro/resolver mode)
Synchro / are listed in Table 2-1.
Resolver Table 2-1. DNx-AI-256 Technical Specifications (Synchro/Resolver Mode)
Specification
Inputs
Number of channels 2
Configuration Synchro (3-wire) or Resolver (4-wire) may be
selected via software
Resolution 16-bit
Accuracy ± 2.6 arc-minute
Frequency 50 Hz to 10 kHz
Signal Inputs 6Q
UP

7SNT
Input Impedance 478 kΩ ±10 kΩ
Acceleration 300 rps/s @ 60 Hz, 450 rps/s @ 400 Hz
1000 rps/s @ 4000 Hz
Step response 800 mS - 179° @ 60 Hz, 150 mS - 179° @ 2500 Hz
Update rate Max. rate is equal to the excitation frequency.
Reference output
Number of channels 2 (one per input channel)
Output voltage up to19.8 Vrms at 3.0 VA (see table on following
page for other output voltages)
Voltage resolution 16 bits
Reference Frequency 50 Hz to 10 kHz (±0.1%)
Synchro / Resolver Outputs
Number of channels 2 (total number of synchro/resolver inputs and
simulated outputs is limited to 2.)
Configuration Synchro (3-wire) or Resolver (4-wire)
Resolution 16-bit
Output Voltage up to 19.8 Vrms up to 2.4 VA. (see table)
Output Accuracy ±4 arc-minutes
Output readback and protection
Output protection Automatic shut down on overload
Voltage output monitoring ±70 mV, monitored at 1.3 Hz
Current output monitoring ±1.0 mA, monitored at 1.3 Hz
General Specifications
Operating temperature Tested -40 °C to +70 °C
Vibration IEC 60068-2-6 3 g, 10-500 Hz, sinusoidal
IEC 60068-2-64 3 g (rms), 10-500 Hz, broad-band random
Shock IEC 60068-2-27 100 g, 3 ms half sine, 18 shocks @ 6 orientations
30 g, 11 ms half sine, 18 shocks @ 6 orientations
Humidity 5 to 95%, non-condensing
MTBF 275,000 hours
Power consumption 6 Watt with no load
12 Watt maximum

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 DNx-AI-256 Synchro/Resolver/LVDT/RVDT Interface
Chapter 2 17
AI-256 Synchro / Resolver Mode

Output Drive Specifications (Synchro/Resolver):

Vrms Vpp Idcmax Irms VA max Rlmin






































































































4QFDJöDBUJPOT
BCPWF
BSF
GPS
B
TJOHMF
PVUQVU
DIBOOFM

5PUBM
PVUQVU
QPXFS
GPS
BMM
DIBOOFMT
DPNCJOFE
NBZ
OPU
FYDFFE

7"

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 DNx-AI-256 Synchro/Resolver/LVDT/RVDT Interface
Chapter 2 18
AI-256 Synchro / Resolver Mode

2.3 AI-256 This section describes the various operational modes available on the AI-256.
Operational For information about programming the board configuration and setting
Modes operating modes and parameters, refer to Chapters 4 and 5.

2.3.1 Synchro Table 2-2 lists the four operational modes for star and delta synchros. Each
Modes synchro mode also supports a z-grounded configuration (see Section 2.5.4 for
more information about z-grounding).
Table 2-2. AI-256 Synchro Operational Modes

Input/Output Excitation Description

Synchro Input Internal excitation AI-256 reads the voltages on the stator coils as analog
inputs and also supplies the excitation voltage to the rotor
coil.

See Section B-1 on page 41 for hardware connections

Synchro Input External excitation AI-256 reads the voltages on the stator coils as analog
inputs. An external source supplies the excitation voltage to
the rotor coil, which is readback by the AI-256 as an analog
input.

See Section B-3 on page 43 for hardware connections

Synchro Simulation Internal excitation The AI-256 outputs voltages that simulate the analog
signals from stator coils of a synchro. It also outputs an
analog excitation voltage generated in the AI-256.

See Section B-5 on page 45 for hardware connections

Synchro Simulation External excitation The AI-256 outputs voltages that simulate the analog
signals from stator coils of a synchro. Excitation voltage is
supplied by an external source and read back by the AI-256
as an analog input.

See Section B-7 on page 47 for hardware connections

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AI-256 Synchro / Resolver Mode

2.3.2 Resolver Table 2-3 lists the four operational modes for resolvers.
Modes
Table 2-3 AI-256 Resolver Operational Modes

Input/Output Excitation Description

Resolver Input Internal excitation AI-256 reads the voltages on the stator coils as analog
inputs and also supplies the excitation voltage to the rotor
coil(s).

See Section B-10 on page 50 for hardware connections

Resolver Input External excitation AI-256 reads the voltages on the stator coils as analog
inputs. An external source supplies the excitation voltage to
the rotor coil(s), which is readback by the AI-256 as an
analog input.

See Section B-11 on page 51 for hardware connections

Resolver Simulation Internal excitation The AI-256 outputs voltages that simulate the analog
signals from stator coils of a resolver. It also outputs an
analog excitation voltage generated in the AI-256.

See Section B-12 on page 52 for hardware connections

Resolver Simulation External excitation The AI-256 outputs voltages that simulate the analog
signals from stator coils of a resolver. Excitation voltage is
supplied by an external source and read back by the AI-256
as an analog input.

See Section B-13 on page 53 for hardware connections

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 DNx-AI-256 Synchro/Resolver/LVDT/RVDT Interface
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AI-256 Synchro / Resolver Mode

2.4 AI-256 The pinout of the DNx-AI-256 62-pin DB connector is shown in Figure 2-11.
Synchro /
Resolver am:
Pinout

Pin Signal Pin Signal Pin Signal

1 Rsvd 22 Gnd 43 Out A-
2 Out B+ 23 Out B- 44 Out A+
3 Rsvd 24 n/c 45 Gnd
4 In A+ 25 In A- 46 Rsvd
Chan 0 5 In B+ 26 In B- 47 n/c
6 Gnd 27 Rsvd 48 Rsvd
7 Out C+ 28 Out C- 49 Rsvd
8 Out D+ 29 Out D- 50 Rsvd
9 In C+ 30 In C- 51 Gnd Dashed line
10 In D+ 31 In D- 52 Rsvd represents
Dashed Line represents t
11 Rsvd 32 n/c 53 Out A- isolation
tion barrierbarrier
between cha
12 Out B+ 33 Out B- 54 Out A+
13 Rsvd 34 Gnd 55 Gnd
between channels
14 In A+ 35 In A- 56 Rsvd
15 In B+ 36 In B- 57 n/c
Chan 1 16 Gnd 37 Rsvd 58 Rsvd
17 Out C+ 38 Out C- 59 n/c
18 Out D+ 39 Out D- 60 Rsvd
19 Rsvd 40 Gnd 61 In C-
20 In D+ 41 In D- 62 In C+
21 Rsvd 42 n/c

Figure 2-11 Pinout Diagram for DNx-AI-256

NOTE: AI-256 has differential inputs and single-ended outputs; OutA-, OutB-,
OutC-, and OutD- are connected to the channel ground.

Before plugging any I/O connector into the Cube or RACK, be sure to remove
power from all field wiring. Failure to do so may cause severe damage to the
equipment.

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AI-256 Synchro / Resolver Mode

2.5 Connecting This section summarizes the hardware connections between the AI-256 and a
Synchro / synchro or resolver device. Refer to Appendix B for connection diagrams.
Resolver
Hardware

2.5.1 Synchro Synchro terminals are labeled S1, S2, S3 for the three stator windings, R1/R2
Wiring for the rotor, and C for the star synchro center point. Exc+/Exc– refer to the
excitation source terminals.
Table 2-4. Synchro Connections for Operational Modes
Signal Input Mode, Input Mode, Simulator Mode, Simulator Mode,
Name Pin No. Internal Excitation External Excitation Internal Excitation External Excitation
Ch 0 Ch 1 Star Delta Star Delta Star Delta Star Delta
In A+ 4 14 S1 S1 S1 S1 NC NC NC NC
In A- 25 35 C S3 C S3 NC NC NC NC
In B+ 5 15 S3 S2 S3 S2 NC NC NC NC
In B- 26 36 C S1 C S1 NC NC NC NC
In C+ 9 62 S2 S3 S2 S3 NC NC NC NC
In C- 30 61 C S2 C S2 NC NC NC NC
In D+ 10 20 NC NC Exc+ Exc+ NC NC Exc+ Exc+
In D- 31 41 NC NC Exc- Exc- NC NC Exc- Exc-
OutA+ 44 54 NC NC NC NC S1 S1 S1 S1
OutA- 43 53 NC NC NC NC C S3 C S3
OutB+ 2 12 NC NC NC NC S3 S2 S3 S2
OutB- 23 33 NC NC NC NC C S1 C S1
OutC+ 7 17 NC NC NC NC S2 S3 S2 S3
OutC- 28 38 NC NC NC NC C S2 C S2
OutD+ 8 18 R1 R1 NC NC R1 R1 NC NC
OutD- 29 39 R2 R2 NC NC R2 R2 NC NC
NC 24,47 32, 42, -- -- -- -- -- -- -- --
57, 59
GND 6, 22, 16, 34, -- -- -- -- -- -- -- --
45, 51 40, 55
Rsvd 1, 3, 11, 13, -- -- -- -- -- -- -- --
27, 46, 19, 21,
48, 49, 37, 56,
50, 52 58, 60

NOTE: Coils on a synchro can be labeled in two different ways. Looking at the
synchro from the shaft side with S1 at the top, S2 and S3 may follow in
either a counterclockwise or clockwise direction depending on the
manufacturer. Refer to “Troubleshooting” on page 26 if you have
questions when connecting synchro stator lines.

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AI-256 Synchro / Resolver Mode

2.5.2 Resolver Resolver terminals are S1/S3 and S2/S4 for stator windings and R1/R2 for the
Wiring rotor. Exc+ and Exc– refer to the excitation source terminals.
Table 2-5. Resolver Connections for Operational Modes
Signal Input Mode, Input Mode, Simulator Mode, Simulator Mode,
Name Pin No. Internal Excitation External Excitation Internal Excitation External Excitation
Ch 0 Ch 1 Resolver Resolver Resolver Resolver
In A+ 4 14 S1 S1 NC NC
In A- 25 35 S3 S3 NC NC
In B+ 5 15 S2 S2 NC NC
In B- 26 36 S4 S4 NC NC
In C+ 9 62 NC NC NC NC
In C- 30 61 NC NC NC NC
In D+ 10 20 NC Exc+(R1) NC Exc+
In D- 31 41 NC Exc-(R2) NC Exc-
OutA+ 44 54 NC NC S1 S1
OutA- 43 53 NC NC S3 S3
OutB+ 2 12 NC NC S2 S2
OutB- 23 33 NC NC S4 S4
OutC+ 7 17 NC(R2) NC Opt+(R2) NC
OutC- 28 38 NC(R4) NC Opt-(R4) NC
OutD+ 8 18 R1 NC Exc+(R1) NC
OutD- 29 39 R3 NC Exc-(R3) NC
NC 24,47 32, 42, -- -- -- --
57, 59
GND 6, 22, 16, 34, -- -- -- --
45, 51 40, 55
Rsvd 1, 3, 11, 13, -- -- -- --
27, 46, 19, 21,
48, 49, 37, 56,
50, 52 58, 60

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Chapter 2 23
AI-256 Synchro / Resolver Mode

2.5.3 Synchro Line- The AI-256 measures and simulates the peak-to-peak voltages (Vpp) across
to-Line stator and rotor coils. RACK/Cube logic and firmware computes the
Voltage corresponding angle from Vpp using the equations on page 7, where
Vpp=2*max(Vα).

S1

VPP and θ values

VPPS1

θ Calculations
S3
VPPS3

DAC
S2
VPPS2

TBD

DNx-AI-255 board
PowerDNA Driver
Star Synchro
Result to User

Figure 2-12 Peak-to-peak Voltage Measurement of Synchro

However, synchro documentation will often refer to line-to-line voltages instead
of peak-to-peak voltages. A line-to-line voltage is measured across two of the
three S1, S2, S3 wires or across R1, R2. For delta synchros, the coil voltages are
measured differentially and therefore equal the line-to-line voltages. For star
synchros, the line-to-line voltages can be derived from the page 7 equations by
substituting in the ground-referenced VS1, VS2, and VS3 for Vα, Vβ, and Vγ
respectively.
The resulting line-to-line amplitudes are:

Star Synchro Delta Synchro

V S1 – V S2 = 3kV R sin  V S2 – V S1 = kV R sin   + 30 

V S2 – V S3 = 3kV R sin   + 120  V S3 – V S2 = kV R sin   + 150 

V S3 – V S1 = 3kV R  t  sin   + 240  V S1 – V S3 = kV R sin   + 270 

NOTE: If the device uses a different reference shaft position from what’s shown
in Figure 2-1, θ will be offset by a constant.

RMS Voltage
Synchros are most commonly rated using a root mean squared (rms) voltage.
When supplying a voltage value to UEI API or interpreting debug waveforms on
an oscilloscope, you may need to convert between the max line-to-line RMS
voltage amplitude (VLL) from the synchro specification and the max peak-to-
peak voltage amplitude (VPP) used by the AI-256 driver.

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 DNx-AI-256 Synchro/Resolver/LVDT/RVDT Interface
Chapter 2 24
AI-256 Synchro / Resolver Mode

To convert between VLL and VPP, you can use the following formulas:

Coil Star Synchro Delta Synchro

Stator V LL V PP = 2 2  V LL  2.82843V LL
V PP = 2 2  ----------  1.63299V LL
3
Rotor
V PP = 2 2  V LL  2.82843V LL V PP = 2 2  V LL  2.82843V LL

Example:
• A star synchro with the rms excitation voltage of 23.5V will need a ground-
referenced peak-to-peak voltage of 66.4 V set for the AI-256.
66.4V ≈ 2.82843 * 23.5V
• A star synchro’s rms stator voltage of 11.8V (between any two stator
terminals) will have a maximum peak-to-peak voltage span of 19.26 V.
19.26V ≈ 1.63299 * 11.8V

Exercise caution when wiring and double-check that correct voltage is set on the
AI-256 to avoid overloading and permanently damaging
the synchro or resolver.

Low-level Macros
Low-level API includes the following software macros for converting star synchro
stator voltages:
• #define DQ_AI255_RMS_LN_LN_TO_PP(V) ((V)*1.633)
where input parameter V is VLL, and the resulting output is VPP.
• #define DQ_AI255_RMS_LN_LN_TO_RMS(V) ((V)*0.5774)
where input parameter V is the line-to-line voltage VLL, and the result is the
ground-referenced stator voltage in volts RMS (VRMS). The constant 0.5774 is
1   3 .

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 DNx-AI-256 Synchro/Resolver/LVDT/RVDT Interface
Chapter 2 25
AI-256 Synchro / Resolver Mode

2.5.4 Z-grounded It is possible to ground the Z (S3) lines of some synchros to the vehicle’s
Mode common ground to save on wiring - this is called a synchro in z-grounded mode.
In hardware, the S3 input/output on the AI-256 is left unconnected for
z-grounded synchros. See Figure 2-13 and Section B-9 on page 49 for
connection diagrams.

VPPS1 S1

VPPS3

DAC
VPPS2 S2

TBD
S3
AGND

AI-256
Star Synchro

Figure 2-13 Connecting Star Synchro in Z-grounded Mode

Software Modes
Z-grounded delta synchros do not require any software changes since their coil
voltages are already measured differentially.
Z-grounded star synchros DO require users to select a special software mode in
their AI-256 program:
• When using the Framework API, the enum UeiSynchroZGroundMode
is used to select z-grounded mode. Refer to Chapter 4 for more
information about programming using the UEIDAQ Framework API.
• When using low-level API, defines listed in the table below are used to
set the different z-grounded modes; refer to Chapter 5 for information
on low-level software programming.

Mode of Operation Description

DQ_AI255_MODE_SI_INTZ Synchro input, internal excitation, Z grounded

DQ_AI255_MODE_SI_EXTZ Synchro input, external excitation, Z grounded

DQ_AI255_MODE_SS_INTZ Synchro output, internal excitation, Z grounded

DQ_AI255_MODE_SS_EXTZ Synchro output, external excitation, Z grounded

Table 2-6. Z-grounded modes of operation from powerdna.h

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 DNx-AI-256 Synchro/Resolver/LVDT/RVDT Interface
Chapter 2 26
AI-256 Synchro / Resolver Mode

2.5.5 Trouble- This section describes some of the conditions observed when the synchro is not
shooting wired correctly to the board. Incorrect wiring can be as mild as inaccurate rotor
position or as severe as permanently damaging the synchro.
In the mildest cases, the synchro or rotor lines may be in incorrect positions in
the terminal panel. Reversing the rotor (Vext+, Vext-) or stator (S1, S2, S3) wires
can cause the position of the rotor to be at a wrong angle, or rotate clockwise.
In the more severe cases, the rotor may move in a jerky or erratic manner, the
synchro may hum and may be warm/hot to the touch, indicating a possible open
connection. Warm or hot synchros may also indicate a short circuit.
The AI-256 board has overvoltage protection up to 350Vrms and thermal
protection; however, the synchro may be permanently damaged by a bad
voltage setting. It is recommended to check the configured voltage with an
oscilloscope (best set to measure in true RMS mode) to ensure that the output
voltages are correct. Unusual waveforms on an oscilloscope may indicate that
thermal limits are being reached (normally due to an overloaded synchro), and
waveforms that drop to zero may indicate that the overvoltage protection was
breached and the board has shut down.
Overvoltage messages appear on the serial console and print as follows:
Ch0 OC: disabling ist=<...>
Ch1 OC: disabling ist=<...>

Alternatively, overvoltage conditions can be monitored in user applications

written with the low-level API; the DqCmdReadStatus() API returns as
STS_POST_OVERCURRENT in the POST word of the board status in the low
level framework. Refer to SampleGetStatus.c for a programming example of
reading the status. (See Section 5.2 for the location of sample programs.)

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 DNx-AI-256 Synchro / Resolver / LVDT / RVDT Interface
Chapter 3 27
AI-256 LVDT / RVDT Mode

Chapter 3 AI-256 LVDT / RVDT Mode

This document describes the feature set and use of the DNx-AI-256 interface
board when used in LVDT/RVDT applications. The following information is
included in this chapter:
• LVDT / RVDT Overview (Section 3.1)
• AI-256 LVDT / RVDT Specification (Section 3.2)
• AI-256 LVDT / RVDT Pinout (Section 3.3)
• AI-256 LVDT / RVDT Operating Modes (Section 3.4)
• Setting Operating Parameters (Section 3.5)

3.1 LVDT / RVDT The DNx-AI-256 can be used as a 2-channel LVDT/RVDT input or simulated
Overview output interface for UEI’s data acquisition systems. It is suited for a wide variety
of linear and rotational motion and/or position measurements in industrial and
military applications.
Each channel can be configured as either a 5- or 6-wire LVDT/RVDT analog
input channel that connects to an LVDT/RVDT sensor or as a 4-, 5-, or 6-wire
LVDT/RVDT output/simulator, which can be used to drive simulator inputs or to
test LVDT/RVDT measurement products.
Additionally, each channel can be configured to operate with excitation
generated internally to the AI-256 or supplied from an external source. External
excitation voltage is read as an input to the AI-256 channel and used as a
reference for computation of the sensor core position.
The wiring connections for the various modes of operation are described in
detail in “AI-256 LVDT / RVDT Operating Modes” on page 30.

3.2 AI-256 LVDT / Technical specifications for the DNx-AI-256 board (LVDT/RVDT Mode) are listed
RVDT in Table 3-1 and extend the features described previously.
Specification
Table 3-1. DNx-AI-256 (LVDT/RVDT Mode) Specifications

Simulation Outputs
Number of channels





















Configuration 2-, 3- or 4-wire
Resolution 16-bit
Output Accuracy 0.1%
Output Voltage





























Vrms
NBY

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 DNx-AI-256 Synchro / Resolver / LVDT / RVDT Interface
Chapter 3 28
AI-256 LVDT / RVDT Mode

3.3 AI-256 LVDT / The pinout for the AI-256 in LVDT/RVDT mode is shown below:
RVDT Pinout

Pinout Diagram
(-7%537%5
.PEF):

Pin Signal Pin Signal Pin Signal

1 Rsvd 22 Gnd 43 Out A-
1
2 Out B+
1 23 Out B-
1 44 Out A+
1
3 Rsvd 24 n/c 45 Gnd
4 In A+
4 25 In A-
4 46 Rsvd
Chan 0 5 In B+
4 26 In B-
4 47 n/c
6 Gnd 27 Rsvd 48 Rsvd
7 Out C+ 28 Out C- 49 Rsvd
8 Out D+
&YD0VU 29 Out D-
&YD0VU 50 Rsvd
9 In C+ 30 In C- 51 Gnd
10 In D+
&YD*O 31 In D-
&YD*O 52 Rsvd Dashed Line represents the isola-
11 Rsvd 32 n/c 53 Out A-
1 tion barrier between channels
12 Out B+
1
33 Out B-
1 54 Out A+
1
13 Rsvd 34 Gnd 55 Gnd
14 In A+
4
35 In A-
4 56 Rsvd
15 In B+
4
36 In B-
4 57 n/c
Chan 1 16 Gnd 37 Rsvd 58 Rsvd
17 Out C+ 38 Out C- 59 n/c
Out D+
&YD0VU
18
19 Rsvd
39
40
Out D-
&YD0VU
Gnd
60
61
Rsvd
In C-
Note:
20 In D+
&YD*O 41 In D-
&YD*O 62 In C+ InC± and OutC±
21 Rsvd 42 n/c are not used.

Figure 3-1 DNx-AI-256 LVDT/RVDT Pinout

NOTE:
1. Use S1+ and S1- for S1 secondary winding, analog differential input con-
nections (input mode).
2. Use S2+ and S2- for S2 secondary winding analog differential input con-
nections (input mode).
3. When the AI-256 is configured in simulator output mode, P1+ and P1- are
used to provide one of the two simulated measurement outputs (S1 sec-
ondary winding).
4. When the AI-256 is configured in simulator output mode, P2+ and P2- are
used to provide the second of the two simulated measurement outputs (S2
secondary winding).

NOTE: AI-256 has differential inputs and single-ended outputs; OutA-, OutB-,
OutC-, and OutD- are connected to the channel ground.

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 DNx-AI-256 Synchro / Resolver / LVDT / RVDT Interface
Chapter 3 29
AI-256 LVDT / RVDT Mode

The following table is provided as a reference for connecting sensors to the

various I/O pins.

Table 1-1. DNx-AI-256 Pin Connections by Channel Number

Signal Name Input/Output Ch 0 Ch 1
P1+ OutA+ 44 54
P1- OutA- 43 53
P2+ OutB+ 2 12
P2- OutB- 23 33
S1+ InA+ 4 14
S1- InA- 25 35
S2+ InB+ 5 15
S2- InB- 26 36
Exc In+ InD+ 10 20
Exc In- InD- 31 41
Exc Out+ OutD+ 8 18
Exc Out- OutD- 29 39
Rsvd Rsvd 1, 3, 27, 46, 11, 13, 19, 21,
48, 49, 50, 52 37, 56, 58, 60
NC NC 24, 47 32, 42, 57, 59
(InC/OutC±) NC 7, 9, 28, 30 17, 38, 61, 62
Gnd Gnd 6, 22, 45, 51 16, 34, 40, 55

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 DNx-AI-256 Synchro / Resolver / LVDT / RVDT Interface
Chapter 3 30
AI-256 LVDT / RVDT Mode

3.4 AI-256 LVDT / The DNx-AI-256 can be used in any of the LVDT/RVDT operating modes
RVDT summarized in Table 3-2:
Operating
Modes
Table 3-2 AI-256 Modes of Operation

Analog Input or Sensor Wire Internal or

Simulated Output Configuration External Excitation Section Reference
Analog Input Mode 5- or 6-wire Internal Excitation Section 3.4.1.1

Analog Input Mode 5- or 6-wire External Excitation Section 3.4.1.2

Simulated Output 5- or 6-wire External Excitation Section 3.4.2.1

Simulated Output 4-wire External Excitation Section 3.4.2.2

Simulated Output 5- or 6-wire Internal Excitation Section 3.4.2.3

Simulated Output 4-wire Internal Excitation Section 3.4.2.4

3.4.1 LVDT / RVDT When a channel is configured as an LVDT/RVDT analog input device, the
Analog Input voltages on the secondary windings of the sensor are connected as AC analog
Mode inputs to the AI-256 through S1± and S2±.
The ADC converted values are continuously integrated/divided to compute the
moving averages of both inputs.These average values are called Sa and Sb, one
for each secondary winding. The readings of the excitation voltage applied to the
primary winding are also averaged to compute the averaged excitation value,
Se.
Either the Sa and Sb input, or the input with the highest amplitude, is monitored
for a desired direction of zero crossing. When a zero crossing is detected, Sa,
Sb, and Se are latched and the values are further processed to compute the
24-bit values (Sa-Sb)/(Sa+Sb) and/or (Sa-Sb)/Se. Results are then adjusted as
needed with a 24-bit gain and offset. These values are also used to compute the
physical position of the magnetic core within the LVDT/RVDT sensor. The
computed results are then passed to the averaging/decimation engine.

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 DNx-AI-256 Synchro / Resolver / LVDT / RVDT Interface
Chapter 3 31
AI-256 LVDT / RVDT Mode

3.4.1.1 Analog Input, For an AI-256 configured as an analog input 6-wire device using internal
Internal excitation, the Sa signal from the S1 secondary winding is connected to S1+ and
Excitation, 5/6- S1-, and the Sb signal from S2 winding is connected to S2+ and S2- as shown
wire in Figure 3-2.
Configuration For a 5-wire device, connect S1+ and S2+ with the same configuration as the
6-wire device, but connect S1- and S2- to the common of the sensor’s
secondary windings.

AI-256 6-wire LVDT

Pin No. Secondary
Ch0 Ch1
Primary S1 Sa
8 18 Exc Out+
Vexc P
29 39 Exc Out-
S2 Sb
4 14 S1+
25 35 S1-

5 15 S2+

26 36 S2-

6, 22, 16,34 GND

45,51 40,55

(Excitation generated Internal to AI-256

and output to the LVDT sensor via Exc Out± )

Figure 3-2 6-wire LVDT Device with AI-256 in Analog Input Mode,
Internal Excitation

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 DNx-AI-256 Synchro / Resolver / LVDT / RVDT Interface
Chapter 3 32
AI-256 LVDT / RVDT Mode

3.4.1.2 Analog Input, For an AI-256 configured as an analog input to a 6-wire device using external
Internal excitation, the Sa signal from S1 secondary is connected to S1+ and S1-, and
Excitation, 5/6- the Sb signal from S2 is connected to S2+ and S2-, as shown in
wire Figure 3-3.
configuration The external Vref excitation voltage is not connected to the AI-256 channel in the
Mode 2, 5-/6-wire configuration. Core position is calculated exclusively from the
Sa and Sb values.
For a 5-wire device, S1+ and S2+ are connected with the same configuration as
the 6-wire device (Figure 3-3), but S1- and S2- are connected to the common of
the sensor’s secondary windings.

AI-256 6-wire LVDT

Pin No. Secondary
Ch0 Ch1
Primary S1 Sa
8 18 Exc Out+ N/C
Vexc P
29 39 Exc Out- N/C
S2 Sb
4 14 S1+
25 35 S1-

5 15 S2+

26 36 S2-

6, 22, 16,34 Avionics Equipment

GND
45,51 40,55 Excitation Voltage Source

(Excitation generated by Avionics Equipment

External to AI-256.)

Figure 3-3 6-wire LVDT Device with AI-256 in Analog Input Mode,
External Excitation

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 DNx-AI-256 Synchro / Resolver / LVDT / RVDT Interface
Chapter 3 33
AI-256 LVDT / RVDT Mode

3.4.2 Simulator When a channel is configured as a simulator output device, the channel
Output Mode simulates the operation of the secondary windings of an LVDT/RVDT sensor. In
this mode, the DAC generates analog voltages on P1± and/or P2± to represent
the output voltages of LVDT/RVDT secondary windings.

3.4.2.1 Simulator When simulating a 6-wire LVDT/RVDT sensor, the AI-256 channel configured as
Output, a simulator output drives signals from P1± and P2± to simulate the secondary
External windings of the LVDT/RVDT, as shown in Figure 3-6.
Excitation, 5/6- The excitation voltage is provided external to the AI-256 channel and connected
wire to Exc In±.
configuration When simulating a 5-wire LVDT/RVDT sensor, P1- and P2- should be
disconnected from the AI-256 and the 5-wire common node on the avionics
equipment will be connected to channel ground.
.

AI-256 simulates 6-wire LVDT

AI-256
Pin No.
Ch0 Ch1
44 54 P1+ InA+
simulated S1 windings (Sa)
43 53 P1- InA- Avionics
Equipment
2 12 P2+ InB+
simulated S2 windings (Sb)
23 33 P2- InB-

10 20 Exc In+ Exc+

31 41 Exc In- Exc-

8 18 Exc Out+ N/C Vexc

29 39 Exc Out- N/C

Excitation
Voltage Source
6, 22 16,34 GND
45,51 40,55

(AI-256 simulates the secondary windings

of an LVDT sensor. Position is software defined.
Excitation generated External to AI-256.)

Figure 3-4 6-wire LVDT Device with AI-256 in Simulator Output

Mode, External Excitation

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 DNx-AI-256 Synchro / Resolver / LVDT / RVDT Interface
Chapter 3 34
AI-256 LVDT / RVDT Mode

3.4.2.2 Simulator When simulating a 4-wire LVDT/RVDT sensor, the AI-256 channel configured as
Output, a simulator output drives signals from P1± that simulate the secondary windings
External of the LVDT/RVDT, as shown in Figure 3-5.
Excitation, 4- The excitation voltage is provided external to the AI-256 channel and connected
wire to Exc In±.
configuration

AI-256 simulates 4-wire LVDT

AI-256
Pin No.
Ch0 Ch1
simulated S1/S2 windings
44 54 P1+ InA+
Vout
43 53 P1- InA- Avionics
Equipment
2 12 P2+ N/C InB+

23 33 P2- N/C InB-

10 20 Exc In+ Exc+

31 41 Exc In- Exc-

8 18 Exc Out+ N/C Vexc

29 39 Exc Out- N/C

Excitation
Voltage Source
6, 22 16,34 GND
45,51 40,55

(AI-256 simulates the secondary windings

of an LVDT sensor. Position is software defined.
Excitation generated External to AI-256.)

Figure 3-5 4-wire LVDT Device with AI-256 in Simulator Mode,

External Excitation

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 DNx-AI-256 Synchro / Resolver / LVDT / RVDT Interface
Chapter 3 35
AI-256 LVDT / RVDT Mode

3.4.2.3 Simulator When simulating a 6-wire LVDT/RVDT sensor, the AI-256 channel configured as
Output, a simulator output drives signals from P1± and P2± to simulate the secondary
Internal windings of the LVDT/RVDT, as shown in Figure 3-6.
Excitation, 5/6- The excitation voltage is provided internal to the AI-256 channel and connected
wire to Exc Out±.
configuration When simulating a 5-wire LVDT/RVDT sensor, P1- and P2- should be
disconnected from the Avionics Equipment.
.

AI-256 simulates 6-wire LVDT

AI-256
Pin No.
Ch0 Ch1
44 54 P1+ InA+
simulated S1 windings (Sa)
43 53 P1- InA- Avionics
Equipment
2 12 P2+ InB+
simulated S2 windings (Sb)
23 33 P2- InB-

10 20 Exc In+ N/C Exc+

31 41 Exc In- N/C Exc-

8 18 Exc Out+
Vexc
29 39 Exc Out-

6, 22 16,34 GND
45,51 40,55

(AI-256 simulates the secondary windings

of an LVDT sensor. Position is software defined.
Excitation generated internal to AI-256.)

Figure 3-6 6-wire LVDT Device with AI-256 in Simulator Output

Mode, External Excitation

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 DNx-AI-256 Synchro / Resolver / LVDT / RVDT Interface
Chapter 3 36
AI-256 LVDT / RVDT Mode

3.4.2.4 Simulator When simulating a 4-wire LVDT/RVDT sensor, the AI-256 channel configured as
Output, a simulator output drives signals from P1± that simulate the secondary windings
Internal of the LVDT/RVDT, as shown in Figure 3-7.
Excitation, 4- The excitation voltage is provided internal to the AI-256 channel and connected
wire to ExcOut±.
configuration

AI-256 simulates 4-wire LVDT

AI-256
Pin No.
Ch0 Ch1
simulated S1/S2 windings
44 54 P1+ InA+
Vout
43 53 P1- InA- Avionics
Equipment
2 12 P2+ N/C InB+

23 33 P2- N/C InB-

10 20 Exc In+ N/C Exc+

31 41 Exc In- N/C Exc-

8 18 Exc Out+
Vexc
29 39 Exc Out-

6, 22 16,34 GND
45,51 40,55

(AI-256 simulates the secondary windings

of an LVDT sensor. Position is software defined.
Excitation generated internal to AI-256.)

Figure 3-7 4-wire LVDT Device with AI-256 in Simulator Mode

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 DNx-AI-256 Synchro / Resolver / LVDT / RVDT Interface
Chapter 3 37
AI-256 LVDT / RVDT Mode

3.4.3 Simulator The AI-256 can be configured to use one or more channels as simulator outputs
Output to and connect them to one or more channels configured as LVDT/RVDT input
LVDT/RVDT interfaces on the same or different AI-256 boards, as shown in Figure 3-8.
Input Mode

Channel 0 -- AI-256 in 6-wire Channel 1 -- AI-256 in 6-wire

Analog Input Mode with Internal Excitation Simulator Output Mode with External Excitation

AI-256 AI-256
Pin No. Pin No.
Ch0 Ch1

8 ExcOut+ P1+ 54

29 ExcOut- Vexc P1- 53

P2+ 12

P2- 33

4 S1+ ExcIn+ 20

25 S1- ExcIn- 41

5 S2+

26 S2- Simulated analog

measurements
6, 22, GND 16,34
GND 40,55
45,51

Figure 3-8 Ch1 Simulated Output Connected to Ch0 Analog Input

(6-wire)
As shown in the diagram, excitation voltage is provided by Channel 0 (Exc Out+
to Exc Out-) DAC.
Channel 1 outputs two simulated measurement signals (P1+ to P1-) and (P2+ to
P2-) from its DACs to the secondary inputs on Channel 0.

3.5 Setting For detailed instructions for configuring the AI-256 (LVDT/RVDT Mode) board
Operating and setting operating modes and parameters, refer to the Framework functions
Parameters CreateSimulatedLVDTChannel() and CreateLVDTChannel() or the
low level API function, DqAdv256SetModeLvdt().
Framework functions are described in the Framework API Reference Manual,
with an overview in Chapter 4.
Low level functions are described in the PowerDNA API Reference Manual, with
an overview in Chapter 5.

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 DNx-AI-256 Synchro/Resolver/LVDT/RVDT Interface
Chapter 4 38
Programming with the High-level API

Chapter 4 Programming with the High-level API

This chapter provides the following information about using the UeiDaq high-
level Framework API to program the DNx-AI-256:
• About the High-level Framework (Section 4.1)
• Creating a Session (Section 4.2)
• Configuring the Resource String (Section 4.3)
• Configuring for Synchro / Resolver Input (Section 4.4)
• Configuring for Simulated Synchro/Resolver Output (Section 4.5)
• Configuring for LVDT /RVDT Input (Section 4.6)
• Configuring for Simulated LVDT / RVDT Output (Section 4.7)
• Configuring the Timing (Section 4.8)
• Reading Data (Section 4.9)
• Writing Data (Section 4.10)
• Cleaning-up the Session (Section 4.11)

4.1 About the UeiDaq Framework is object oriented and its objects can be manipulated in the
High-level same manner from different development environments, such as Visual C++,
Framework Visual Basic, or LabVIEW.
UeiDaq Framework is bundled with examples for supported programming
languages. Examples are located under the UEI programs group in:
• Start » Programs » UEI » Framework » Examples
The following sections focus on the C++ API, but the concept is the same no
matter which programming language you use.
Please refer to the “UeiDaq Framework User Manual” for more information on
use of other programming languages.

4.2 Creating a The Session object controls all operations on your PowerDNx device. Therefore,
Session the first task is to create a session object:

// create a session object for input, and a session object for output

CUeiSession aiSession;
CUeiSession aoSession;

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4.3 Configuring UeiDaq Framework uses resource strings to select which device, subsystem
the Resource and channels to use within a session. The resource string syntax is similar to a
String web URL:

<device class>://<IP address>/<Device Id>/<Subsystem><Channel list>

For PowerDNA and RACKtangle, the device class is pdna.

For example, the following resource string selects analog input lines 0,1 on
device 1 at IP address 192.168.100.2: “pdna://192.168.100.2/Dev1/Ai0,1”

4.4 Configuring The AI-256 can be configured for a synchro or resolver input.
for Synchro / Use the method CreateSynchroResolverChannel() to program the input
Resolver channels and parameters associated with each channel.
Input The following call configures the analog input channels of an AI-256 set as
device 1:

// Configure session synchro/resolver input

aiSession.CreateSynchroResolverChannel(
"pdna://192.168.100.2/Dev1/Ai0,1",
UeiSynchroMode,
3.0,
5000.0,
false);

It configures the following parameters:

• Sensor Mode: the type of sensor (synchro or resolver) connected to the
input channel.
• Excitation Voltage: the amplitude of the excitation sine wave in volts
RMS.
• Excitation Frequency: the frequency of the excitation sine wave.
• External Excitation: specifies whether you wish to provide external
excitation or use the excitation provided by the AI-256.
If you want to use different parameters for each channel, you can call
CreateSynchroResolverChannel() multiple times with a different set of
channels (0 or 1) in the resource string.
Note that the external excitation amplitude value that comes back from firmware
is a peak-to-peak voltage that is converted to an RMS value by the framework
on the assumption that it is a sinusoidal excitation signal. However, position
transducers may use a square wave or a pulse for excitation. As a result, the
amplitude for these signals will appear to be low, and only serve to verify the
existence of a signal. When using the framework, the actual RMS or peak-to-
peak amplitude of the excitation signal should be measured using an
oscilloscope to ensure correctness.

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4.5 Configuring The AI-256 can be configured as a synchro or resolver output. When using the
for Simulated AI-256 in Synchro/Resolver Mode, you can also use the AI-256 to simulate a
Synchro/ Synchro or a Resolver output.
Resolver The following call configures an analog output channel of an AI-256 set as
Output device 1:

// Configure session for synchro/resolver output

aoSession.CreateSimulatedSynchroResolverChannel(
"pdna://192.168.100.2/Dev1/AO0",
UeiResolverMode,
3.0,
5000.0,
false);

It configures the following parameters:

• Sensor Mode: the type of sensor (synchro or resolver) to be simulated.
• Excitation Voltage: the amplitude of the excitation sine wave in volts
RMS.
• Excitation Frequency: the frequency of the excitation sine wave.
• External Excitation: specifies whether you wish to provide external
excitation or use the excitation provided by the AI-256.

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4.6 Configuring The method CreateLVDTChannel() is used to program the input channels
for LVDT / and parameters associated with each channel.
RVDT Input The following call configures an analog input channel of an AI-256 set as
device 1:

// Configure session LVDT/RVDT input

aiSession.CreateLVDTChannel("pdna://192.168.100.2/Dev1/Ai0:1",
-10.0, //Minimum range
10.0, //Maximum range
1000.0, //Sensor sensitivity
UeiLVDTFiveWires, //Wiring scheme
6.0, //Excitation voltage
400.0, //Excitation frequency
false); //External excitation

CreateLVDTChannel() configures the following parameters:

• Minimum range: minimum value you expect to measure.
The unit is the distance unit specified by your LVDT sensitivity. For
example, if your LVDT sensitivity is given in mV/V/mm, the distance unit
is mm. Similarly for RVDTs the unit is the angle unit used in the
sensitivity.
• Maximum range: maximum value you expect to measure.
The unit is the position unit specified by your LVDT sensitivity. For
example if your LVDT sensitivity is given in mV/V/mm, the distance unit
is mm. Similarly for RVDTs, the unit is the angle unit used in the
sensitivity.
• Sensor Sensitivity: the sensor sensitivity specified in
mV/V/<position unit>.
The position unit specifies the unit of the min. and max. range as well as
the unit of the data read from the input channels.
• Wiring Scheme: the wiring scheme used to connect the LVDT/RVDT to
the AI-256. Note that the AI-256 can be used as an analog input for
5-/6-wire LVDT/RVDTs (UeiLVDTFiveWires).
• Excitation voltage: the amplitude in volt RMS of the excitation sine
wave.
• Excitation frequency: the frequency of the excitation sine wave.
• External excitation: specifies whether you wish to provide external
excitation or use the excitation provided by the AI-256.

If you want to use different parameters for each channel, you can call
CreateLVDTChannel( ) multiple times with a different set of channels in the
resource string each time.

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4.7 Configuring The AI-256 can be used to simulate an LVDT or RVDT output.
for Simulated The following call configures an analog output channel on an AI-256 set as
LVDT / RVDT device 1:
Output
// Configure session for simulated LVDT/RVDT output

aoSession.CreateSimulatedLVTDChannel(
"pdna://192.168.100.2/Dev1/AO0",
153.65 //Sensor sensitivity
UeiLVDTFiveWires, //Wiring scheme
6.0, //Excitation voltage
400.0); //Excitation frequency

CreateSimulatedLVTDChannel() configures the following parameters:

• Sensor Sensitivity: the sensor sensitivity specified in
mV/V/<position unit>. The position unit specifies the unit of the data
written to the channel.
• Wiring Scheme: the wiring scheme used to connect the simulated
LVDT/RVDT to the reading device.
• Excitation Voltage: the amplitude in volt RMS of the excitation sine
wave.
• Excitation Frequency: the frequency of the excitation sine wave.

4.8 Configuring You can configure the AI-256 to run in simple mode (point by point).
the Timing In simple mode, the delay between samples is determined by software on the
host computer.
The following sample shows how to configure the simple mode. Please refer to
the “UeiDaq Framework User’s Manual” to learn how to use other timing modes.

// configure timing of input for point-by-point (simple mode) for AI

aiSession.ConfigureTimingForSimpleIO();

// configure timing of input for point-by-point (simple mode) for AO

aoSession.ConfigureTimingForSimpleIO();

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4.9 Reading Data Reading data is done using reader object(s). The following sample code shows
how to create a scaled reader object and read samples.

// create a reader and link it to the analog-input session’s stream

CUeiAnalogScaledReader aiReader(aiSession.GetDataStream());
// the buffer must be big enough to contain one value per channel

double data[2];

// read one scan, where the buffer will contain one value per channel

aiReader.ReadSingleScan(data);

4.10 Writing Data Writing data is done using a writer object.

The following sample shows how to create a scaled writer and write samples.
The AI-256 simulates angle positions entered in radians.

// create a writer and link it to the session’s analog-output stream

CUeiAnalogScaledWriter aoWriter(aoSession.GetDataStream());
// to write a value, the buffer must contain one value per channel

double data[2] = { 1.0, 2.0 };

// write one scan, where the buffer contains one value per channel

aoWriter.WriteSingleScan(data);

4.11 Cleaning-up The session object will clean itself up when it goes out of scope or when it is
the Session destroyed. To reuse the object with a different set of channels or parameters,
you can manually clean up the session as follows:

// clean up the sessions

aiSession.CleanUp();
aoSession.CleanUp();

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Chapter 5 Programming with the Low-level API

This chapter provides the following information about programming the AI-256
using the low-level API:
• About the Low-level API (Section 5.1)
• Low-level Programming Techniques (Section 5.2)
• DNx-AI-256 Modes of Operation (Section 5.3)
• Programming AI-256 for Synchro/Resolver Devices (Section 5.4)
• Programming Power Monitor on AI‒256 (Section 5.6)

NOTE: This chapter contains descriptions of the low-level functions that may be
used in programming the AI-256.
Note that AI-255 functions can be used to program the Synchro /
Resolver functionality of the AI-256.

5.1 About the The low-level API provides direct access to the DAQBIOS protocol structure and
Low-level API registers in C. The low-level API is intended for speed-optimization, when
programming unconventional functionality, or when programming under Linux or
real-time operating systems.
When programming in Windows OS, however, we recommend that you use the
UeiDaq high-level Framework API (see Chapter 4). The Framework extends the
low-level API with additional functionality that makes programming easier and
faster, and additionally the Framework supports a variety of programming
languages and the use of scientific software packages such as LabVIEW and
Matlab.
For additional information regarding low-level programming, refer to the
“PowerDNA API Reference Manual” located in the following directories:
• On Linux systems:
<PowerDNA-x.y.z>/docs
• On Windows systems:
Start » All Programs » UEI » PowerDNA » Documentation

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5.2 Low-level Application developers are encouraged to explore existing source code
Programming examples when first programming the AI-256. Sample code provided with the
Techniques installation is self-documented and serves as a good starting point.
Code examples are located in the following directories:
• On Linux systems: <PowerDNA-x.y.z>/src/DAQLib_Samples
• On Windows: Start » All Programs » UEI » PowerDNA » Examples

Sample code has the name of the I/O boards being programmed embedded in
the sample name. For example, Sample256ReadLVDT contains sample code
for running the an AI-256 in LVDT mode.

NOTE: The AI-256 provides similar capabilities as the AI-255 (Synchro/

Resolver) and AI-254 (LVDT/RVDT). Please refer to sample code for
these products as additional examples, (i.e., Sample255).

5.2.1 Data The AI-256 supports the following acquisition modes:

Collection • Immediate (point-to-point): Designed to provide easy access to a single I/O
Modes board at a non-deterministic pace. Acquires a single data point per channel.
Runs at a maximum of 100 Hz.
• RtDMAP: Designed for closed-loop (control) applications. Users set up a
“map” of I/O boards and channels from which to acquire data. Input data is
stored on the I/O board at a rate paced by its hardware clock; a single API
call (refresh) paced by the user application causes data to be collected
directly from the I/O board and packed for delivery to the user application.
- RtDMAP collects 1 data sample per channel

API that implement data acquisition modes and additional mode descriptions
are provided in the PowerDNA API Reference Manual.

5.3 DNx-AI-256 The modes of operation supported by an DNx-AI-256 channel are:

Modes of • Synchro Input • LVDT Input (5/6-wire)
Operation
• Resolver Input • RVDT Input (5/6-wire)
• Synchro Output/Simulator • LVDT Simulator Output (4/5/6-wire)
• Resolver Output/Simulator • RVDT Simulator Output (4/5/6-wire)

NOTE: Synchro and Resolver modes of operation are described in

Section 2.3 on page 18.
LVDT / RVDT modes of operation are described in Section 3.4 on page
30.

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5.4 Programming This section describes the use of the AI-256 in Synchro/Resolver applications.
AI-256 for For applications that use LVDTs and RVDTs, refer to “Programming AI-256 for
Synchro/ LVDT / RVDT Devices” on page 52.
Resolver
Devices

5.4.1 Synchro / Table 5-1 provides a summary of AI-256-specific functions. All low-level
Resolver Low- functions are described in detail in the PowerDNA API Reference Manual.
level Function
Table 5-1. Summary of Low-level Synchro / Resolver API Functions for DNx-AI-256

Function Description

DqAdv255SetMode Sets synchro or resolver operating modes per channel

DqAdv255SetExt Set up extra (additional) parameters

DqAdv255SetExcitation Sets excitation frequency and amplitude in internal

exitation mode

DqAdv255GetWFMeasurements Returns the measured parameters of waveform on

selected input(s)

DqAdv255MeasureWF Simple form of DqAdv255GetWFMeasurements

DqAdv255Enable Enables/disables operation on specified channels

DqAdv255Read Reads the calculated angle or special data for selected

channels (point-to-point mode)

DqAdv255Write Writes a simulated position of a synchro or resolver or

special data (point-to-point mode)

DqAdv255ConvertSim Converts angle to raw data representation for gain and

phase control

DqAdv255WriteBin Writes an angle or special data for selected channels

The following AI-256 superset of functions extend the abilities of the AI-255:

Function Description

DqAdv256SetModeSynchroResolver Identical to DqAdv255SetMode()

DqAdv256Enable Enable/disable operations for channels specified in channel

list (can also use DqAdv255Enable)

DqAdv256WriteSynchroResolver Identical to DqAdv255Write()

DqAdv256ReadPADC Returns the power monitor ADC readings from an AI-256

DqAdv256SetAll Sets up most of the AI-256 configuration parameters.

DqAdv256GetWFMeasurements Returns the measured parameters of waveform on the input

line(s) (same as DqAdv255GetWFMeasurements for
synchro/resolver modes)

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5.4.2 Configuring The DNx-AI-256 can be configured to use internal or external excitation. For
Synchro/ internally generated excitation, configure the excitation frequency and level
Resolver before configuring the mode of a channel. For external excitation, API are
provided for measuring the excitation frequency and level. These parameters
Excitation
are needed when setting the mode.

5.4.2.1 Reading When using external excitation, use the DqAdv255GetWFMeasurements API
External to measure the external excitation. It returns a structure that holds the acquired
Excitation waveform data.
The following is an example of setting up the DqAdv255GetWFMeasurements
API for external excitation measurement:

NOTE: Many of the defines and structure types for the AI-255 are also used for
the AI-256 in synchro/resolver mode. For example, the waveform return
structure in this example is of type WFPRM_255, and the waveform
measurement setup structure is WFMEASURE_255.
// CHANNELS is 2 for the AI-256
// WFMEASURE_255 & WFPRM_255 are structures for waveform setup & data
for(i=0; i<CHANNELS; i++) {

WFMEASURE_255 param;
WFPRM_255 chan_m[DQ_AI255_ADCS]; //A/D per channel

// Configure channel list

// Set gain = gain of 1
cl[i] = i | DQ_LNCL_GAIN(DQ_AI255_GAIN_1); //UEI macro & #define

//program gain for excitation measurement

param.changain = cl[i];

// get waveform frequency and amplitude used to power the sensor

DqAdv255GetWFMeasurements(
hd, // handle for the IOM, set in DqOpenIOM()
DEVN, // AI-256 board position in the chassis
0, // Reserved, set to 0
&param, // structure of type pWFMEASURE_255
// used to store waveform parameters,
// specifically the changain parameter
// must be set to the channel list, cl
chan_m); // pointer to structure of type pWFPRM_255,
// used to store external excitation
// measurements
// chan_m.freq: the measured exc frequency
// chan_m.ampl: the measured Vpp level
}

Macro, structure and #define descriptions

For more information, refer to the PowerDNA API Reference Manual or refer to
the powerdna.h header file.

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5.4.2.2 Setting To set up internal excitation, use the DqAdv255SetExcitation API.

Internal The following is an example of setting up the DqAdv255SetExcitation API
Excitation for generating internal excitation:
for(i=0; i<CHANNELS; i++) {
// Configure channel list
// Set gain = gain of 1
cl[i] = i | DQ_LNCL_GAIN(DQ_AI255_GAIN_1); //UEI macro & #define

// For internal excitation modes, configure the

// amplitude and frequency of the sine waveform
// used to power the sensor
// convert RMS voltage to peak-to-peak voltage
exc_rates[i] = INT_EXC_RATE; // From 50 Hz to 10 kHz
exc_rms_amplitudes[i] = RMS_AMPL; // Up to 19.8 Vrms
exc_peakpeak_amplitudes[i] = exc_rms_amplitudes[i]*(2*DQ_AI254_AMP2RMS);

DqAdv255SetExcitation(
hd, // handle for the IOM, set in DqOpenIOM()
DEVN, // AI-256 board position in the chassis
DQ_LNCL_GETCHAN(cl[i]), // get channel # programmed in cl
DQ_AI255_ENABLE_EXC_D, // set which output to use for
// excitation, D must be used
// for simulation devices
exc_rates[i],
exc_peakpeak_amplitudes[i]; //peak-to-peak excitation voltage

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5.4.3 Configuring The DqAdv255SetMode() API configures a DNx-AI-256 channel as a

Synchro/ Synchro or Resolver, as an input or output, or to use internal or external
Resolver excitation, etc.
Operational Since the DqAdv255SetMode API is passed an expected excitation frequency
Modes (exc_freq) and an excitation voltage level (se_level), before calling
DqAdv255SetMode(), call an API to get or set excitation waveform
parameters. See Section 5.4.2 for more information about programming
excitation.
The DqAdv255SetMode API can then be called to set the mode:

DqAdv255SetMode(hd, // handle for the IOM

DEVN, // AI-256 board position in the chassis
channel, // channel to apply mode setting to
mode, // listed below in Table 5-2
0, // Reserved, set to 0
exc_freq, // expected excitation frequency
se_level); // Excitation level (Vpp)

The AI-256 can be programmed as synchro or resolver modes with internal or

external excitation.
Synchro modes can additionally be configured as z-grounded, allowing the S3
stator to be grounded.
To set the mode of a channel, pass one of the following as the mode
parameter:

Mode Description
DQ_AI255_MODE_SI_INT Synchro input, internal excitation

DQ_AI255_MODE_RI_INT Resolver input, internal excitation

DQ_AI255_MODE_SI_EXT Synchro input, external excitation

DQ_AI255_MODE_RI_EXT Resolver input, external excitation

DQ_AI255_MODE_SS_INT Synchro simulation (output), internal excitation

DQ_AI255_MODE_RS_INT Resolver simulation (output), internal excitation

DQ_AI255_MODE_SS_EXT Synchro simulation (output), external excitation

DQ_AI255_MODE_RS_EXT Resolver simulation (output), external excitation

DQ_AI255_MODE_SI_INTZ Synchro input, internal excitation, Z-grounded

DQ_AI255_MODE_SI_EXTZ Synchro input, external excitation, Z-grounded

DQ_AI255_MODE_SS_INTZ Synchro simulation (output), internal excitation, Z-grounded

DQ_AI255_MODE_SS_EXTZ Synchro simulation (output), external excitation, Z-grounded

Table 5-2. AI-256 Modes of Operation

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Pinouts and connection diagrams

Pinouts for wiring each of the modes of operation are provided in Table 2-5 on
page 22. Refer to Appendix B for connection diagrams.

5.4.4 Enabling After the excitation and modes of operation are set up, the DNx-AI-256 channels
Synchro/ can be enabled with the DqAdv255Enable()API.
Resolver
Channels
// Enable channels,
// For example, CHANNELS is set to 2 (the maximum number of
// channels on the device)
// and cl is a configuration array of length CHANNELS, (i.e. cl[0]
// holds the gain setting for channel 0, cl[1] holds the gain setting
// for channel 1)

DqAdv255Enable( hd, //handle for the IOM

DEVN, // AI-256 board position in the chassis
0, // Reserved, set to 0
1, // 1 = TRUE (enabled)
CHANNELS, // CHANNELS = max # of channels / board
cl); // channel list, encoded with gain settings

5.4.5 Reading After the channels are enabled, you can measure the stator voltages on AI-256
Synchro or channels configured as inputs (not simulated outputs).
Resolver The DqAdv255Read API is used to acquire stator readings in Immediate
Inputs (point-to-point) data acquisition mode.
(Immediate
Mode)

DqAdv255Read( hd, // handle for the IOM

DEVN, // AI-256 board position in the chassis
CHANNELS, // CHANNELS = max # of channels / board
cl, // channel list
NULL, //
angles); // converted data

By default, DqAdv255Read returns the calculated rotor angle (angles).

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5.4.6 Writing After the channels are enabled, you can output simulated stator voltages on
Synchro or AI-256 channels configured as simulated outputs.
Resolver The DqAdv255Write API can be used in Immediate data acquisition mode to
Simulated convert an angle parameter to stator output waveforms and output those
Outputs waveforms.

double angles = angleInDegrees * _pi_/180.0;

DqAdv255Write( hd, // handle for the IOM

DEVN, // AI-256 board position in the chassis
CHANNELS, // CHANNELS = max # of channels / board
cl, // channel list
exc_peakpeak_amplitudes,
// maximum voltage (Vpp) of the simulated
// stator voltage
angles); // output position in radians

Note that if you review stator waveforms on a scope, you are looking at line-to-
ground waveforms. For more information about interpreting simulated outputs
and to review simulated position calculations and formulas, refer to the
DqAdv255Write API description in the PowerDNA API Reference Manual.

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5.5 Programming This section describes the use of the AI-256 in LVDT/RVDT applications.
AI-256 for For applications that use synchros or resolvers, refer to “Programming AI-256
LVDT / RVDT for Synchro/Resolver Devices” on page 46.
Devices

5.5.1 LVDT/RVDT The LVDT/RVDT low-level functions for an AI-256 I/O board are listed in this
Functions section.
The following AI-256 functions perform are used for LVDT/RVDT applications:

Function Description

DqAdv256SetModeLvdt Sets LVDT/RVDT operating modes:4/5/6-wire simulated output

mode or 5/6-wire LVDT/RVDT input mode, internal or external
excitation.

DqAdv256Enable Enable/disable operations for channels specified in channel list.

DqAdv256ConvertSimLvdt Converts a ±1.0 position into raw data representation for gain/
phase.

DqAdv256GetWFMeasurements Returns the measured parameters of waveform on the input line(s).

DqAdv256ReadLvdt Returns the LVDT/RVDT readings from AI-256 input channel.

DqAdv256SetAll Sets up AI-256 configuration parameters to non-default variables.

DqAdv256WriteLvdt Writes simulated position to simulate 4- and 5/6-wire LVDT/RVDTs.

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5.5.2 Configuring The DqAdv256SetModeLvdt() API configures a DNx-AI-256 channel as a

LVDT/RVDT LVDT/RVDT, as a 5/6-wire input or 4/5/6-wire output, or to use internal or
Operational external excitation, etc. Note that excitation is also programmed in the
DqAdv256SetModeLvdt() API.
Modes

DqAdv256SetModeLvdt(hd, // handle for the IOM

DEVN, // AI-256 board position in the chassis
channel, // channel to apply mode setting to
mode, // listed below
0, // Reserved, set to 0
meas_pts, // API returns the number of points per period in
// sine wave
usr_offset, // set to 0.0
usr_gain, // set to 1.0
exc_freq, // expected excitation frequency
se_level); // excitation level (Vpp)

To set the mode of a channel, pass one of the following as the mode
parameter.:
Table 5-3 AI-256 LVDT/RVDT Modes of Operation

Analog Input or Sensor Wire Internal or

Mode Simulated Output Configuration External Excitation
DQ_AI254_MODE_INT_5 Analog Input Mode 5- or 6-wire Internal Excitation

DQ_AI254_MODE_EXT_5 Analog Input Mode 5- or 6-wire External Excitation

DQ_AI256_MODE_SIM_5_EXT Simulated Output 5- or 6-wire External Excitation

DQ_AI256_MODE_SIM_4_EXT Simulated Output 4-wire External Excitation

DQ_AI256_MODE_SIM_5_INT Simulated Output 5- or 6-wire Internal Excitation

DQ_AI256_MODE_SIM_4_INT Simulated Output 4-wire Internal Excitation

For more information, refer to the PowerDNA API Reference Manual or refer to
the powerdna.h header file.

Pinouts and connection diagrams

Pinouts and connection diagrams for wiring each of the modes of operation are
provided in Chapter 3.

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5.6 Programming The DqAdv256ReadPADC() API is used to retrieve power information from the
Power AI-256 power monitoring analog-to-digital converter.
Monitor on
AI‒256
DqAdv256ReadPADC(hd, // handle for the IOM
DEVN, // AI-256 board position in the chassis
bdata, // array of uint32 raw binary data (8 values)
fdata); // array of converted double data (8 values)

where the 8 values returned are:

Table 5-4. Return Values for Power Monitor

Array Position Define variable Description

0 DQ_AI256_SUBCH_NEGV_0 Channel 0, negative voltage

1 DQ_AI256_SUBCH_POSV_0 Channel 0, +VCC

2 DQ_AI256_SUBCH_I_DC_0 Channel 0, DC current on common

3 DQ_AI256_SUBCH_THERM_0 Channel 0, temperature of the ADC IC

in degrees C

4 DQ_AI256_SUBCH_NEGV_1 Channel 1, negative voltage

5 DQ_AI256_SUBCH_POSV_1 Channel 1, +VCC

6 DQ_AI256_SUBCH_I_DC_1 Channel 1, DC current on common

7 DQ_AI256_SUBCH_THERM_1 Channel 1, temperature of the ADC IC

in degrees C

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 DNx-AI-256 Synchro/Resolver/LVDT/RVDT Interface
Appendix A 55

Appendix A

A.1 Accessories The following cables and STP boards are available for the AI-256 board.

DNA-CBL-62
This is a 62-conductor round shielded cable with 62-pin male D-sub connectors
on both ends. It is made with round, heavy-shielded cable; 2.5 ft (75 cm) long,
weight of 9.49 ounces or 269 grams; up to 10ft (305cm) and 20ft (610cm).

DNA-STP-62
The STP-62 is a Screw Terminal Panel with three 20-position terminal blocks
(JT1, JT2, and JT3) plus one 3-position terminal block (J2). The dimensions of
the STP-62 board are 4w x 3.8d x1.2h inch or 10.2 x 9.7 x 3 cm (with standoffs).
The weight of the STP-62 board is 3.89 ounces or 110 grams.

DB-62 (female) JT3 — 20-position JT2 — 20-position JT1 — 20-position J2 — 5-position

62-pin connector: terminal block: terminal block: terminal block: terminal block:
62 UP
+ 42 UP
+ 21 UP
+
61 UP
+5 41 UP
+5 20 UP
+5    5 4)*&-%
60 UP
+5 40 UP
+5 19 UP
+5    4 (/%
59 UP
+5 39 UP
+5 18 UP
+5    3 
58 UP
+5 38 UP
+5 17 UP
+5    2 
57 UP
+5 37 UP
+5 16 UP
+5    1 
56 UP
+5 36 UP
+5 15 UP
+5 44  
55 UP
+5 35 UP
+5 14 UP
+5   
54 UP
+5 34 UP
+5 13 UP
+5   
53 UP
+5 33 UP
+5 12 UP
+5   
52 UP
+5 32 UP
+5 11 UP
+5   
51 UP
+5 31 UP
+5 10 UP
+5 4  
50 UP
+5 30 UP
+5 9 UP
+5   
49 UP
+5 29 UP
+5 8 UP
+5   
48 UP
+5 28 UP
+5 7 UP
+5   
47 UP
+5 27 UP
+5 6 UP
+5 47  
46 UP
+5 26 UP
+5 5 UP
+5   
45 UP
+5 25 UP
+5 4 UP
+5   
44 UP
+5 24 UP
+5 3 UP
+5   
43 UP
+5 23 UP
+5 2 UP
+5   
22 UP
+5 1 UP
+5 GND 7 

SHIELD

to J2 to JT1 to JT2 to JT3

Figure A-1 Pinout and photo of DNA-STP-62 screw terminal panel

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 DNx-AI-256 Synchro/Resolver/LVDT/RVDT Interface
Appendix B 56

Appendix B
Connection Diagrams for Synchro / Resolver
Operating and Excitation Modes
This appendix provides connection diagrams for the following AI-256 modes:
• Synchro Input Mode with Internal Excitation (Section A.1)
• Synchro Input Mode with External Excitation (Section A.2)
• Synchro Simulator Output Mode with Internal Excitation (Section A.3)
• Synchro Simulator Output Mode with External Excitation (Section A.4)
• Synchro Simulator Output Mode with External Excitation & Z-grounding
(Section A.5)
• Resolver Input Mode with Internal Excitation (Section A.6)
• Resolver Input Mode with External Excitation (Section A.7)
• Resolver Simulator Output Mode with Internal Excitation (Section A.8)
• Resolver Simulator Output Mode with External Excitation (Section A.9)

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 DNx-AI-256 Synchro/Resolver/LVDT/RVDT Interface
Appendix B 57

A.1 Synchro Input Set up AI-256 connections as shown in Figure B-1 (star synchro) or Figure B-2
Mode with (delta synchro) when a channel is configured for the following:
Internal • Each stator line of the synchro is input to AI-256
Excitation
• AI-256 generates excitation internally
DNx-AI-256
Pin No.
Ch0 Ch1
4 14 InA+ S1
25 35 InA– C
5 15 InB+ S3 indicates
Inputs 26 36 InB– C optional conn.
InC+ S2 If center point is
9 62 not wired, leave
30 61 InC– C InA-, InB-, InC-
10 20 InD+ NC unconnected.
TBD
31 41 InD– NC
Rotor

44 54 OutA+ NC
43 53 OutA– NC
2 12 OutB+ NC
Outputs
23 33 OutB– NC
7 17 OutC+ NC
28 38 OutC– NC
8 18 OutD+ R1
29 39 OutD– R2
Star Synchro in
Ch0 Ch1
Input Mode,
24,47 32,42 NC Internal Excitation
57,59
Other 6, 22 16,34
Pins GND
45,51 40,55
1, 3 11,13 Rsvd
27,46 19,21
48,49 37,56
50,52 58,60

Figure B-1 Star Synchro: Input Mode, Internal Excitation

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 DNx-AI-256 Synchro/Resolver/LVDT/RVDT Interface
Appendix B 58

DNx-AI-256
Pin No.
Ch0 Ch1
4 14 InA+ S1
25 35 InA– S3
5 15 InB+ S2
Inputs 26 36 InB– S1
9 62 InC+ S3
30 61 InC– S2
10 20 InD+ NC
TBD Rotor
31 41 InD– NC

44 54 OutA+ NC
43 53 OutA– NC
2 12 OutB+ NC
Outputs
23 33 OutB– NC
7 17 OutC+ NC
28 38 OutC– NC
8 18 OutD+ R1
29 39 OutD– R2
Delta Synchro in
Ch0 Ch1
Input Mode,
24,47 32,42 NC Internal Excitation
57,59
Other 6, 22 16,34
Pins GND
45,51 40,55
1, 3 11,13 Rsvd
27,46 19,21
48,49 37,56
50,52 58,60

Figure B-2 Delta Synchro: Input Mode, Internal Excitation

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 DNx-AI-256 Synchro/Resolver/LVDT/RVDT Interface
Appendix B 59

A.2 Synchro Input Set up AI-256 connections as shown in Figure B-3 (star synchro) or Figure B-4
Mode with (delta synchro) when a channel is configured for the following:
External • Each stator line of the synchro is input to AI-256
Excitation
• AI-256 uses an externally generated excitation

DNx-AI-256
Pin No.
Ch0 Ch1
4 14 InA+ S1
25 35 InA– C
5 15 InB+ S3
Inputs 26 36 InB– C
9 62 InC+ S2
30 61 InC– C
10 20 InD+ Exc+ TBD
31 41 InD– Exc-
Rotor

Excitation
OutA+ Source NC Star Synchro in
44 54
Input Mode,
43 53 OutA– NC
External Excitation
2 12 OutB+ NC
Outputs
23 33 OutB– NC
7 17 OutC+ NC
28 38 OutC– NC
8 18 OutD+ NC
29 39 OutD– NC

Ch0 Ch1
24,47 32,42 NC
57,59 indicates
Other 6,22 16,34 optional connection.
Pins GND
45,51 40,55 If center point is
not wired, leave
1, 3 11,13 Rsvd InA-, InB-, InC-
27,46 19,21 unconnected.
48,49 37,56
50,52 58,60

Figure B-3 Star Synchro: Input Mode, External Excitation

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 DNx-AI-256 Synchro/Resolver/LVDT/RVDT Interface
Appendix B 60

DNx-AI-256
Pin No.
Ch0 Ch1
4 14 InA+ S1
25 35 InA– S3
5 15 InB+ S2
Inputs 26 36 InB– S1
9 62 InC+ S3
30 61 InC– S2
10 20 InD+ Exc+ TBD Rotor
31 41 InD– Exc-

Excitation
Source
44 54 OutA+ NC
43 53 OutA– NC
2 12 OutB+ NC
Outputs
23 33 OutB– NC
7 17 OutC+ NC
28 38 OutC– NC
8 18 OutD+ R1
29 39 OutD– R2
Delta Synchro in
Ch0 Ch1 Input Mode,
24,47 32,42 NC External Excitation
57,59
Other 6, 22 16,34
Pins GND
45,51 40,55
1, 3 11,13 Rsvd
27,46 19,21
48,49 37,56
50,52 58,60

Figure B-4 Delta Synchro: Input Mode, External Excitation

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 DNx-AI-256 Synchro/Resolver/LVDT/RVDT Interface
Appendix B 61

A.3 Synchro Set up AI-256 connections as shown in Figure B-5 (star synchro) or Figure B-6
Simulator (delta synchro) when a channel is configured for the following:
Output Mode • AI-256 simulates a synchro and internally generates stator line wave-
with Internal forms
Excitation
• AI-256 generates excitation internally
DNx-AI-256

Pin No.
Ch0 Ch1
4 14 InA+ NC
25 35 InA– NC
5 15 InB+ NC
Inputs 26 36 InB– NC Star Synchro in
9 62 InC+ NC Simulator Mode,
30 61 InC– NC Internal Excitation
10 20 InD+ NC
31 41 InD– NC

44 54 OutA+ S1
43 53 OutA– C
2 12 OutB+ S3
Outputs
23 33 OutB– C
7 17 OutC+ S2 TBD
28 38 OutC– C
8 18 OutD+ R1 Rotor
29 39 OutD– R2

Ch0 Ch1
24,47 32,42 NC
57,59
Other 6,22 16,34
Pins GND
45,51 40,55
1, 3 11,13 Rsvd indicates
27,46 19,21 optional connection.
48,49 37,56 If center point is
50,52 58,60 not wired, leave
OutA-, OutB-, OutC-
unconnected.
NOTE: Most synchros do not require connections to OutA-, OutB-, and OutC-. Some devices,
however, use electronic equivalents of synchros. In such cases, connect the channel ground to
the device ground.

Figure B-5 Star Synchro: Simulator Mode, Internal Excitation

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 DNx-AI-256 Synchro/Resolver/LVDT/RVDT Interface
Appendix B 62

DNx-AI-256
Pin No.
Ch0 Ch1
4 14 InA+ NC
25 35 InA– NC
5 15 InB+ NC Delta Synchro in
Inputs InB– Simulator Mode,
26 36 NC Internal Excitation
9 62 InC+ NC
30 61 InC– NC
10 20 InD+ NC TBD
31 41 InD– NC

44 54 OutA+ S1
43 53 OutA– S3
2 12 OutB+ S2
Outputs
23 33 OutB– S1
7 17 OutC+ S3
28 38 OutC– S2
8 18 OutD+ R1
29 39 OutD– R2
Rotor
Ch0 Ch1
24,47 32,42 NC
57,59
Other 6, 22 16,34
Pins GND
45,51 40,55
1, 3 11,13 Rsvd
27,46 19,21
48,49 37,56
50,52 58,60

Figure B-6 Delta Synchro: Simulator Mode, Internal Excitation

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 DNx-AI-256 Synchro/Resolver/LVDT/RVDT Interface
Appendix B 63

A.4 Synchro Set up AI-256 connections as shown in Figure B-7 (star synchro) or Figure B-8
Simulator (delta synchro) when a channel is configured for the following:
Output Mode • AI-256 simulates a synchro and internally generates stator line wave-
with External forms
Excitation
• AI-256 uses an externally generated excitation source

DNx-AI-256

Pin No.
Ch0 Ch1
4 14 InA+ NC
25 35 InA– NC Star Synchro in
5 15 InB+ NC Simulator Mode,
External Excitation
Inputs 26 36 InB– NC
Excitation
9 62 InC+ Source NC
30 61 InC– NC Rotor
10 20 InD+ Exc+
31 41 InD– Exc-

44 54 OutA+ S1
43 53 OutA– C
2 12 OutB+ S3
Outputs
23 33 OutB– C
7 17 OutC+ S2
28 38 OutC– C
8 18 OutD+ NC TBD
29 39 OutD– NC

Ch0 Ch1
24,47 32,42 NC
57,59 indicates
Other 6,22 16,34 optional connection.
Pins GND
45,51 40,55 If center point is
not wired, leave
1, 3 11,13 Rsvd OutA-, OutB-, OutC-
27,46 19,21 unconnected.
48,49 37,56
50,52 58,60

Figure B-7 Star Synchro: Simulator Mode, External Excitation

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 DNx-AI-256 Synchro/Resolver/LVDT/RVDT Interface
Appendix B 64

DNx-AI-256
Pin No.
Ch0 Ch1
4 14 InA+ NC
25 35 InA– NC
5 15 InB+ NC Delta Synchro in
Inputs InB– Simulator Mode,
26 36 NC External Excitation
Excitation
9 62 InC+ NC
Source
30 61 InC– NC Rotor
10 20 InD+ Exc+ TBD
31 41 InD– Exc-

44 54 OutA+ S1
43 53 OutA– S3
2 12 OutB+ S2
Outputs
23 33 OutB– S1
7 17 OutC+ S3
28 38 OutC– S2
8 18 OutD+ NC
29 39 OutD– NC
Ch0 Ch1
24,47 32,42 NC
57,59
Other 6, 22 16,34
Pins GND
45,51 40,55
1, 3 11,13 Rsvd
27,46 19,21
48,49 37,56
50,52 58,60

Figure B-8 Delta Synchro: Simulator Mode, External Excitation

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 DNx-AI-256 Synchro/Resolver/LVDT/RVDT Interface
Appendix B 65

A.5 Synchro Set up AI-256 connections as shown in Figure B-9 (star synchro) when a
Simulator channel is configured for the following:
Output Mode • AI-256 simulates a synchro and internally generates stator line wave-
with External forms**
Excitation &
• **AI-256 is configured for z-grounding mode and produces waveforms
Z-grounding
on S1 and S2 accordingly: OutC is open and S3 on mating device is
grounded
• AI-256 uses an externally generated excitation source
DNx-AI-256

Pin No.
Ch0 Ch1
4 14 InA+ NC
25 35 InA– NC
Star Synchro in
5 15 InB+ NC Simulator Mode,
Inputs 26 36 InB– NC External Excitation,
Excitation NC Z-grounding
9 62 InC+
Source
30 61 InC– NC
Rotor
10 20 InD+ Exc+
31 41 InD– Exc-

OutA+ S1 X
44 54
43 53 OutA– C
OutB+ S3 Z
2 12
Outputs
23 33 OutB– C
7 17 OutC+ S2
Y
28 38 OutC– C
8 18 OutD+ NC TBD
29 39 OutD– NC

Ch0 Ch1
24,47 32,42 NC
57,59
Other 6,22 16,34
Pins GND
45,51 40,55
1, 3 11,13 Rsvd
27,46 19,21
48,49 37,56
50,52 58,60

Figure B-9 Star Synchro: Simulator Mode, External Excitation, Z-grounding

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 DNx-AI-256 Synchro/Resolver/LVDT/RVDT Interface
Appendix B 66

A.6 Resolver Input Set up AI-256 connections as shown in Figure B-10 when a channel is
Mode with configured for the following:
Internal • Each stator line of the resolver is input to AI-256
Excitation
• AI-256 generates excitation internally

DNx-AI-256

Pin No.
Ch0 Ch1
4 14 InA+ S1
25 35 InA– S3
5 15 InB+ S2
Inputs 26 36 InB– S4
9 62 InC+ NC
30 61 InC– NC
10 20 InD+ NC TBD
31 41 InD– NC Rotor 1

44 54 OutA+ R1
43 53 OutA– R3
Outputs 2 12 OutB+ R2
Rotor 2
23 33 OutB– R4
7 17 OutC+ NC
28 38 OutC– NC Resolver in
NC Input Mode,
8 18 OutD+ Internal Excitation
29 39 OutD– NC

Ch0 Ch1
24,47 32,42 NC NOTE:
57,59 Connect rotor to Output D. If more
Other 6, 22 16,34 GND current is needed, use Output B in
Pins 45, 51 40,55 parallel and add a 2-10 ohm series
resistor.
1, 3 11,13 Rsvd Resolvers that use the second rotor
27,46 19,21 coil can be connected to Output C.
48,49 37,56
50,52 58,60

Figure B-10 Resolver: Input Mode, Internal Excitation

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 DNx-AI-256 Synchro/Resolver/LVDT/RVDT Interface
Appendix B 67

A.7 Resolver Input Set up AI-256 connections as shown in Figure B-11 when a channel is
Mode with configured for the following:
External • Each stator line of the resolver is input to AI-256
Excitation
• AI-256 uses an externally generated excitation source

DNx-AI-256

Pin No.
Ch0 Ch1
4 14 InA+ S1
25 35 InA– S3
5 15 InB+ S2
Inputs 26 36 InB– S4
9 62 InC+ NC
30 61 InC– NC
10 20 InD+ Exc+ TBD
31 41 InD– Exc- Rotor

Excitation
Source
44 54 OutA+ NC
43 53 OutA– NC
2 12 OutB+ NC Resolver in
Outputs
23 33 OutB– NC Input Mode,
NC External Excitation
7 17 OutC+
28 38 OutC– NC
8 18 OutD+ NC
29 39 OutD– NC

Ch0 Ch1
24,47 32,42 NC
57,59
Other 6, 22 16,34
Pins GND
45, 51 40,55
1, 3 11,13 Rsvd
27,46 19,21
48,49 37,56
50,52 58,60

Figure B-11 Resolver: Input Mode, External Excitation

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 DNx-AI-256 Synchro/Resolver/LVDT/RVDT Interface
Appendix B 68

A.8 Resolver Set up AI-256 connections as shown in Figure B-12 when a channel is
Simulator configured for the following:
Output Mode • AI-256 simulates a resolver and internally generates stator line wave-
with Internal forms
Excitation
• AI-256 generates excitation internally

DNx-AI-256

Pin No.
Ch0 Ch1
4 14 InA+ NC
25 35 InA– NC
5 15 InB+ NC
Inputs 26 36 InB– NC Resolver in
9 62 InC+ NC Simulator Mode,
InC– Internal Excitation
30 61 NC
10 20 InD+ TBD
NC
31 41 InD– NC

44 54 OutA+ S1
43 53 OutA– S3
2 12 OutB+ S2
Outputs
23 33 OutB– S4
7 17 OutC+ Opt+(R2)
28 38 OutC– Opt-(R4)
8 18 OutD+ Exc+(R1)
29 39 OutD– Exc-(R3) Rotor

Ch0 Ch1
24,47 32,42 NC
57,59
Other 6, 22 16,34
Pins GND
45, 51 40,55
1, 3 11,13 Rsvd
27,46 19,21
48,49 37,56
50,52 58,60

Figure B-12 Resolver: Simulator Mode, Internal Excitation

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 DNx-AI-256 Synchro/Resolver/LVDT/RVDT Interface
Appendix B 69

A.9 Resolver Set up AI-256 connections as shown in Figure B-13 when a channel is
Simulator configured for the following:
Output Mode • AI-256 simulates a resolver and internally generates stator line wave-
with External forms
Excitation
• AI-256 uses an externally generated excitation source

DNx-AI-256

Pin No.
Ch0 Ch1
4 14 InA+ NC
25 35 InA– NC
Resolver in
5 15 InB+ NC Simulator Mode,
Inputs 26 36 InB– NC External Excitation
9 62 InC+ NC
30 61 InC– NC
10 20 InD+ Exc+ TBD
31 41 InD– Exc- Rotor

Excitation
Source
44 54 OutA+ S1
43 53 OutA– S3
2 12 OutB+ S2
Outputs
23 33 OutB– S4
7 17 OutC+ NC
28 38 OutC– NC
8 18 OutD+ NC
29 39 OutD– NC

Ch0 Ch1
24,47 32,42 NC
57,59
Other 6, 22 16,34
Pins GND
45, 51 40,55
1, 3 11,13 Rsvd
27,46 19,21
48,49 37,56
50,52 58,60

Figure B-13 Resolver: Simulator Mode, External Excitation

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