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IC2-Lecture5

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4 views

IC2-Lecture5

Uploaded by

Roshdy - رشدي
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Integrated Circuit 2

ECE 430

Lecture 5: CMOS Logic Gates (1)

Dr. Emad Badry


(a) combinational (b) sequential
Combinational Logic Circuits

CMOS NOR2 (Two-Input NOR) Gate


The circuit consists of a parallel-connected N-net and a series-connected
complementary P-net. The input voltages VA and VB are applied to the
gates of one NMOS and one PMOS transistor. The network of NMOS is
called Pull Down Network (PDN) while the network of PMOS transistors
denoted as Pull Up Network (PUN).

VA VB Vout
0 0 1
1 0 0
0 1 0
1 1 0
1 𝐾𝑃 Inverter
𝑉𝑡𝑛 + (𝑉 − 𝑉𝑡𝑝 )
2 𝐾𝑁 𝐷𝐷
𝑉𝑡ℎ 𝑁𝑂𝑅2 =
1 𝐾𝑃 𝐾
1+ 𝑉𝑡𝑛 + 𝐾𝑃 (𝑉𝐷𝐷 − 𝑉𝑡𝑝 )
2 𝐾𝑁 𝑁
𝑉𝑡ℎ 𝐼𝑁𝑉 =
𝐾
1 + 𝐾𝑃
𝑁
If KN=KP, Vtn=|Vtp|

𝑉𝐷𝐷 + 𝑉𝑡𝑛
𝑉𝑡ℎ (𝑁𝑂𝑅2) =
3
Which is not equal to 𝑉𝐷𝐷 Τ2 as the inverter
The Vth of two-input NOR gate can be defined as
𝐾
𝑉𝑡𝑛 + 4𝐾𝑃 (𝑉𝐷𝐷 − |𝑉𝑡𝑝 |)
𝑁
𝑉𝑡ℎ (𝑁𝑂𝑅2) =
𝐾
1 + 4𝐾𝑃
𝑁

❑ The parallel-connected NMOS transistors can be


represented by a single MMOS transistor with 2Kn.
Similarly, the series-connected PMOS transistors are
represented by a single PMOS transistor with KP/2.

❑ To achieve a switching threshold voltage of 𝑉𝐷𝐷 Τ2 for


simultaneous switching, we have to set Vtn=|Vtp| and
KP=4KN.
CMOS NAND2 (Two-Input NAND) Gate

In the case of two-input NAND gate, the PDN network consists of two cascaded NMOS transistors while the PUN
network composed of two parallel PMOS transistors. The threshold Vth value can be defined as

𝐾
𝑉𝑡𝑛 + 2 𝐾𝑃 (𝑉𝐷𝐷 − |𝑉𝑡𝑝 |)
𝑁
𝑉𝑡ℎ (𝑁𝐴𝑁𝐷2) =
𝐾
1 + 2 𝐾𝑃
𝑁

❑ In order to achieve a switching threshold voltage of


𝑉𝐷𝐷 Τ2 for simultaneous switching, we have to set
Vtn=|Vtp| and KN=4KP.
CMOS Complex Logic Gates

A set of construction rules can be derived to construct logic functions:


▪ NMOS devices connected in series corresponds to an AND function.
▪ NMOS transistors connected in parallel represent an OR function.
▪ A series connection of PMOS conducts if both inputs are low, representing a NOR function.
▪ PMOS transistors are stacked in parallel implement a NAND.
Examples of CMOS logic gates

𝑓 = 𝐴𝐵 + 𝐶𝐷 𝑓 = 𝐴𝐵 + 𝐶 𝑓 = 𝐴𝐵 + 𝐶(𝐷 + 𝐸)
Transistor sizing

❑ To estimate the sizing of CMOS circuits, the equivalent aspect ratio for any path contains n transistors (PMOS or
NMOS) can be defined as

𝑊 1
( )𝑒𝑞𝑠 =
𝐿 𝐿
σ𝑛𝑖=1( )𝑛
𝑊
𝑛
𝑊 𝑊
( )𝑒𝑞𝑝 = ෍( )𝑛
𝐿 𝐿
𝑖=1

𝑊 𝑊
where ( 𝐿 )𝑒𝑞𝑠 is equivalent aspect ratio of serially stacked transistors, ( 𝐿 )𝑒𝑞𝑝 is the equivalent aspect ratio of
parallel transistors
Example 4.1
𝑊 𝑊
Estimate the equivalent size of an CMOS circuit characterize the Boolean function of 𝑓 = 𝐴. 𝐵. 𝐶 + (𝐷. 𝐸). ( 𝐿 )𝑛 =12 and ( 𝐿 )𝑝 =20.

For PUN
𝑊 𝑊 𝑊 𝑊
( )𝑝𝐴𝐵𝐶 = + + = 3𝑥20 = 60
𝐿 𝐿 𝐴
𝐿 𝐵
𝐿 𝐶

𝑊 𝑊 𝑊
( )𝑝𝐷𝐸 = + = 2𝑥20 = 40
𝐿 𝐿 𝐷
𝐿 𝐸

𝑊 1 1
( )𝑝 = = = 24
𝐿 𝐿 𝐿 1 1
( )𝑝𝐴𝐵𝐶 + ( )𝑝𝐷𝐸 +
𝑊 𝑊 60 40
For PDN
𝑊 1
( )𝑛𝐴𝐵𝐶 = =4
𝐿 𝐿 𝐿 𝐿
+ 𝑊 + 𝑊
𝑊 𝐴 𝐵 𝐶

𝑊 1
( )𝑛𝐷𝐸 = =6
𝐿 𝐿 𝐿
+ 𝑊
𝑊 𝐷 𝐸

𝑊 𝑊 𝑊
( )𝑛 = + = 10
𝐿 𝐿 𝑛𝐴𝐵𝐶
𝐿 𝑛𝐷𝐸
End of Lecture

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