Module-4 DIGITAL SYSTEM DESIGN USING VERILOG (BEC302)

MODULE-4
INTRODUCTION TO VERILOG

Introduction to VERILOG: Structure of Verilog Module, Operators, Data Types, Styles of

description
VERILOG Data Flow Description: Highlights of Data Flow description, Structure of Data
Flow Description
Why HDL?
What is Hardware description language (HDL):
HDL is a computer aided design (CAD) tool for the modern digital design and
synthesis of digital systems.
Need for HDL
 The advancement in the semiconductor technology, the power and complexity of
digital systems has increased. Due to this, such digital systems cannot be realized
using discrete integrated circuits (IC’s).
 Complex digital systems can be realized using high-density programmable chips such
as application specific integrated circuits (ASIC’s) and field programmable gate arrays
(FPGA’s). To design such systems, we require sophisticated CAD tool such as HDL.
 HDL is used by designer to describe the system in a computer language that is similar
to other software Language like C. Debugging the design is easy, since HDL package
implement simulators and test benches. The two widely used Hardware description
languages are VHDLand Verilog

A Brief History of Verilog

Evolution of Verilog
 In 1983, a company called Gateway design Automation developed a hardware-
description language for its newly introduced logic simulator verilog_XL
 Gateway was bought by cadence in 1989 & cadence made Verilog available as
publicdomain.
 In December 1995, Verilog HDL became IEEE standard 1364-1995.
 The language presently is maintained by the Open Verilog international (OVI)
organization.
 Verilog code structure is based on C software language.

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Difference between VHDL and Verilog HDL

Structure of Verilog Module

The Verilog module has a declaration and a body. In the declaration, name, input and outputs
of the modules are listed. The body shows the relationship between the input and the outputs
with help of signal assignment statements.
The syntax of the Verilog module is shown below
module name of module(port_list);

// declaration:
input , output, reg, wire, parameter,
inout;

functions, tasks;

// statements or body
Initial statement
always statement
module instantiation
continuous assignment
endmodule

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The example program is halfadder

module halfadder (a,b,sum,carry);

input a;
input b;
output sum;
output carry;
assign sum=a ^b; // statement 1
assign carry=a &b; // statement2
end module
 Verilog is case sensitive. Halfadder and halfadder are two different modules in
verilog. The declaration starts with predefined word module.
 The name of the module should start with alphabetical letter and can include special
character underscore (_). It is user selected.
 Semicolon (;) is a line separator. The order in which the inputs, &outputs and their
declarations are written is irrelevant.
 “=” is assignment operator, and symbols ^ and & are used for: “xor” and “and”
respectively.
 The doubles slashes (//) signal a comment command or /*… ................. */ the pair is
used to write a comment of any length.
 The program ends with predefined word endmodule

Verilog ports
input: the port is only an input port. In any assignment statement, the port should appear only
on the right hand side of the assignment statement.(i.e., port is read.)
output: the port is an output port. The Verilog output port can appear on either side of the
assignment statement.
inout: the port can be used as both an input and output. The inout port represents a
bidirectional bus.
Operators
HDL has an extensive list of operators. Operator performs a wide variety of functions.
Functions classified
1. Logical operators such as and, or, nand, nor, xor, xnor and not

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2. Relational operators: to express the relation between objects. The operators include =,
/=, <, <=, >and >=.
3. Arithmetic operators: such as +, -, * and division.
4. Shifts operators: To move the bits of an object in a certain direction such as
right or left.
Logical operators
These operator performs Logical operations, such as and, or, nand, nor, xor, xnor, and not.
The operation can be on two operands or on a single operand. The operand can be single bit
or multiple bits.
Verilog logical operators
Verilog logical operator can be classified as Bitwise, Boolean logical and reduction
logical operators.
Bitwise Logical Operators
The bitwise operators operate on the corresponding bits of two operands.

Table 1.1 logical operators.

Verilog operator
Equivalent logic Operand type Result type
(bitwise)

& Bit Bit

| Bit Bit

~(&) Bit Bit

~(|) Bit Bit

^ Bit Bit

~^ Bit Bit

~ Bit Bit

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Example: z= x & y, if x=1011 and y=1010 are 4-bit signals then z=1010 is logical and
operation of x and y.
Boolean Logical Operators
Boolean logical operators operate on the two operands. The result is Boolean true (1) or false
(0). These are shown in table 1.2
Table 1.2 Boolean operators

Operators Operation Number ofoperands

&& AND two

|| OR two
Example for z= x && y, if x=1011 and y=0001 then Z=1, 2nd case if x=1010 and
y=0101 then z=0;
Reduction logical operators:
Reduction logical operators operate on a single operand. The result is Boolean.

Table 1.3 Verilog Reduction logical operators

Operators Operation Number of operands

& Reduction AND One

| Reduction OR One
~(&) Reduction One
NAND
~(|) Reduction NOR One
^ Reduction XOR One
~(^) Reduction One
XNOR
! Negation One
Example y=&x, if x=1010 then y= (1&0&1&0) =0
Example z! =x if x=1111 then z=0.

Verilog Relational operators

These are implemented to compare the values of two objects. The result is false (0) or true
(1).Verilog has a set of Relational operator. It Returns Boolean values false (0) or true (1).
The result can also be of type unknown (X) when any of the operand include don’t care or
unknown (X) or high impedance. Table 1.4 shows the list of Verilog Relational operators

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Table 1.4 List of Verilog Relational operators

Operators Description Result type
== Equality 0,1,X
!= Inequality 0,1,X
=== Equality Inclusive 0,1
!== Inequality Inclusive 0,1
< Less than 0,1,X
<= Less than equal to 0,1,X
> Greater than 0,1,X
>= Greater than equal to 0,1,X

Example: if (A==B), if the values of A or B contains one or more don’t care or Z bits. The
value of the expression is unknown.
If A is equal to B, then result of the expression (A==B) is true (1).
If A is not equal to B, then result of the expression (A==B) is false (0).
Verilog Arithmetic operators
Arithmetic operators can perform a wide variety of operation, such as addition, subtraction,
multiplication and division.
Table 1.5 Verilog arithmetic operator
Operators Description A or B type Y type
Addition A numeric
+ Numeric
A+B B numeric
Subtraction A numeric
- Numeric
A-B B numeric
Multiplication A numeric
* Numeric
A?B B numeric
division A numeric
/ Numeric
A/B B numeric
A numeric, not real
Modulus
% B numeric, Numeric, not real
A%B
not real
Exponent A numeric
** Numeric
A**B B numeric
Concatenation A numeric, or array
{,} Same as A
{A,B} B numeric, or array

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Verilog Shift operators

A shift left represents multiplication by two, and a shift left represents division by two.
It has basic shift operators. These are unary operators i.e., operate on single operand.
Example if A=1110, is a 4 bit vectors table 1.8 shows the Verilog shift and rotate operators.
Table 1.6 the Verilog shift operators
Operand A Operand A
Operation Description
Before shift After shift

A <<1 Shift A one position left logical 1110 110X

A <<2 Shift A two position left logical 1110 10XX

A >>1 Shift A one position right logical 1110 X111

A >> 2 Shift A two position right logical 1110 XX11

Data types
The data or operands used in the language must have several types to match the need for
describing the hardware.

Verilog Data types

There are different types of Verilog data types. Namely
1. Nets
2. Registers
3. Vectors
4. Integer
5. Real
6. Parameters
7. Array
Nets:
These are declared by the predefined word “wire”. Nets values are change continuously by
the circuits that are driving them. A wire represents a physical wire in a circuit and is used to
connect gates or modules. The value of a wire can be read, but not assigned to, in a function
or block.

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Verilog supports 4 values for nets.

Value Net Definition Reg

0 Logic 0(false) Logic 0
1 Logic1(true) Logic 1
X Unknown Unknown
Z High impedance High impedance
Eg. Wire sum; // statement declares a net by name sum.
Wire s1=1’b0; // this statement declares a net by the name of s1; it is initial value 1 bit
with value 0.
Registers:
Registers store values until they are updated. They are data storage elements. Declared by the
predefined word “reg” Verilog supports 4 values for registers. As shown in above table.
Eg reg sum_total; // declares a register by the name sum_total.
Vectors:
These are multiple bits. A reg or net can be declared as a vector. Vectors are declared by
brackets [ ].
Eg. Wire [3:0] a=4’b1010;
Reg [7:0] total =8’d12;
Integer:
Integers are declared by the predefined word “integer”. Integers are general-purpose
variables. For synthesis they are used mainly loops-indices, parameters, and constants.
Eg. Integer no_bits;//The above statement declares no_bits as an integer.
Real:
Real (floating point) numbers are declared with the predefined word “real”. Examples of
real values are 2.4, 56.3 5e12.
Eg. Real weight; // the statement declares the register weight as real.

Parameters:
It represents global constants. Declared by the predefined word “parameter”
Eg. Module comp_genr (x, y, xgty, xlty, xeqy);
Parameter N=3;
input [n:0] x,y;
output xgty, xlty, xeqy;
Wire [N:0] sum, xb;

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Arrays: there is no predefined word “array”. Registers and integers can be used as arrays.
Parameter N=4;
Parameter M=3;
reg signed [M: 0] carry [0:N]
reg [M: 0] b [0: N];
integer sum [0: N];
The above statement declares an array by the name sum. It has 5 elements, and each element is
an integer type. Array carry has 5 elements, and each elements is 4bits. They are in 2’S
complement formThe array b has 5 elements, each element is 4 bits. The value of each bit
can be 0, 1, X or Z;
Styles (Types) of Description
1.Data Flow Description
Data flow describes how the system’s signals flow from the inputs to the outputs. Usually,
the description is done by writing the Boolean function of the outputs. The data-flow
statements are concurrent; their execution is controlled by events.
Example: Refer Lab Record
2. Behavioral Descriptions
A behavioral description models the system as to how the outputs be have with the inputs.
HDL behavioral description is the one where the Verilog module contains the predefined
word always or initial.
Example: Refer Lab Record & Class Notes
3. Structural Description
Structural description models the system as gates. This description is identified by the
presence of the keyword gates construct such as and, or, and not in the module.
Example: Refer Lab Record & Class Notes
4. Switch-Level Description
The switch-level description is the lowest level of description. The system is described using
switches or transistors. Some of the Verilog predefined words used in the switch level
description are nmos, pmos, cmos, tranif0, tran, and tranif1.

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module invert(y,a);
input a;
output y;
supply1 vdd;
supply0 gnd;
pmos p1(y, vdd, a);
nmos n1(y, gnd, a); /The above two statement are using the two primitives pmos and
nmos/
endmodule
5. Mixed-Type Description
Mixed-type or mixed-style descriptions are those that use more than one type or style of the
above-mentioned descriptions.
module halfadder (a,b,sum,carry);
input a,b;
output sum,carry;
reg carry;
assign sum=a^b;
always@(a,b)
begin
carry=a&b;
end
endmodule

6. Mixed-Language Description
The mixed-language description is a newly added tool to HDL description. The user now can
write a module in one language (VHDL or Verilog) and invoke or import a construct (entity
or module) written in the other language.
module halfadder (a,b,sum,carry);
input a,b;
output sum,carry;
assign sum=a^b;
assign carry=a&b;
endmodule

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity halfadder is
port(a,b: in bit;
sum,carry: out bit);
end halfadder;

architecture data of halfadder is

begin
sum<= a xor b;
carry <= a and b;
end data;
VERILOG DATA FLOW DESCRIPTION:
Highlights of Data-Flow Description
 Data-flow description simulates the system to be described by showing how the
signal flows from the system inputs to its outputs. For example, the Boolean function
of the output or the logical structure of the system shows such signal flow.
 Signal-assignment statements are concurrent. At any simulation time, all signal-
assignment statements that have an event are executed concurrently.
Structure of the data-flow description
A dataflow model specifies the functionality of the system without explicitly specifying its
structure. It specifies how the system’s signals flow from inputs to the outputs. The
description is usually done by writing the Boolean functions of the outputs. The dataflow
statements are concurrent and their execution is controlled by events.

EVENT: An event is a change in the value of a signal, such as a change from 0 to 1 or 1 to

0.Dataflow description is modeled using continuous signal assignment statements.

Example: HDL Code for Half adder using data-flow description

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module halfadder (a,b,sum,carry);

input a;
input b;
output sum;
output carry;
assign sum=a ^b; // statement 1
assign carry=a &b; // statement2
end module

Figure 1: simulation waveform of half adder

Signal Declaration and Assignments Statements

Figure 2: AND-OR circuit. a) Symbol diagram. b) Logic diagram.

Figure 1.1 shows an AND-OR circuit. Signals a, b, c, and d are the inputs, signal y is the
output, and signals s1 and s2 are intermediates. The Boolean function of the output y can be

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written as:
y = s1 + s2; where s1=ab and s2 =cd
The Boolean function of y could be written as:
Y = ab + cd
Verilog description
module andor (a,b,c,d, y );
input a,b,c,d;
output y;
wire s1, s2;
assign s1 = a & b; //statement 1.
assign s2 = c & d; //statement 2.
assign y = s1 | s2; //statement 3.
Endmodule

Figure 3: Simulation waveform for the AND-OR circuit

In Verilog, s1 and s2 are declared as signals by using the predefined word wire:
wire s1, s2;
By default, all ports in Verilog are assumed to be wires. The value of the wire is continuously
changing with changes in the device that is deriving it. For example, s1 is the output of the
AND gate in Figure 1.1, and s1 is continuously updated as a or b changes.
A signal-assignment statement is used to assign a value to a signal. The left-hand side of the
statement should be declared as a signal. The right hand side can be a signal, a variable, or a
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constant. The operator for signal assignment is the predefined word assign in Verilog.
The signal-assignment statement is executed in two phases: calculation and assignment.
Calculation: If an event occurs on the right-hand side of a statement, then this side is
calculated at the time of the event.
Assignment: after calculation, the value obtained from the calculation is assigned to the
left-hand side, taking into consideration any timing information given in the statement. For
example
assign #10 y = s1 | s2;
Constant Declaration and Assignment Statements
A constant in HDL is treated as it is in C language; its value is constant within the segment of
the program where it is visible. A constant in Verilog can be declared by its type such as time
or integer
time period; // Verilog
To assign a value to a constant, use the assignment operator = in Verilog
period = 100; // Verilog
In the above Verilog statement, there are no explicit units of time; 100 means 100 simulation
screen time units. If the simulation screen time units are defined as nanoseconds (ns), for
example, then 100 will mean 100 nanoseconds. The declaration and assignment can be
combined in one statement as:
time period = 100 //Verilog
Assigning a Delay Time to the Signal-Assignment Statement
To assign a delay time to a signal-assignment statement, the # symbol is used in Verilog. For
example, the following statement assigns a 10 ns delay time to signal S1:
assign #10 S1 = a & b // Verilog
EXAMPLE- 2x1 MULTIPLEXER WITH ACTIVE LOW ENABLE
A 2x1 multiplexer is a combinational circuit; it has two one-bit inputs, a one-bit select line,
and a one-bit output. Additional control signals may be added, such as enable. The output of
the basic multiplexer depends on the level of the select line. If the select is high (1), the
output is equal to one of the two inputs. If the select is low (0), the output is equal to the
other input. A truth table for a 2x1 multiplexer with active low enable is shown in Table 1.9.

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Table 1.7: Truth Table for a 2x1 Multiplexer

If the enable (Gbar) is high (1), the output is low (0) regardless of the input. When Gbar is
low (0), the output is A if SEL is low (0), or the output is B if SEL is high (1). From Table
1.9, the Boolean function of the output Y is:
Y = (S1 and A and ̅̅̅̅̅ ) or (S1 and B and SEL);S1 is the invert of Gbar
Figure 1.3a shows the logic symbol, and Figure 1.3b shows the gatelevel structure of the
multiplexer

Figure 4: 2x1 Multiplexer. a) Logic symbol. b) Logic diagram

Verilog Description
module mux2x1 (A, B, SEL, Gbar, Y);
input A, B, SEL, Gbar;
output Y;
wire S1, S2, S3, S4, S5;
time dly = 7;

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assign # dly Y = S4 | S5; //st1

assign #dly S4 = A & S2 & S1; //st2
assign #dly S5 = B & S3 & S1; //st3
assign #dly S2 = ~ SEL; //st4
assign #dly S3 = ~ S2; //st5
assign #dly S1 = ~ Gbar; //st6
endmodule
or
module mux2x1 (A, B, SEL, Gbar, Y);
input A, B, SEL, Gbar;
output Y;
wire S1, S2, S3, S4, S5;
time dly = 7;
assign # dly Y = assign # dly Y = ~ (Gbar) & ((SEL & B ) | (~ SEL & A));
endmodule

Figure 5: Simulation waveform for a 2x1 multiplexer.

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Previous VTU Questions

1. Define HDL and types of HDL. Give structure of Verilog module with example
2. Explain Verilog logical operators with example
3. Write a note on arithmetic, relational and rotate operators with example
4. List all the data types available in Verilog HDL and explain any three data types with
examples
5. Explain various descriptive styles available for hardware modeling using Verilog HDL
with an example or Give classification of styles types) of description with example.
6. Write a Verilog code for 2x1 multiplexer with active low enable using dataflow
description
7. Write a Verilog code for the following
i) Full adder/ full subtractor.
ii) Half adder/ half subtractor
iii) 4:1 Mux & 8:1 Mux
iv) 2:4 & 3:8 Decoder
v) 4:2 & 8:3 Encoder & priority encoder
8. Write a note on Verilog Data Types.
9. Write a short note on
i) Signal Declaration and Assignments Statements
ii) Constant Declaration and Assignment Statements
iii) Assigning a Delay Time to the Signal-Assignment Statement

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