UNIT – 2

Logic Gates: Boolean Algebra, Map simplification,

Combinational circuits: Half Adder, Full Adder, Decoders, Multiplexers,
Sequential Circuits: Flip Flops, SR, JK, D, T flip flop.
Logic Gates :
 The logic gates are the main structural part of a digital system.
 Logic Gates are a block of hardware that produces signals of binary 1 or 0 when input logic
requirements are satisfied.
 Each gate has a distinct graphic symbol, and its operation can be described by means of algebraic
expressions.
 The seven basic logic gates includes: AND, OR, XOR, NOT, NAND, NOR, and XNOR.
 The relationship between the input-output binary variables for each gate can be represented in
tabular form by a truth table.
 Each gate has one or two binary input variables designated by A and B and one binary output
variable designated by x.
Basic Logic Gates :

1. AND gate
2. OR gate
3. NOT/ inverter gate

AND gate :

The AND gate is an electronic circuit which gives a high output only if all its inputs are high. In the AND gate, the
output of an AND gate attains state 1 if and only if all the inputs are in state 1. Otherwise, the output is
logic 0. The AND operation is represented by a dot (.) sign. The output is logical multiplication of the inputs.

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 Fig: Three input AND gate

OR gate:

The OR gate is an electronic circuit which gives a high output if one or more of its inputs are high. When
both the inputs are 0, output is 0. The operation performed by an OR gate is represented by a plus (+)
sign. The output is logical addition of the inputs.

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 Fig: Three input OR gate

NOT gate:

The NOT gate is an electronic circuit which produces an inverted version of the input at its output. It is
also known as an Inverter. For example, if the boolean variable 'A' is in state 1, then NOT A will be in
state 0.

Universal gates:

The gates by which we can perform all the binary operations like Addition, subtraction,
multiplication, and division. All the basic logic gates can be derived from them. This means that
we can create any logical Boolean expression using only universal gates i.e. NAND or NOR
gates.Universal gates are commutative but not associative in nature. Types of universal gates are:
NAND gate or NOR gate

NAND gate:

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The NOT-AND (NAND) gate which is equal to an AND gate followed by a NOT gate. The NAND gate
gives a high output if any of the inputs are low. The NAND gate is represented by a AND gate with a
small circle on the output. The small circle represents inversion.

Fig: Three input NAND gate

Application of NAND Gate:

 NAND gates can be used in alarm circuits.

 They re also used in buzzer and burglar devices
 NAND logic gates also have application in automatic temperature regulation circuits
 NAND gates can be used to detect if system has gone low. For e.g. Consider a security system build using
NAND gates can monitor signals provided by sensors on doors and windows. If a single window or door is
opened, the security system can output signal “1” and this can be used to trigger an alarm or take some
other action.

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 Implication of all gates with NAND gate

NOR gate:

The NOT-OR (NOR) gate which is equal to a OR gate followed by a NOT gate. The NOR gate gives a
low output if any of the inputs are high i.e. it gives output as 1 only if all the inputs are in 0 state. The
NOR gate is represented by an OR gate with a small circle on the output. The small circle represents
inversion. NOR gate is basically opposite of OR gate.

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 Fig: Three inputs NOR gate

Implication of all gates with NOR gate

Applications of NOR Gate

 NOR Gate can be used in combinational circuits such as multipliers, multiplexers, half and full
adders, and in ripple-carry adders.
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  There are also used in sequential circuits and in shift registers. The sequential circuit is a circuit
that has memory unlike combinational circuits and output can vary based on input. They have
previous input, output, clock and a memory element.

Combinational gates:

There are two types of combinational gates: XOR and XNOR gates

XOR gate:

The 'Exclusive-OR' gate is a circuit which will give a high output if one of its inputs is high but not both
of them. Thus, the output is 1 when, both the inputs are of different types. The XOR operation is
represented by an encircled plus sign. An odd number of 1's generate a 1 output and even number of 1's
give zero output.

Fig: Three input XOR gate

XNOR gate:

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The 'Exclusive-NOR' gate is a circuit that does the inverse operation to the XOR gate. It will give a low
output if one of its inputs is high but not both of them. Thus, it produces high output when both the input
are at the same logic. The small circle represents inversion.

Fig: Three input XNOR gate

Uses of Logic Gates

1. Logic gates are utilized in a variety of technologies. These are components of chips (ICs), which
are components of computers, phones, laptops, and other electronic devices.

2. Logic gates may be combined in a variety of ways, and a million of these combinations are
necessary to make the newest gadgets, satellites, and even robots.

3. Simple logic gate combinations can also be found in burglar alarms, buzzers, switches, and street
lights. Because these gates can make a choice to start or stop based on logic, they are often used in
a variety of sectors.

4. Logic gates are also important in data transport, calculation, and data processing. Even transistor-
transistor logic and CMOS circuitry make extensive use of logic gates.

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BOOLEAN ALGEBRA:

Boolean algebra is a type of algebra that is created by operating the binary system. In the year 1854,
George Boole, an English mathematician, proposed this algebra. This is a variant of Aristotle’s
propositional logic that uses the symbols 0 and 1, or True and False. Boolen algebra is concerned with
binary variables and logic operations.

Boolean Algebra is fundamental in the development of digital electronics systems as they all use the
concept of Boolean Algebra to execute commands.

A boolean function can be expressed algebrically with binary variables, the logic operation symbols,
parenthesis and equal sign. Eg. F = x + y`z

Truth Table:

The truth table is a table that gives all the possible values of logical variables and the combination of the
variables. It is possible to convert the Boolean equation into a truth table. The number of rows in the truth
table should be equal to 2n, where “n” is the number of variables in the equation. For example, if a
Boolean equation consists of 3 variables, then the number of rows in the truth table is 8. (i.e.,) 23 = 8.

Logic Diagram:

A boolean function can be transformed from an algebraic expression into a logic diagram composed of
AND, OR and NOT gates. The purpose of boolean algebra is to facilitate the analysis and design of
digital circuits. It provides a convinient tool to :

1. Express in algebraic form a truth table relationship between binary variables.

2. Express in algebraic form the input – output relationship of logic diagrams.
3. Find simpler circuits for the same function.

Boolean Operations

1. Boolean addition : is equivalent to OR operation. The addition operation of Boolean algebra is

similar to the OR operation. In digital circuits, the OR operation is used to calculate the sum term,
without using AND operation. A + B, A + B', A + B + C', and A'+ B + C + D' are some of the
examples of 'sum term'. The value of the sum term is true when one or more than one literals are

true and false when all the literals are false.

2. Boolean multiplication : is equivalent to AND operation. The multiplication operation of
Boolean algebra is similar to the AND operation. In digital circuits, the AND operation calculates
the product, without using OR operation. AB, AB, ABC, and ABCD are some of the examples of
the product term. The value of the product term is true when all the literals are true and false when
any one of the literal is false.

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Laws of Boolean Algebra

1) Commutative Law :

This law states that no matter in which order we use the variables. It means that the order of variables
doesn't matter. In Boolean algebra, the OR and the addition operations are similar. In the below diagram,
the OR gate display that the order of the input variables does not matter at all.

For two variables, the commutative law of addition is written as: A+B = B+A

A A
B B+A
A+B
0 0 0
0 1 1
1 0 1
1 1 1
B
0 0 0
0 1 1
1 0 1
1 1 1

For two variables, the commutative law of multiplication is written as: A.B = B.A

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 A A
B BA
AB
0 0 0
0 1 0
1 0 0
1 1 1
B
0 0 0
0 1 0
1 0 0
1 1 1

2) Associative Law:

This law states that the operation can be performed in any order when the variables priority is same. As
'*' and '/' have same priority. In the below diagram, the associative law is applied to the 2-input OR gate.

For three variables, the associative law of addition is written as: A + (B + C) = (A + B) + C

A B B C C B+C
A+B A+(B+C)
(A+B)+C
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 1
1 0 0 1 1
1 0 1 1 1
1 1 0 1 1
1 1 1 1 1
A
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 0 0 0 0 0
0 0 1 0 1
0 1 0 1 1
0 1 1 1 1
1 0 0 1 1
1 0 1 1 1
1 1 0 1 1
1 1 1 1 1

According to this law, no matter in what order the variables are grouped when ANDing more than two
variables. In the below diagram, the associative law is applied to 2-input AND gate.

A B C BC A(BC)
A B C AB (AB)C
0 0 0 0 0
0 0 0 0 0
0 0 1 0 0
0 0 1 0 0
0 1 0 0 0
0 1 0 0 0
0 1 1 1 0
0 1 1 0 0
1 0 0 0 0
1 0 0 0 0
1 0 1 0 0
1 0 1 0 0
1 1 0 0 0
1 1 0 1 0
1 1 1 1 1
1 1 1 1 1

3) Distributive Law:

According to this law, if we perform the OR operation of two or more variables and then perform the AND
operation of the result with a single variable, then the result will be similar to performing the AND operation
of that single variable with each two or more variable and then perform the OR operation of that product.
This law explains the process of factoring.

For three variables, the distributive law is written as:

A(B + C) = AB + AC

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A B C B+C A(B+C) A B C AB AC AB+AC
0 0 0 0 0 0 0 0 0 0 0
0 0 1 1 0 0 0 1 0 0 0
0 1 0 1 0 0 1 0 0 0 0
0 1 1 1 0 0 1 1 0 0 0
1 0 0 0 0 1 0 0 0 0 0
1 0 1 1 1 1 0 1 0 1 1
1 1 0 1 1 1 1 0 1 0 1
1 1 1 1 1 1 1 1 1 1 1
A + (B.C) = (A + B) . ( A + C)

Distributive Law

A B C BC A+(BC) A B C A+B A+C (A+B)(A+C)

0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 1 0 1 0
0 1 0 0 0 0 1 0 1 0 0
0 1 1 1 1 0 1 1 1 1 1
1 0 0 0 1 1 0 0 1 1 1
1 0 1 0 1 1 0 1 1 1 1
1 1 0 0 1 1 1 0 1 1 1
13
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Rules of Boolean algebra

There are the following rules of Boolean algebra, which are mostly used in manipulating and simplifying
Boolean expressions. These rules plays an important role in simplifying boolean expressions.

1. A+0=A 7. A.A=A

2. A+1=1 8. A.A'=0

3. A.0=0 9. A''=A

4. A.1=A 10. A+AB=A

5. A+A=A 11. A+A'B=A+B

6. A+A'=1 12. (A+B)(A+C)=A+BC

Rule 1: A + 0 = A

Let's suppose; we have an input variable A whose value is either 0 or 1. When we perform OR operation
with 0, the result will be the same as the input variable. So, if the variable value is 1, then the result will
be 1, and if the variable value is 0, then the result will be 0. Diagrammatically, this rule can be defined as:

Rule 2: (A + 1) = 1

Let's suppose; we have an input variable A whose value is either 0 or 1. When we perform OR operation
with 1, the result will always be 1. So, if the variable value is either 1 or 0, then the result will always be
1. Diagrammatically, this rule can be defined as:

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Rule 3: (A.0) = 0

Let's suppose; we have an input variable A whose value is either 0 or 1. When we perform the AND
operation with 0, the result will always be 0. This rule states that an input variable ANDed with 0 is equal
to 0 always. Diagrammatically, this rule can be defined as:

Rule 4: (A.1) = A

Let's suppose; we have an input variable A whose value is either 0 or 1. When we perform the AND
operation with 1, the result will always be equal to the input variable. This rule states that an input
variable ANDed with 1 is equal to the input variable always. Diagrammatically, this rule can be defined
as:

Rule 5: (A + A) = A

Let's suppose; we have an input variable A whose value is either 0 or 1. When we perform the OR
operation with the same variable, the result will always be equal to the input variable. This rule states an
input variable ORed with itself is equal to the input variable always. Diagrammatically, this rule can be

defined as:
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Rule 6: (A + A') = 1

Let's suppose; we have an input variable A whose value is either 0 or 1. When we perform the OR
operation with the complement of that variable, the result will always be equal to 1. This rule states that a
variable ORed with its complement is equal to 1 always. Diagrammatically, this rule can be defined as:

Rule 7: (A.A) = A

Let's suppose; we have an input variable A whose value is either 0 or 1. When we perform the AND
operation with the same variable, the result will always be equal to that variable only. This rule states that
a variable ANDed with itself is equal to the input variable always. Diagrammatically, this rule can be

defined as:

Rule 8: (A.A') = 0

Let's suppose; we have an input variable A whose value is either 0 or 1. When we perform the AND
operation with the complement of that variable, the result will always be equal to 0. This rule states that a
variable ANDed with its complement is equal to 0 always. Diagrammatically, this rule can be defined as:

Rule 9: A = (A')'

This rule states that if we perform the double complement of the variable, the result will be the same as
the original variable. So, when we perform the complement of variable A, then the result will be A'.
Further if we again perform the complement of A', we will get A, that is the original variable.

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Rule 10: (A + AB) = A

We can prove this rule by using the rule 2, rule 4, and the distributive law as:

A + AB = A(1 + B) Factoring (distributive law)

A + AB = A.1 Rule 2: (1 + B)= 1
A + AB = A Rule 4: A .1 = A

Rule 11: A + A'B = A + B

We can prove this rule by using the above rules as:

A + A'B = (A + AB)+ AB Rule 10: A = A + AB

A+A'B= (AA + AB)+ AB Rule 7: A = AA
A+A'B=AA +AB +AA +AB Rule 8: adding AA = 0
A+A'B= (A + A)(A + B) Factoring
A+A'B= 1.(A + B) Rule 6: A + A = 1
A+A'B=A + B Rule 4: drop the 1

Rule 12: (A + B)(A + C) = A + BC

We can prove this rule by using the above rules as:

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(A + B)(A + C)= AA + AC + AB + BC Distributive law
(A + B)(A + C)= A + AC + AB + BC Rule 7: AA = A
(A + B)(A + C)= A( 1 + C)+ AB + BC Rule 2: 1 + C = 1
(A + B)(A + C)= A.1 + AB + BC Factoring (distributive law)
(A + B)(A + C)= A(1 + B)+ BC Rule 2: 1 + B = 1
(A + B)(A + C)= A.1 + BC Rule 4: A .1 = A
(A + B)(A + C)= A + BC

De Morgan's Theorem :

De Morgan’s theorem is a fundamental principle in Boolean algebra that provides a way to simplify the
complement (negation) of a logical expression involving both AND and OR operations. There are two
forms of De Morgan’s theorem, one for negating an AND operation and another for negating an OR
operation. These theorems are named after the British mathematician and logician Augustus De Morgan.

De Morgan’s Theorem for AND Operations:

The theorem states that the complement of the AND operation between two or more variables is
equivalent to the OR operation of their complements.

Mathematically, for variables A and B (and possibly more):

– NOT (A AND B) = (NOT A) OR (NOT B)

This means that if you want to find the complement of the AND operation of two or more variables, you
can take the complement of each variable individually and then use the OR operation between their
complements.

A B AB AB A B A+ B
0 0 0 1 1 1 1
0 1 0 1 1 0 1
1 0 0 1 0 1 1
1 1 1 0 0 0 0

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LHS = RHS . Hence Proved

De Morgan’s Theorem for OR Operations:

The theorem states that the complement of the OR operation between two or more variables is equivalent
to the AND operation of their complements.

Mathematically, for variables A and B (and possibly more):

– NOT (A OR B) = (NOT A) AND (NOT B)

This means that if you want to find the complement of the OR operation of two or more variables, you
can take the complement of each variable individually and then use the AND operation between their
complements. To prove the above theorem, we need to show that LHS = RHS for all possible values of A
and B. Here are all the four cases –

Case 1 : A=0, B=0

LHS = A+ B = 0+ 0 = 0 = 1
RHS = A . B = 0 . 0 = 1.1 = 1

Case 2 : A=0, B=1

LHS = A+ B = 0+1 = 1 = 0
RHS = A . B = 0 . 1 = 1 . 0 = 0

Case 3 : A=1, B=0

LHS = A+ B = 1+0 = 1 = 0
RHS = A . B = 1 . 0 = 0 . 1 = 0

Case 4 : A=1, B=1

LHS = A+ B = 1+1 = 1 = 0
RHS = A . B = 1 . 1 = 0 . 0 = 0

Hence Proved.

Example 1 – Minimize the following boolean function using algebraic manipulation-

F = ABC'D' + ABC'D + AB'C'D + ABCD + AB'CD + ABCD' + AB'CD'

Solution :

F = ABC'(D'+D) + AB'C'D + ACD(B+B') + ACD' (B+B')

=ABC' + AB'C'D +ACD+ ACD' using rule 6 (A+A' = 1)

= ABC' + AB'C'D + AC (D+D')
= ABC' + AB'C'D +AC using rule 6 (A+A' = 1)
= A(BC' +C) + AB'C'D
= A(B+C) + AB'C'D using rule 11 (A+A'B = A+B)
= AB +AC + AB'C'D
= AB +AC + AC'D using rule 11 (A+A'B = A+B)
= AB + AC+AD using rule 11 (A+A'B = A+B)
Example 2 – F = AB + BC(B+C)

= AB + BC (B + C) Distributing terms
= AB + BBC + BCC Applying Identity AA = A to 2nd and 3rd terms
= AB + BC + BC Applying identity A + A = A to 2nd and 3rd terms
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= AB + BC
= B ( A + C) Factoring B out of terms

Example 3 – A + B (A + C) + AC

= A + B (A + C) + AC
= A + AB + BC + AC Distributing terms
= A + BC + AC Applying rule A + AB = A to 1st and 2nd terms
= A + BC Applying rule A + AB = A to 1st and 3rd terms

Example 4 – (A+B) . (A+C)

= A.A + A.C + A.B + B.C Distributive law

= A + A.C + A.B + B.C Idempotent AND law (A.A = A)
= A (1 + C) + A.B + B.C Distributive law
= A.1 + A.B + B.C Identity OR Law (1+C= 1)
= A(1 + B) + B.C Distributive law
= A.1 + B.C Identity OR Law ( 1+ B = 1)
= A + (B.C) Identity AND Law (A.1 =A)

Map Simplification :
In the previous topic, we have simplified the Boolean functions using Boolean laws and theorems. It is a
time consuming process and we have to rewrite the simplified expression after each step. To overcome
this difficulty Karnaugh introduced a method for simplification of Boolean functions in an easy way. This
method is known as Karnaugh Map method or K-map method. It is a graphical method, which consists of
2n cells for n variables.

The K-map is a systematic way of simplifying Boolean expressions. With the help of the K-map method,
we can find the simplest POS and SOP expression, which is known as the minimum expression. The K-
map provides a cookbook for simplification.

Just like the truth table, a K-map contains all the possible values of input variables and their
corresponding output values. However, in K-map, the values are stored in cells of the array. In each cell,
a binary value of each input variable is stored.

The K-map method is used for expressions containing 2, 3, 4, and 5 variables. For a higher number of
variables, there is another method used for simplification called the Quine-McClusky method. In K-map,
the number of cells is similar to the total number of variable input combinations. For example, if the
number of variables is three, the number of cells is 23=8, and if the number of variables is four, the
number of cells is 24. The K-map takes the SOP and POS forms. The K-map grid is filled using 0's and
1's. The K-map is solved by making groups. There are the following steps used to solve the expressions
using K-map:

1. First, we find the K-map as per the number of variables.

2. Find the maxterm and minterm in the given expression.

3. Fill cells of K-map for SOP with 1 respective to the minterms.

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 4. Fill cells of the block for POS with 0 respective to the maxterm.

5. Next, we create rectangular groups that contain total terms in the power of two like 2, 4, 8, … and
try to cover as many elements as we can in one group.

6. With the help of these groups, we find the product terms and sum them up for the SOP form.

2 Variable K-map

There is a total of 4 variables in a 2-variable K-map. There are two variables in the 2-variable K-map.
The following figure shows the structure of the 2-variable K-map:

o In the above figure, there is only one possibility of grouping four adjacent minterms.

o The possible combinations of grouping 2 adjacent minterms are {(m0, m1), (m2, m3), (m0, m2) and
(m1, m3)}.

Example :

F = ∑(0, 1, 2) or ∑( m0, m1, m2)

K-map for above function will be

Place '1' on the given minterm place.

Now make groups –

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 Red group – A'.B' + A'.B
= A' ( B' + B ) Factoring A' out of terms
= A' By applying B' + B = 1

Purple group – A'.B' + A.B'

= B' ( A' + A) Factoring B' out of terms
= B' By applying A' + A = 1
So the answer in SOP ( Sum of Products) is A' + B'

3 variable K-map :

The 3-variable K-map is represented as an array of eight cells. In this case, we used A, B, and C for the
variable. We can use any letter for the names of the variables. The binary values of variables A and B are
along the left side, and the values of C are across the top. The value of the given cell is the binary values
of A and B at left side in the same row combined with the value of C at the top in the same column. For
example, the cell in the upper left corner has a binary value of 000, and the cell in the lower right corner
has a binary value of 101.

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Example :

F(A,B,C) = ∑ (m0, m1, m2, m4, m5, m6)

K- map for above function will be

Place '1' on the given minterm place.

Now make groups –

Red group – A'B'C' + A'B'C + AB'C' + AB'C

= A'B' (C' + C) + AB' (C' + C) Factoring 1st and 2nd terms, 3rd and 4th terms
= A'B' + AB' Applying identiy (C'+C = 1)
= B' (A' + A) Factoring 1st and 2nd terms
= B' Applying identity (B' + B = 1)

Purple group – A'B'C' + A'BC' + AB'C' + ABC'

= A'C' (B' + B) + AC' (B' + B) Factoring 1st and 2nd terms, 3rd and 4th terms
= A'C' + AC' Applying identiy (B'+B = 1)
= C' (A'+A) Factoring 1st and 2nd terms
= C' Applying identiy (A'+A = 1)
Thus answer is F = B' + C'
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4 Variable Karnaugh Map :

The 4-variable K-map is represented as an array of 16 cells. Binary values of A and B are along the left
side, and the values of C and D are across the top. The value of the given cell is the binary values of A
and B at left side in the same row combined with the binary values of C and D at the top in the same
column. For example, the cell in the upper right corner has a binary value of 0010, and the cell in the
lower right corner has a binary value of 1010.

Example:

F(A,B,C,D) = ∑(m0,m1,m2,m4,m5,m6,m8,m9,m12,m13,m14)

K- map for above function will be

Place '1' on the given minterm place.

Now make groups –
Red group – A'B'C'D' + A'B'C'D + A'BC'D' + A'BC'D + ABC'D' + ABC'D + AB'C'D' + AB'C'D
= A'B'C'(D'+D) + A'BC'(D'+D) + ABC'(D'+D) + AB'C'(D'+D)
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Factoring the terms and taking common from 1-2, 3-4, 5-6, 7-8 terms
= A'B'C' + A'BC' + ABC' + AB'C' Applying identiy (D'+D = 1)
= A'C'(B'+B) + AC'(B+B') Factoring the terms and taking common
= A'C' + AC' Applying identiy (B'+B = 1)
= C'(A'+A) Factoring the terms and taking common
= C' Applying identiy (A'+A = 1)
Purple group – A'B'C'D' + A'B'CD' + A'BC'D' + A'BCD'
= A'B'D' (C'+C) + A'BD' (C'+C) Factoring the terms and taking common
= A'B'D' + A'BD' Applying identiy (C'+C = 1)
=A'D' (B'+B) Factoring the terms and taking common
=A'D' Applying identiy (B'+B = 1)
Green group – A'BC'D' + A'BCD' + ABC'D' + ABCD'
= A'BD' (C'+C) + ABD'(C'+C) Factoring the terms and taking common
= A'BD' + ABD' Applying identiy (C'+C = 1)
= BD' (A'+A) Factoring the terms and taking common
= BD' Applying identiy (A'+A = 1)
Solution = A'D' + BD' + C' or D'(A' + B ) + C'

5-variable K-map:

With the help of the 32- cell K-map, the boolean expression with 5 variables can be simplified. For
constructing a 5-variable K-map, we use two 4-variable K-maps. The cell adjacencies within each of the
4- variable maps for the 5-variable map are similar to the 4- variable map.
A K-map for five variables (PQRST) can be constructed using two 4-variable maps. Each map contains
16 cells with all combinations of variables Q, R, S, and T. One map is for P = 0, and the other is for P =
1).

Example :
F (A,B,C,D,E) = ∑ (m0,m2,m4,m7,m8,m10,m12,m16,m18,m20,m23,m24,m25,m26,m27,m28)
K- map for above function will be

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Red group – (0,4,8,12,16,20,24,28)
A'B'C'D'E' + A'B'CD'E' + A'BCD'E' + A'B'CD'E' = D'E'
Blue group – (24,25,26,27)
ABC'D'E' + ABC'D'E + ABC'DE + ABC'DE' = ABC'
Purple group – (0,2,8,10,16,18,24,26)
A'B'C'D'E' + A'B'C'DE' + A'BC'D'E' + A'BC'DE' + AB'C'D'E' + AB'C'DE' + ABC'D'E' + ABC'DE' = C'E'
Green group – (7,23)
A'B'CDE + AB'CDE = B'CDE

Solution = (D'E' + ABC' + C'E' + B'CDE)

Don’t Care (X) Conditions in K-Maps :

One of the very significant and useful concepts in simplifying the output expression using K-Map is the
concept of “Don’t Care”. The “Don’t Care” conditions allow us to replace the empty cell of a K-Map to
form a grouping of the variables which is larger than that of forming groups without don’t care. While
forming groups of cells, we can consider a “Don’t Care” cell as 1 or 0 or we can also ignore that cell.
Therefore, the “Don’t Care” condition can help us to form a larger group of cells.
A Don’t Care cell can be represented by a cross(X) or minus(-) or phi(Φ) in K-Maps representing an
invalid combination. For example, in the Excess-3 code system, the states 0000, 0001, 0010, 1101, 1110,
and 1111 are invalid or unspecified. These states are called don’t cares.
A standard SOP function having don’t cares can be converted into a POS expression by keeping don’t
cares as they are, and writing the missing minterms of the SOP form as the maxterm of POS form.
Similarly, a POS function having don’t cares can be converted to SOP form keeping the don’t cares as
they are and writing the missing maxterms of the POS expression as the minterms of SOP expression.

Example-1:
Minimise the following function in SOP minimal form using K-Maps:
f = m(1, 5, 6, 11, 12, 13, 14) + d(4)
Explanation:
The SOP K-map for the given expression is:

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Therefore, SOP minimal is,

f = BC' + BD' + A'C'D + AB'CD

Example-2:
Minimise the following function in POS minimal form using K-Maps:
F(A, B, C, D) = m(0, 1, 2, 3, 4, 5) + d(10, 11, 12, 13, 14, 15)
Explanation:
Writing the given expression in POS form:

F(A, B, C, D) = M(6, 7, 8, 9) + d(12, 13, 14, 15)

The POS K-map for the given expression is:

Therefore, POS minimal is,

F = (A'+ C)(B' + C')

Example-3:
Minimise the following function in SOP minimal form using K-Maps:
F(A, B, C, D) = m(1, 2, 6, 7, 8, 13, 14, 15) + d(0, 3, 5, 12)
Explanation:
The SOP K-map for the given expression is:

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Therefore,

f = AC'D' + A'D + A'C + AB

Significance of “Don’t Care” Conditions:
Don’t Care conditions has the following significance in designing of the digital circuits:

1. Simplification of the output:

These conditions denotes inputs that are invalid for a given digital circuit. Thus, they can used to
further simplify the boolean output expression of a digital circuit.

2. Reduction in number of gates required:

Simplification of the expression reduces the number of gates to be used for implementing the
given expression. Therefore, don’t cares make the digital circuit design more economical.

3. Reduced Power Consumption:

While grouping the terms along with don’t cares reduces switching of the states. This decreases
the memory space that is required to represent a given digital circuit which in turn results in less
power consumption.

4. Represent Invalid States in Code Converters:

These are used in code converters. For example- In design of 4-bit BCD-to-XS-3 code converter,
the input combinations 1010, 1011, 1100, 1101, 1110, and 1111 are don’t cares.

5. Prevention of Hazards in Digital Circuits:

Don’t cares also prevents hazards in digital systems.

Combinational Circuit :
The The combinational logic circuits are the circuits that contain different types of logic gates. Simply, a
circuit in which different types of logic gates are combined is known as a combinational logic circuit. The output
of the combinational circuit is determined from the present combination of inputs, regardless of the previous
input. The input variables, logic gates, and output variables are the basic components of the combinational logic
circuit. There are different types of combinational logic circuits, such as Adder, Subtractor, Decoder, Encoder,
Multiplexer, and De-multiplexer.
There are the following characteristics of the combinational logic circuit:

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 o At any instant of time, the output of the combinational circuits depends only on the present input
terminals.
o The combinational circuit doesn't have any backup or previous memory. The present state of the
circuit is not affected by the previous state of the input.
o The n number of inputs and m number of outputs are possible in combinational logic circuits.

The 'n' input variable comes from the external source while the 'm' output variable goes to the external
destination. In many applications, the source or destinations are storage registers.

1) Half Adder –

Half adder is the simplest of all adder circuits. Half adder is a combinational arithmetic circuit that
adds two numbers and produces a sum bit (s) and carry bit (c) both as output. The addition of 2
bits is done using a combination circuit called a Half adder. The input variables are augend and
addend bits and output variables are sum & carry bits. A and B are the two input bits.
let us consider two input bits A and B, then sum bit (s) is the X-OR of A and B. it is evident from
the function of a half adder that it requires one X-OR gate and one AND gate for its construction.

Truth Table:
Input Output
A B Carry Sum
'C' 'S'
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Logical Expression:

Sum = A' . B + A . B' or A XOR B

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 Carry = AB

Circuit diagram :

Advantages of Half Adder in Digital Logic :

1.Simplicity: A half viper is a straightforward circuit that requires a couple of fundamental parts like
XOR AND entryways. It is not difficult to carry out and can be utilized in numerous advanced
frameworks.
2.Speed: The half viper works at an extremely rapid, making it reasonable for use in fast computerized
circuits.

Disadvantages of Half Adder in Digital Logic :

1.Limited Usefulness: The half viper can add two single-piece numbers and produce a total and a convey
bit. It can’t perform expansion of multi-bit numbers, which requires the utilization of additional intricate
circuits like full adders.
2.Lack of Convey Info: The half snake doesn’t have a convey input, which restricts its value in more
mind boggling expansion tasks. A convey input is important to perform expansion of multi-bit numbers
and to chain numerous adders together.
3.Propagation Deferral: The half snake circuit has a proliferation delay, which is the time it takes for
the result to change in light of an adjustment of the info. This can cause timing issues in computerized
circuits, particularly in fast frameworks.

Application of Half Adder in Digital Logic:

1.Arithmetic circuits: Half adders are utilized in number-crunching circuits to add double numbers. At
the point when different half adders are associated in a chain, they can add multi-bit double numbers.
2.Data handling: Half adders are utilized in information handling applications like computerized signal
handling, information encryption, and blunder adjustment.
3.Address unraveling: In memory tending to, half adders are utilized in address deciphering circuits to
produce the location of a particular memory area.
4.Encoder and decoder circuits: Half adders are utilized in encoder and decoder circuits for
computerized correspondence frameworks.

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5.Multiplexers and demultiplexers: Half adders are utilized in multiplexers and demultiplexers to
choose and course information.
6.Counters: Half adders are utilized in counters to augment the count by one.

2. Full Adder –

The half adder is used to add only two numbers. To overcome this problem, the full adder was developed.
The full adder is used to add three 1-bit binary numbers A, B, and carry C. The full adder has three input
states and two output states i.e., sum and carry.

Logical Expression for SUM: = (1,2,4,7) = A'B'CIN + A'BCIN' + AB'CIN' + ABCIN

= CIN (A'B' + AB) + CIN' (A'B + AB')
= CINXOR (A XOR B)

Logical Expression for C-OUT: = (3,5,6,7) = A'BCIN+ AB'CIN+ ABCIN' + ABCIN

= CIN(A'B + AB') + AB (CIN' + CIN)
= CIN(A'B + AB') + AB
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 Inputs Outputs
A B Cin Carry Sum
'Co' 'S'
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Logic Circuit

Implementation of Full Adder using Half Adders:

2 Half Adders and an OR gate is required to implement a Full Adder. With this logic circuit, two bits can
be added together, taking a carry from the next lower order of magnitude, and sending a carry to the next
higher order of magnitude.

Implementation of Full Adder using NOR gates:

Total 9 NOR gates are required to implement a Full Adder.

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 In the logic expression above, one would recognize the logic expressions of a 1-bit half-adder. A 1-bit
full adder can be accomplished by cascading two 1-bit half adders.

Advantages of Full Adder in Digital Logic:

1.Flexibility: A full snake can add three information bits, making it more flexible than a half viper. It can
likewise be utilized to add multi-bit numbers by binding different full adders together.
2.Carry Info: The full viper has a convey input, which permits it to perform expansion of multi-bit
numbers and to chain different adders together.
3.Speed: The full snake works at an extremely fast, making it reasonable for use in rapid computerized
circuits.

Disadvantages of Full Adder in Digital Logic:

1.Complexity: The full snake is more mind boggling than a half viper and requires more parts like XOR,
AND, or potentially entryways. It is likewise more challenging to execute and plan.
2.Propagation Deferral: The full viper circuit has a proliferation delay, which is the time it takes for the
result to change in light of an adjustment of the info. This can cause timing issues in computerized
circuits, particularly in fast frameworks.
Application of Full Adder in Digital Logic:

1.Arithmetic circuits: Full adders are utilized in math circuits to add twofold numbers. At the point
when different full adders are associated in a chain, they can add multi-bit paired numbers.
2.Data handling: Full adders are utilized in information handling applications like advanced signal
handling, information encryption, and mistake rectification.
3.Counters: Full adders are utilized in counters to addition or decrement the count by one.
4.Multiplexers and demultiplexers: Full adders are utilized in multiplexers and demultiplexers to
choose and course information.
5.Memory tending to: Full adders are utilized in memory addressing circuits to produce the location of a
particular memory area.
6.ALUs: Full adders are a fundamental part of Number juggling Rationale Units (ALUs) utilized in chip
and computerized signal processors.

Decoders :
The name “Decoder” means to translate or decode coded information from one format into another, so a
digital decoder transforms a set of digital input signals into an equivalent decimal code at its output. A
decoder is a combinational circuit having n inputs and to a maximum of m = 2n outputs. The decoder is
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the same as the de-multiplexer. The only difference between de-multiplexer and decoder is that in the
decoder, there is no data input. The decoder performs an operation that is completely opposite of an
encoder and are commonly used in digital systems to convert a serial code into a parallel set of outputs.

1. The basic principle of a binary decoder is to assign a unique output to each possible binary code.
For example, a binary decoder with 4 inputs and 2^4 = 16 outputs can assign a unique output to
each of the 16 possible 4-bit binary codes.
2. The inputs of a binary decoder are usually active low, meaning that only one input is active (low)
at any given time, and the remaining inputs are inactive (high). The active low input is used to
select the specific output that is active.
3. There are different types of binary decoders, including priority decoders, which assign a priority
to each output, and error-detecting decoders, which can detect errors in the binary code and
generate an error signal.

There are various types of decoders which are as follows:

2 to 4 line decoder:
In the 2 to 4 line decoder, there is a total of three inputs, i.e., A0, and A1 and E and four outputs,
i.e., Y0, Y1, Y2, and Y3. For each combination of inputs, when the enable 'E' is set to 1, one of these four
outputs will be 1. The block diagram and the truth table of the 2 to 4 line decoder are given below.

Block Diagram:

Truth Table:

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Logical Expression :
The logical expression of the term Y0, Y0, Y2, and Y3 is as follows:
Y3=E.A1.A0
Y2=E.A1.A0'
Y1=E.A1'.A0
Y0=E.A1'.A0'

Logical circuit of the above expressions is given below:

3 to 8 line decoder:
The 3 to 8 line decoder is also known as Binary to Octal Decoder. In a 3 to 8 line decoder, there
is a total of eight outputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 and three outputs, i.e., A0, A1, and A2.
This circuit has an enable input 'E'. Just like 2 to 4 line decoder, when enable 'E' is set to 1, one of these
four outputs will be 1. The block diagram and the truth table of the 3 to 8 line encoder are given below.

Block Diagram:

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Truth Table:

The logical expression of the term Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 is as follows:
Y0 = A0' . A1' . A2'
Y1 = A0 . A1' . A2'
Y2 = A0' . A1 . A2'
Y3 = A0 . A1 . A2'
Y4 = A0' . A1' . A2
Y5 = A0 . A1' . A2
Y6 = A0' . A1 . A2
Y7 = A0 . A1 . A2

Logical circuit of the above expressions is given below:

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4 to 16 line Decoder
In the 4 to 16 line decoder, there is a total of 16 outputs, i.e., Y0, Y1, Y2,……, Y16 and four inputs,
i.e., A0, A1, A2, and A3. The 3 to 16 line decoder can be constructed using either 2 to 4 decoder or 3 to 8
decoder. There is the following formula used to find the required number of lower-order decoders.
Required number of lower order decoders=m2/m1
m1 = 8
m2 = 16
16
Required number of 3 to 8 decoders = = 2
8

Block Diagram:

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The logical expression of the term A0, A1, A2,…, A15 are as follows:

Y0=A0'.A1'.A2'.A3'
Y1=A0'.A1'.A2'.A3
Y2=A0'.A1'.A2.A3'
Y3=A0'.A1'.A2.A3
Y4=A0'.A1.A2'.A3'
Y5=A0'.A1.A2'.A3
Y6=A0'.A1.A2.A3'
Y7=A0'.A1.A2.A3
Y8=A0.A1'.A2'.A3'
Y9=A0.A1'.A2'.A3
Y10=A0.A1'.A2.A3'
Y11=A0.A1'.A2.A3
Y12=A0.A1.A2'.A3'
Y13=A0.A1.A2'.A3
Y14=A0.A1.A2.A3'
Y15=A0.A1.A2'.A3

Truth Table:

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Logical circuit of the above expressions is given below:

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Advantages of using Binary Decoders in Digital Logic:

1. Increased flexibility: Binary decoders provide a flexible way to select one of multiple outputs
based on a binary code, allowing for a wide range of applications.
2. Improved performance: By converting a serial code into a parallel set of outputs, binary
decoders can improve the performance of a digital system by reducing the amount of time
required to transmit information from a single input to multiple outputs.
3. Improved reliability: By reducing the number of lines required to transmit information from a
single input to multiple outputs, binary decoders can reduce the possibility of errors in the
transmission of information.

Disadvantages of using Binary Decoders in Digital Logic:

1. Increased complexity: Binary decoders are typically more complex circuits compared to
demultiplexers, and require additional components to implement.
40 | P a g e
 2. Limited to specific applications: Binary decoders are only suitable for applications where a
serial code must be converted into a parallel set of outputs.
3. Limited number of outputs: Binary decoders are limited in their number of outputs, as the
number of outputs is determined by the number of inputs and the binary code used.

In conclusion, binary decoders are useful digital circuits that have their advantages and disadvantages.
The choice of whether to use a binary decoder or not depends on the specific requirements of the system
and the trade-offs between complexity, reliability, performance, and cost.

Application of Binary Decoder in Digital Logic:

1.Memory tending to: In computerized frameworks, paired decoders are generally used to choose a
particular memory area from a variety of memory areas. The location inputs are applied to the double
decoder, and the comparing memory area is chosen.
2.Control circuits: Parallel decoders are utilized in charge circuits to produce control signals for various
tasks. For instance, in a microchip, a double decoder is utilized to translate the guidance opcode and
produce control signals for the comparing activity.
3.Display drivers: In computerized frameworks that utilization show gadgets, for example, Drove
shows, parallel decoders are utilized to drive the presentation. The double data sources are applied to the
decoder, and the relating Drove is enlightened.
4.Address unraveling: Parallel decoders are utilized in address disentangling circuits to create the chip
select sign for a particular memory or fringe gadget.
5.Digital correspondence: Twofold decoders are utilized in advanced correspondence frameworks to
unravel the computerized information got over the correspondence channel.
6.Error rectification: Double decoders are utilized in mistake amendment circuits to recognize and
address blunders in computerized information.

Multiplexers :
A multiplexer is a combinational circuit that has 2n input lines and a single output line. Simply, the
multiplexer is a multi-input and single-output combinational circuit. The binary information is received
from the input lines and directed to the output line. On the basis of the values of the selection lines, one of
these data inputs will be connected to the output.

Multiplexers are also known as data n selector, parallel to serial convertor, many to one circuit,
universal logic circuit”. Multiplexers are mainly used to increase amount of the data that can be sent
over the network within certain amount of time and bandwidth.

Unlike encoder and decoder, there are n selection lines and 2n input lines. So, there is a total of
2N possible combinations of inputs. A multiplexer is also treated as Mux.

There are various types of the multiplexer which are as follows:

2×1 Multiplexer:
In 2×1 multiplexer, there are only two inputs, i.e., A0 and A1, 1 selection line, i.e., S0 and single
outputs, i.e., Y. On the basis of the combination of inputs which are present at the selection line S 0, one of
these 2 inputs will be connected to the output.

Block diagram of the 2×1 multiplexer

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Truth table of the 2×1 multiplexer

The logical expression of the term Y is as follows:

Y=S0'.A0+S0.A1

Logical circuit of the above expression is given below:

a) Implementation of NOT gate using 2 : 1 Mux

NOT Gate :

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We can analyze it
Y = x’.1 + x.0 = x’
It is NOT Gate using 2:1 MUX.
The implementation of NOT gate is done using “n” selection lines. It cannot be implemented using “n-1”
selection lines. Only NOT gate cannot be implemented using “n-1” selection lines.

b) Implementation of AND gate using 2 : 1 Mux

AND GATE

This implementation is done using “n-1” selection lines.

c) Implementation of OR gate using 2 : 1 Mux using “n-1” selection lines.

OR GATE

Implementation of NAND, NOR, XOR and XNOR gates requires two 2:1 Mux. First multiplexer will act
as NOT gate which will provide complemented input to the second multiplexer.

d) Implementation of NAND gate using 2 : 1 Mux

NAND GATE

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e) Implementation of NOR gate using 2 : 1 Mux
NOR GATE

f) Implementation of EX-OR gate using 2 : 1 Mux

EX-OR GATE

g) Implementation of EX-NOR gate using 2 : 1 Mux

EX-NOR GATE

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4×1 Multiplexer:
In the 4×1 multiplexer, there is a total of four inputs, i.e., A0, A1, A2, and A3, 2 selection lines, i.e.,
S0 and S1 and single output, i.e., Y. On the basis of the combination of inputs that are present at the
selection lines S0 and S1, one of these 4 inputs are connected to the output.

Block Diagram of the 4×1 multiplexer:

Truth table of the 4×1 multiplexer is –

The logical expression of the term Y is as follows:

Y=S1' S0' A0+S1' S0 A1+S1 S0' A2+S1 S0 A3

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Logical circuit of the above expression is given below:

8 to 1 Multiplexer
In the 8 to 1 multiplexer, there are total eight inputs, i.e., A0, A1, A2, A3, A4, A5, A6, and A7, 3
selection lines, i.e., S0, S1and S2 and single output, i.e., Y. On the basis of the combination of inputs that
are present at the selection lines S0, S1, and S2, one of these 8 inputs are connected to the output. The block
diagram and the truth table of the 8×1 multiplexer are given below.

Block Diagram:

Truth Table:

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The logical expression of the term Y is as follows:
Y=S0'.S1'.S2'.A0+S0.S1'.S2'.A1+S0'.S1.S2'.A2+S0.S1.S2'.A3+S0'.S1'.S2 A4+S0.S1'.S2 A5+S0'.S1.S2 .A6+S0.S1.S3.A7

Logical circuit of the above expression is given below:

16 to 1 Multiplexer
In the 16 to 1 multiplexer, there are total of 16 inputs, i.e., A 0, A1, …, A16, 4 selection lines, i.e., S 0, S1,
S2, and S3 and single output, i.e., Y. On the basis of the combination of inputs that are present at the
selection lines S0, S1, and S2, one of these 16 inputs will be connected to the output. The block diagram
and the truth table of the 16×1

47 | P a g e
Block Diagram:

The logical expression of the term Y is as follows:

Y=A0.S0'.S1'.S2'.S3'+A1.S0'.S1'.S2 '.S3+A2.S0'.S1'.S2.S3'+A3.S0'.S1 '.S2.S3+A4.S0'.S1.S2'.S3'+A5.S0 '.S1.S2'.S3+

A6.S1.S2.S3'+A7.S0 '.S1.S2.S3+A8.S0.S1'.S2'.S3'+A9 .S0.S1'.S2'.S3+Y10.S0.S1'.S2.S3 '+A11.S0.S1'.S2.S3+A12
S0.S1.S2 '.S3'+A13.S0.S1.S2'.S3+A14.S0.S1 .S2.S3'+A15.S0.S1.S2'.S3

Truth Table :

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Logical circuit of the above expression is given below:

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Advantages of Multiplexers in Digital Logic:

1.Space-saving: Multiplexers consider numerous signs to be directed through a solitary channel, which
recoveries space in computerized circuits.
2.Cost-successful: Multiplexers can assist with decreasing the expense of Advanced circuits by
diminishing the quantity of parts required.
3.Time-saving: Multiplexers can save time in computerized circuits by decreasing the quantity of parts
that should be wired together, subsequently diminishing the intricacy of the circuit.
4.Flexibility: Multiplexers are profoundly adaptable and can be utilized in a great many applications.

Disadvantages of Multiplexers in Digital Logic:

1.Limited number of data sources: The quantity of sources of info that can be taken care of by a
multiplexer is restricted by the quantity of control lines, which can be a disservice in certain
applications.
2.Delay: Multiplexers can present some postpone in the sign way, which can influence the exhibition
of the circuit.
3.Complex control rationale: The control rationale for multiplexers can be perplexing, particularly for
bigger multiplexers with an enormous number of data sources.
4.Power utilization: Multiplexers can consume more power contrasted with other straightforward
rationale entryways, particularly when they have countless data sources.

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Sequential Circuits :
In our previous sections, we learned about combinational circuit and their working. The
combinational circuits have set of outputs, which depends only on the present combination of inputs.
Sequential circuits are digital circuits that store and use the previous state information to determine their
next state. Unlike combinational circuits, which only depend on the current input values to produce
outputs, sequential circuits depend on both the current inputs and the previous state stored in memory
elements.
1. Sequential circuits are commonly used in digital systems to implement state machines, timers,
counters, and memory elements. The memory elements in sequential circuits can be implemented
using flip-flops, which are circuits that store binary values and maintain their state even when the
inputs change.
2. There are two types of sequential circuits: finite state machines (FSMs) and synchronous
sequential circuits. FSMs are designed to have a limited number of states and are typically used to
implement state machines and control systems. Synchronous sequential circuits, on the other
hand, are designed to have an infinite number of states and are typically used to implement timers,
counters, and memory elements.

In summary, sequential circuits are digital circuits that store and use previous state information to
determine their next state. They are commonly used in digital systems to implement state machines,
timers, counters, and memory elements and are essential components in digital systems design.

Sequential circuit is a combinational logic circuit that consists of inputs variable (X), logic gates
(Computational circuit), and output variable (Z). Below is the block diagram of the synchronous logic
circuit.

The sequential circuit is a special type of circuit that has a series of inputs and outputs. The
outputs of the sequential circuits depend on both the combination of present inputs and previous outputs.
The previous output is treated as the present state. So, the sequential circuit contains the combinational
circuit and its memory storage elements. A sequential circuit doesn't need to always contain a
combinational circuit. So, the sequential circuit can contain only the memory element.

Difference between the combinational circuits and sequential circuits are given below:

Combinational Circuits Sequential Circuits

1) The outputs of the combinational The outputs of the sequential circuits

circuit depend only on the present depend on both present inputs and present

51 | P a g e
 inputs. state(previous output).

2) The feedback path is not present in The feedback path is present in the
the combinational circuit. sequential circuits.

3) In combinational circuits, memory In the sequential circuit, memory elements

elements are not required. play an important role and require.

4) The clock signal is not required for The clock signal is required for sequential
combinational circuits. circuits.

5) The combinational circuit is simple It is not simple to design a sequential

to design. circuit.

Types of Sequential Circuits

Asynchronous sequential circuits

The clock signals are not used by the Asynchronous sequential circuits. The asynchronous
circuit is operated through the pulses. So, the changes in the input can change the state of the circuit. The
asynchronous circuits do not use clock pulses. The internal state is changed when the input variable is
changed. The un-clocked flip-flops or time-delayed are the memory elements of asynchronous sequential
circuits. The asynchronous sequential circuit is similar to the combinational circuits with feedback.

Synchronous sequential circuits

In synchronous sequential circuits, synchronization of the memory element's state is done by the
clock signal. The output is stored in either flip-flops or latches(memory devices). The synchronization of
the outputs is done with either only negative edges of the clock signal or only positive edges.

Clock Signal and Triggering

Clock signal

A clock signal is a periodic signal in which ON time and OFF time need not be the same. When
ON time and OFF time of the clock signal are the same, a square wave is used to represent the clock
signal. Below is a diagram which represents the clock signal:
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A clock signal is considered as the square wave. Sometimes, the signal stays at logic, either high 5V or
low 0V, to an equal amount of time. It repeats with a certain time period, which will be equal to twice the
'ON time' or 'OFF time'.

Types of Triggering

These are two types of triggering in sequential circuits:

1) Level triggering - The logic High and logic Low are the two levels in the clock signal. In
level triggering, when the clock pulse is at a particular level, only then the circuit is
activated. There are the following types of level triggering:

a) Positive level triggering - In a positive level triggering, the signal with Logic
High occurs. So, in this triggering, the circuit is operated with such type of clock
signal. Below is the diagram of positive level triggering:

b) Negative level triggering - In negative level triggering, the signal with Logic Low
occurs. So, in this triggering, the circuit is operated with such type of clock signal.
Below is the diagram of Negative level triggering:

2) Edge triggering - In clock signal of edge triggering, two types of transitions occur, i.e.,
transition either from Logic Low to Logic High or Logic High to Logic Low.
Based on the transitions of the clock signal, there are the following types of edge triggering:

a) Positive edge triggering - The transition from Logic Low to Logic High occurs in
the clock signal of positive edge triggering. So, in positive edge triggering, the
circuit is operated with such type of clock signal. The diagram of positive edge
triggering is given below.

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 b) Negative edge triggering - The transition from Logic High to Logic low occurs in
the clock signal of negative edge triggering. So, in negative edge triggering, the
circuit is operated with such type of clock signal. The diagram of negative edge
triggering is given below.

Advantages of Sequential Circuits:

1. Memory: Sequential circuits have the ability to store binary values, which makes them ideal for
applications that require memory elements, such as timers and counters.
2. Timing: Sequential circuits are commonly used to implement timing and synchronization in
digital systems, making them essential for real-time control applications.
3. State machine implementation: Sequential circuits can be used to implement state machines,
which are useful for controlling complex digital systems and ensuring that they operate as
intended.
4. Error detection: Sequential circuits can be designed to detect errors in digital systems and respond
accordingly, improving the reliability of digital systems.

Disadvantages of Sequential Circuits:

1. Complexity: Sequential circuits are typically more complex than combinational circuits and
require more components to implement.
2. Timing constraints: The design of sequential circuits can be challenging due to the need to ensure
that the timing of the inputs and outputs is correct.
3. Testing and debugging: Testing and debugging sequential circuits can be more difficult compared
to combinational circuits due to their complex structure and state-dependant outputs.
In conclusion, sequential circuits have their advantages and disadvantages, but they play an important
role in digital systems design due to their ability to store and use binary values, implement timing and
synchronization, and implement state machines.

Flip Flops :

A circuit that has two stable states is treated as a flip flop. These stable states are used to store binary
data that can be changed by applying varying inputs. The flip flops are the fundamental building blocks
of the digital system. Flip flops and latches are examples of data storage elements. In the sequential
logical circuit, the flip flop is the basic storage element. The latches and flip flops are the basic storage
elements but different in working. There are the following types of flip flops:
1. S-R Flip Flop
2. JK Flip Flop
3. D Flip Flop
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 4. T Flip Flop

Applications of Flip-Flops:
These are the various types of flip-flops being used in digital electronic circuits and the applications of
Flip-flops are as specified below.
 Counters
 Frequency Dividers
 Shift Registers
 Storage Registers
 Bounce elimination switch
 Data storage
 Data transfer
 Latch
 Registers
 Memory

SR Flip Flop

The S-R flip flop is the most common flip flop used in the digital system. In SR flip flop, when the
set input "S" is true, the output Y will be high, and Y' will be low. It is required that the wiring of the
circuit is maintained when the outputs are established. We maintain the wiring until set or reset input
goes high, or power is shutdown.

Block Diagram :

The SR flip flop is a 1-bit memory bistable device having two inputs, i.e., SET and RESET. The SET
input 'S' set the device or produce the output 1, and the RESET input 'R' reset the device or produce the
output 0. The SET and RESET inputs are labeled as S and R, respectively.
The SR flip flop stands for "Set-Reset" flip flop. The reset input is used to get back the flip flop to its
original state from the current state with an output 'Q'. This output depends on the set and reset
conditions, which is either at the logic level "0" or "1".

Circuit Diagram of SR Flip Flop:

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 The S-R flip flop is the simplest and easiest circuit to understand.
Truth Table of SR Flip Flop:

S R Q(n+1)
0 0 Q(n) No Change
0 1 0
Clear to 0
1 0 1 Set to 1
1 1 ? Invalid

Working of SR Flip Flop

 Case 1: Let’s say, S=0 and R=0, then output of both AND gates will be 0 and the value of Q and
Q’ will be same as their previous value, i.e, Hold state.
 Case 2: Let’s say, S=0 and R=1, then output of both AND gates will be 1 and 0, correspondingly
the value of Q will be 0 as one of input is 1 and it is a NOR gate so it will ultimately gives 0,
hence Q gets 0 value, similarly Q’ will be 1.
 Case 3: Let’s say, S=1 and R=0, then output of both AND gates will be 0 and 1, correspondingly
the value of Q’ will be 0 as one of input to NOR gate is 1, so output will be 0 ultimately and this 0
value will go as input to upper NOR gate, and hence Q will become 1.
 Case 4: Let’s say, S=1 and R=1, then output of both AND gates will be 1 and 1 which is invalid,
as the outputs should be complement of each other.

Characteristic Table of SR Flip Flop:

S R Q(n Q(n+1)
)
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 X
1 1 1 X

Characteristic Equation of SR Flip Flop :

 The characteristic equation tells us about what will be the next state of flip flop in terms of present
state.
 In order to get the characteristic equation, K-Map is constructed which will be shown as below:

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  Q(n+1) = S + R'Qn

Excitation Table of SR Flip Flop :

In electronics design, an excitation table shows the minimum inputs that are necessary to generate a
particular next state (in other words, to “excite” it to the next state) when the current state is known. They
are similar to truth tables and state tables, but rearrange the data so that the current state and next state are
next to each other on the left-hand side of the table, and the inputs needed to make that state change
happen are shown on the right side of the table.
The excitation table of SR Flip Flop indicate the excitations required to take the flip flop from the
present state to the next state.

Qn Qn+1 S R
0 0 0 X
0 1 1 0
1 0 0 1
1 1 X 0

Applications of SR Flip Flop

There are numerous applications of SR Flip Flop in Digital System, which are listed below:
 Register: SR Flip Flop used to create register. Designer can create any size of register by
combining SR Flip Flops.
 Counters: SR Flip Flops used in counters. Counters counts the number of events that occurs in a
digital system.
 Memory: SR Flip Flops used to create memory which are used to store data, when the power is
turned off.
 Synchronous System: SR Flip Flop are used in synchronous system which are used to
synchronise the operation of different component.

J-K Flip-flop :

The SR Flip Flop or Set-Reset flip flop has lots of advantages. But, it has the following switching
problems:
o When Set 'S' and Reset 'R' inputs are set to 0, this condition is always avoided.
o When the Set or Reset input changes their state while the enable input is 1, the incorrect latching
action occurs.
The JK Flip Flop removes these two drawbacks of SR Flip Flop.

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 The JK flip flop is one of the most used flip flops in digital circuits. It bears the name of its originator
Jack Kilby. The JK flip flop is a universal flip flop having two inputs 'J' and 'K'. In SR flip flop, the 'S'
and 'R' are the shortened abbreviated letters for Set and Reset, but J and K are not. The J and K are
themselves autonomous letters which are chosen to distinguish the flip flop design from other types.
The JK flip flop work in the same way as the SR flip flop work. The JK flip flop has 'J' and 'K' flip
flop instead of 'S' and 'R'. The only difference between JK flip flop and SR flip flop is that when both
inputs of SR flip flop is set to 1, the circuit produces the invalid states as outputs, but in case of JK flip
flop, there are no invalid states even if both 'J' and 'K' flip flops are set to 1.

Block Diagram :

In J-K flip flop, if both of its inputs are different, the value of J at the next clock edge is taken by the
output Y. If both of its input is low, then no change occurs, and if high at the clock edge, then from one
state to the other, the output will be toggled. The JK Flip Flop is a Set or Reset Flip flop in the digital
system. JK Flip Flop is universal Flip Flop.

The JK flip flop is an improved clocked SR flip flop. But it still suffers from the "race" problem. This
problem occurs when the state of the output Q is changed before the clock input's timing pulse has time
to go "Off". We have to keep short timing plus period (T) for avoiding this period.

Circuit diagram of JK Flip flop:

Truth Table of JK Flip Flop :

J K Q(n+1)
0 0 Qn No change
58
0 | P 1a g e 0
1 0 1
1 1 Q'n
 Reset
Set
Complement of Previous state

Characteristic Table of JK Flip Flop:

J K Qn Qn+1
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0

Characteristic Equation of JK Flip Flop:

 The characteristic equation tells us about what will be the next state of flip flop in terms of present
state.
 In order to get the characteristic equation, K-Map is constructed which will be shown as below:

 Qn+1 = JQ'n + K'Qn

Excitation Table of JK Flip Flop :

In electronics design, an excitation table shows the minimum inputs that are necessary to generate
a particular next state (in other words, to “excite” it to the next state) when the current state is known.
They are similar to truth tables and state tables, but rearrange the data so that the current state and next
state are next to each other on the left-hand side of the table, and the inputs needed to make that state
change happen are shown on the right side of the table.

Qn Qn+1 J K
0 0 0 X
0 1 1 X
1 0 X 1

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 1 1 X 0

NOTE --- JK Flip Flop is Universal Flip Flop

J K Q(n+1)
SR Flip Flop 0 0 Qn
D Flip Flop T Flip Flop
0 1 0
1 0 1
1 1 Q'n

Advantages of JK Flip-Flop

 Versatility: As discussed above, JK-flipflops can be used as a basic memory element or a

primary building block of further complex memory design. It is very much adaptive as it can be
operated in both synchronous and asynchronous modes.
 Toggle Functionality: The application which are required to get output as its complement of
input that also can be developed by JK-flipflops as when J=K=1 it triggers toggle state which
gives output which is complement with it’s each clock pulse.
 Error Detection and Correction: We can use a complex circuit built by JK-flipflops which can
detect and correct information during data-transmission.

Disadvantages of JK Flip-Flop

 Complexity: Compared to other types of flipflops(D,T, SR), JK flipflop requires additional logic
gates to implement which consumes extra memory resources and increases complexity to operate.
 Propagation Delay: This is the major problem present in JK-FF. Propagation delay results a
timing delay in certain application which are time-flow sensitive.
 Race Problem: This issue arises when the clock input’s timing pulse isn’t given enough time to
turn “Off” before the output Q’s state is altered.

D Flip Flop :

D flip flop is a widely used flip flop in digital systems. The D flip flop is mostly used in shift-
registers, counters, and input synchronization. It is called transparent latch because Input = Output.
The D flip flop is the most important flip flop from other clocked types. It ensures that at the same
time, both the inputs, i.e., S and R, are never equal to 1. The Delay flip-flop is designed using a gated SR
flip-flop with an inverter connected between the inputs allowing for a single input D(Data).
This single data input, which is labeled as "D" used in place of the "Set" input and for the
complementary "Reset" input, the inverter is used. Thus, the level-sensitive D-type or D flip flop is
constructed from a level-sensitive SR flip flop.
Block Diagram :

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 D flip flops are synchronous or asynchronous. The clock single required for the synchronous version
of D flip flops but not for the asynchronous one.The D flip flop has two inputs, data and clock input
which controls the flip flop. when clock input is high, the data is transferred to the output of the flip flop
and when the clock input is low, the output of the flip flop is held in its previous state.

Circuit diagram of D Flip Flop :

Truth Table of D Flip Flop:

D Qn+1
0 0
1 1

Working of D Flip Flop:

D flip flop consist of a single input D and two outputs (Q and Q’). The basic working of D Flip Flop
is as follows:
 When the clock signal is low, the flip flop holds its current state and ignores the D input.
 When the clock signal is high, the flip flop samples and stores D input.
 The value that was previously fed into the D input is reflected at the flip flop’s Q output.
 If D = 0 then Q will be 0.
 If D = 1 then Q will be 1.
 The Q’ output of the flip flop is complemented by the Q output.
 If Q = 0 then Q’ will be 1.
 If Q = 1 then Q’ will be 0.

Characteristic Table of D Flip Flop:

D Qn Qn+1
0 0 0
0 1 0
1 0 1
1 1 1

Characteristic Equation of D Flip Flop:

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 Excitation Table of D Flip Flop:

Qn Qn+1 D
0 0 0
0 1 1
1 0 0
1 1 1

Advantages of D Flip Flop

 D flip flop is very simple to design.

 The computation speed of D flip flop is very fast compared to other flip flops.
 D flip flop requires very few components to design which makes it simple to understand.

Disadvantages of D Flip Flop

 D flip flops are glitch prone. When input varies fast, flip flop output may glitch. Digital circuit
glitches are hard to identify and fix.

Types of D Flip Flop

 D Latch.
 EdgeTriggered D Flip Flop.

Application of D Flip Flop

D flip flop is having numerous number of application in digital system is described as follows:
 Memory: D flip flop is used to create memory circuit for holding the data.
 Registers: D flip flop is used to create register, which can hold data in digital system. By using
the D flip flop the designer can built any size of register as per the requirement.
 Counters: D flip flops are used to create the counters which counts the number of event occurred
in the digital system.
 Synchronous System: D flip flop is having in developing the synchronous system.

T Flip Flop :
The T flip flop is also known as Toggle flip-flop. These T flip-flops are able to find the complement
of its state.
In T flip flop, "T" defines the term "Toggle". In SR Flip Flop, we provide only a single input called
"Toggle" or "Trigger" input to avoid an intermediate state occurrence. Now, this flip-flop work as a
Toggle switch. The next output state is changed with the complement of the present state output. This
process is known as "Toggling"'.
We can construct the "T Flip Flop" by making changes in the "JK Flip Flop". The "T Flip Flop" has
only one input, which is constructed by connecting the input of JK flip flop. This single input is called T.

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In simple words, we can construct the "T Flip Flop" by converting a "JK Flip Flop". Sometimes the "T
Flip Flop" is referred to as single input "JK Flip Flop".

Block diagram :

Circuit diagram of T flip flop:

Truth Table of T Flip flop :

T Qn+1
0 Qn No Change
1 Q'n Toggle

Working of T Flip Flop

Case 1: Let’s say, T = 0 and clock pulse is high i.e, 1, then output of both, AND gate 1, AND gate 2
will be 0, gate 3 output will be Q and similarly gate 4 output will be Q’ so both the values of Q and Q’
are same as their previous value, which means Hold state.

Case 2: Let’s say, T=1, then output of both AND gate 1 will be (T * clock * Q), and since T and
clock both are 1, then the output of AND gate 1 will be Q, and similarly output of AND gate 2 will be (T
* clock * Q’) i.e, Q’. Now, gate 3 output will be (Q’+Q)’ and let’s say Q’ is zero, then gate 3 output will
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be (0+Q)’ which means Q’ and similarly gate 4 output will be (Q+Q’)’ and since Q’ is zero, so gate 4
output will be Q’ which means 0 as Q’ is zero. Hence in this case we can say that the output toggles,
because T=1.

Characteristic table of T Flip flop :

T Qn Qn+1
0 0 0
0 1 1
1 0 1
1 1 0

Characteristic equation of T Flip flop:

 Qn+1 = TQ'n + T'Qn or Qn+1 = T Exor Qn

Excitation table of T Flip flop:

Qn Qn+ T
1
0 0 0
0 1 1
1 0 1
1 1 0

Applications of T Flip Flop

There are numerous applications of T Flip Flop in Digital System, which are listed below:
 Counters: T Flip Flops used in counters. Counters counts the number of events that occurs in a
digital system.
 Data Storage: T Flip Flops used to create memory which are used to store data, when the power
is turned off.
 Synchronous logic circuits: T flip-flops can be used to implement synchronous logic circuits,
which are circuits that perform operations on binary data based on a clock signal. By
synchronizing the logic circuit’s operations to the clock signal using T flip-flops, the circuit’s
behavior can be made predictable and reliable.
 Frequency division: It is used to divide the frequency of a clock signal by 2. Flip-flop will toggle
its output every time the clock signal transitions from high to low or low to high, hence dividing
the clock frequency by 2.
 Shift registers: T flip-flops can be used in shift registers which are used to shift binary data in
one direction.

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Combined Excitation Table of Flip Flops :

Qn Qn+1 S R J K D T

0 0 0 X 0 X 0 0

0 1 1 0 1 X 1 1

1 0 0 1 X 1 0 1

1 1 X 0 X 0 1 0

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