1 Digital VLSI Design

Introduction

 Compiled By: Jayanta Kumar Panigrahi

 Department of Electrical Engineering
 Govt. College of Engineering, Kalahandi, Bhawanipatna

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2 About Course

 Books:
 CMOS Digital Integrated circuits – Analysis and Design
by Sung – Mo Kang, Yusuf Leblebici, TATA McGraw-Hill
Pub. Company Ltd.
 Principles of CMOS VLSI Design – a System Perspective,
K. Eshraghian and N.H.E..Weste , Addison Wesley, 2nd
Edition 1993 .
 VLSI Design by Debaprasad Das, Oxford University
Press 2010

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3 Outlines

 About Course
 Brief History and Introduction
 Overview of VLSI design methodology,
 VLSI design flow
 Design hierarchy
 Concept of regularity, Modularity, and Locality
 VLSI design style
 Design quality
 package technology
 introduction to FPGA and CPLD
 computer aided design technology

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4 Brief History and Introduction

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5 Integrated Circuits

Less area
Low power consumption
Higher speed
Low cost
Reliability

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The First Computer

The Babbage
Difference Engine
(1832)
25,000 parts
cost: £17,470
ENIAC - The first electronic computer (1946)
8

Fig.1.1.Invention of transistor by John Bardeen, William

shockely and Walter (1947) at Bell Lab 23rd Dec
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First Integrated Circuit
1 Transistor and 4 other devices on 1 chip
First Commercial Planar IC
Fairchild – One Binary Digital (Bit) Memory Device on
Chip.
4 Transistors and 5 Resistors
 First IC created with Computer Aided Design
Tools -1967
First 1024 Bit Memory Chip --1970
Intel 4004 : 2.3k Transistors,1971
Pentium : 3.1 Million Transistors (1993)
Pentium II: 7.5 Million Transistors (1997)
 Pentium III : 28.1 Million Transistors
(1999)
Pentium IV : 52 Million Transistors (2001)
 Core 2 Duo: 291 Million Transistors
(2006)
 NVIDIA Graphics Processing Unit : 1.4
Billion
Intel’s Tukwila: 2 Billion Transistors
21

 VLSI is possible because of shrinking feature size day

by day.
 Technological advancement is the key to VLSI
 Advances in CAD tool
 Advances in Fabrication technology(Foundry)

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22

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23

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27 Brief History and Introduction

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Design Abstraction Levels
SYSTEM

MODULE
+

GATE

CIRCUIT

DEVICE
G
S D
n+ n+
29 Overview of VLSI design
methodology
 Higher the growth in VLSI technology needs some
structured design methodology for economically
viable VLSI products, in timely manner.
 Logic chips(microprocessors) have more complex
design compare to memory chips. The complexity is
also increased exponentially for logic chips.
 This increase in design cycle time of chips.
 This time is strongly dependent on the efficiency of the
design methodologies as well as on design style.
 As shown in upcoming figure, two different design
styles are compared for their relative merits and
demerits.

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30

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31 Overview of VLSI design
methodology
 Full custom design style( where the geometry and the
placement of every transistor can be optimized
individually) requires a longer time until design maturity
can be reached. But the final product have the higher
level of performance.
 In semicustom design style (standard cell based or
FPGA) will allow a shorter design time until design
maturity can be achieved.
 The choice of design style depends on performance
requirements of the VLSI product.

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32 Overview of VLSI design
methodology

GCE Kalahandi Impact of different design styles upon the design cycle time 8/28/2024
33 Overview of VLSI design
methodology
 Approximately every two years, a new generation of
Technology is introduced.
 This may require that the level of logic integration and
chip performance fall short of the level achievable
with the current processing technology.(see
upcoming figure)
 It can be seen that the design cycle time of a
successful VLSI product is kept shorter than what
would be necessary for developing an optimum
performance.
 The use of CAD tools methodologies are also essential
for reducing the design cycle time for managing the
increasing design complexity.

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34 Overview of VLSI design
methodology

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Progressive performance improvement of a VLSI product for each new generation technology
35 VLSI design flow

 The Y-chart (first introduced by D. Gajski) shown in Fig.

1.4 illustrates a design flow for most logic chips, using
design activities on three different axes (domains)
which resemble the letter Y.

 The Y-chart consists of three major domains, namely:

1. behavioral domain,
2. structural domain,
3. geometrical layout domain.

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36 VLSI design flow

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37 VLSI design flow

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38 Behavioral representation
Example

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39

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41 Structural Representation

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42 Structural Representation

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43 Structural Representation

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44 VLSI design flow

Figure-1.4: Typical VLSI design flow in three domains (Y-chart represen

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45 VLSI design flow

 The design flow starts from the algorithm that describes

the behavior of the target chip.
 The corresponding architecture of the processor is first
defined.
 It is mapped onto the chip surface by floorplanning.
 The next design evolution in the behavioral domain
defines finite state machines (FSMs) which are
implemented with functional modules such as registers
and arithmetic logic units (ALUs).
 These modules are then geometrically placed onto the
chip surface using CAD tools for automatic module
placement followed by routing, with a goal of minimizing
the interconnects area and signal delays.

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46 VLSI design flow

 The third evolution starts with a behavioral module

description.
 Individual modules are then implemented with leaf
cells. At this stage the chip is described in terms of
logic gates (leaf cells), which can be placed and
interconnected by using a cell placement & routing
program.
 The last evolution involves a detailed Boolean
description of leaf cells followed by a transistor level
implementation of leaf cells and mask generation.
 In standard-cell based design, leaf cells are already
pre-designed and stored in a library for logic design
use.

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47 VLSI design flow

 Figure 1.5 provides a more simplified view of the VLSI

design flow, taking into account the various
representations, or abstractions of design - behavioral,
logic, circuit and mask layout.
 Note that the verification of design plays a very
important role in every step during this process. The
failure to properly verify a design in its early phases
typically causes significant and expensive re-design at
a later stage, which ultimately increases the time-to-
market.

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48 VLSI design flow
Figure-1.5: A
more
simplified view
of VLSI design
flow.

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49 VLSI design flow

 Although the design process has been described in

linear fashion for simplicity, in reality there are many
iterations back and forth, especially between any two
neighboring steps, and occasionally even remotely
separated pairs.
 In the following, we will examine design
methodologies and structured approaches which
have been developed over the years to deal with
both complex hardware and software projects.
 Some of the classical techniques for reducing the
complexity of IC design are: Hierarchy, regularity,
modularity and locality.

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50 Design Hierarchy

 The use of hierarchy, or “divide and conquer”

technique involves dividing a module into sub-
modules and then repeating this operation on the sub-
modules until the complexity of the smaller parts
becomes manageable.
 This approach is very similar to the software case
where large programs are split into smaller and smaller
sections until simple subroutines, with well-defined
functions and interfaces, can be written.
 we have seen that the design of a VLSI chip can be
represented in three domains.

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51 Design Hierarchy

 Correspondingly, a hierarchy structure can be

described in each domain separately.
 As an example of structural hierarchy, Fig. 1.6 shows
the structural decomposition of a CMOS four-bit adder
into its components. The adder can be decomposed
progressively into one- bit adders, separate carry and
sum circuits, and finally, into individual logic gates.
 At this lower level of the hierarchy, the design of a
simple circuit realizing a well-defined Boolean function
is much more easier to handle than at the higher
levels of the hierarchy.

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 52 Design Hierarchy

Figure-1.6: Structural decomposition of a four-bit adder circuit, showing the hierarc

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53 Design Hierarchy

 In the physical domain, partitioning a complex system

into its various functional blocks will provide a valuable
guidance for the actual realization of these blocks on
chip.
 Obviously, the approximate shape and size (area) of
each sub-module should be estimated in order to provide
a useful floorplan. Figure 1.7 shows the hierarchical
decomposition of a four-bit adder in physical description
(geometrical layout) domain, resulting in a simple
floorplan.
 This physical view describes the external geometry of the
adder, the locations of input and output pins, and how
pin locations allow some signals (in this case the carry
signals) to be transferred from one sub-block to the other
without external routing.

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55 Design Hierarchy

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56 Concept of regularity,
Modularity, and Locality
 Regularity

 Modularity

 Locality

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57 Concept of regularity,
Modularity, and Locality
 The hierarchical design approach reduces the design
complexity by dividing the large system into several sub-
modules.
 Regularity means that the hierarchical decomposition of
a large system should result in not only simple, but also
similar blocks, as much as possible.
 A good example of regularity is the design of array
structures consisting of identical cells - such as a parallel
multiplication array.
 Regularity can exist at all levels of abstraction: At the
transistor level, uniformly sized transistors simplify the
design. At the logic level, identical gate structures can be
used, etc.

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59 Concept of regularity,
Modularity, and Locality
Figure-
1.11: Regular
design of a 2-1
MUX, a DFF
and an adder,
using inverters
and tri-state
buffers.

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60 Concept of regularity,
Modularity, and Locality
 Modularity in design means that the various functional
blocks which make up the larger system must have
well-defined functions and interfaces.
 Modularity allows that each block or module can be
designed relatively independently from each other,
since there is no ambiguity about the function and the
signal interface of these blocks.
 All of the blocks can be combined with ease at the
end of the design process, to form the large system.

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61 Concept of regularity,
Modularity, and Locality
 The concept of modularity enables the parallelization
of the design process. It also allows the use of generic
modules in various designs - the well-defined
functionality and signal interface allow plug-and-play
design.
 By defining well-characterized interfaces for each
module in the system, we effectively ensure that the
internals of each module become unimportant to the
exterior modules.
 Internal details remain at the local level. The concept
of locality also ensures that connections are mostly
between neighboring modules, avoiding long-
distance connections as much as possible.

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62 Concept of regularity,
Modularity, and Locality
 This last point is extremely important for avoiding
excessive interconnect delays. Time-critical operations
should be performed locally, without the need to
access distant modules or signals. If necessary, the
replication of some logic may solve this problem in
large system architectures.

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63 Field Programmable Gate
Array (FPGA)

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64

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65

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80

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124 Gate Array

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5 Gate Array

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6 Gate Array manufacturing

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7 Gate Array..

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8 Standard Cell-based Design

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9 Standard Cell-based Design

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13
0 Example..

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1 Full-Custom design

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2 Full-Custom design ..

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3 A full-custom layout

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13
4 Comparison of different
design styles

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5 MOS Transistor

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6 MOSFET as Switch

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7 MOSFET Structure

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8 MOSFET..

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9 Threshold Voltage

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0 MOS Capacitor

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1 MOS Capacitor under
different bias

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2 MOS C-V Characteristics

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3
Energy band diagram of
components that make up MOS

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4 Energy band diagram of
combined MOS structure

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5 Band diagram of MOS in
Inversion condition

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6

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7 MOS FET operating in
different regions

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8 Threshold Voltage of MOSFET

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9 Threshold Voltage ..

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15
0 Threshold Voltage ..

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1 Threshold Voltage ..

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3 MOSFET Current Equation

Assumption
 Gradual Channel Approximation
 Charge Sheet model
 Boundary Conditions are

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4

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5

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6

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7

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15
8

 Calculate the width (W) of a MOSFET with length (L) = 1.25μm,

mobility of electron (μn) = 650cm2/V s, oxide capacitance (COX) =
6.9 × 10-8 F/cm2, threshold voltage (Vt) = 0.65 V for a saturated
current of 4 mA to flow for applied VGS = 5 V?

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15
9

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0 Scaling Definition

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1

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2

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3

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4

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5

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6

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7

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8
Advantage

Disadvantage

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9

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0

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1

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2

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3

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4

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5 Short Channel MOSFET

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6 Short Channel Effects

Velocity Saturation

Threshold voltage reduction

Channel Length Modulation

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 Velocity Saturation
Velocity saturation limits IDsat in sub-micron MOSFETS

v =  for  <  sat

v = vsat for   sat

Esat is the electric field at velocity saturation:

𝐼𝑑𝑠𝑎𝑡 = 𝑄. 𝑊. 𝑣𝑠𝑎𝑡
17
8

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 Qualitative Explanation of SCE
on Threshold voltage
 Before an inversion layer forms beneath the gate,
the surface of the Si underneath the gate must be
depleted.
 The source & drain pn junctions assist in depleting
the Si underneath the gate
 Portions of the depletion charge in the channel region are
balanced by charge in S/D regions, rather than by charge
on the gate
 Less gate charge is required to invert the semiconductor
surface (i.e. |VT| decreases)
The smaller L is, the greater the percentage
of depletion charge balanced by the S/D pn
junctions:
depletion
charge
supported VG
by gate
(simplified
n+ n+ rj
analysis)

p depletion region

Large L: Small L:
S D S D

Depletion Depletion
charge charge
supported by supported by
S/D S/D
18
1

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2 Channel Length Modulation

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3

λ = Channel Length Modulation coefficient

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4 Channel Length Modulation

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5 MOS parasitic capacitances

Oxide-related capacitances
Junction capacitances

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6 MOS Oxide Capacitances

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7 Overlap Capacitance

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8
Approximate oxide
capacitance in different regions

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9

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19
0 Computer Aided Design
Technology
 CAD tools are essential for timely development of
integrated circuits.
 Although CAD tools can not replace the creative and
inventive parts of the design activities, the majority of
time consuming and computation intensive
mechanistic parts of the design can be executed by
using CAD tools.
 The CAD technology can be categorized into the
following area:
 High level synthesis
 Logic synthesis

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19
1 Computer Aided Design
Technology
 Circuit optimization
 Layout
 Simulation
 Design rules checking
 Formal Verification

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19
2 Computer Aided Design
Technology
 Synthesis Tools
 The high level synthesis tools using hardware
description language(HDLs), such as VHDL or Verilog,
address the automation of the design phase in the top
level of the design hierarchy.
 Layout Tools
 The tools for circuit optimization are concerned with
transistor sizing for minimization of delays and with
process variations, noise, and reliability hazards. The
Layout CAD tools include floor planning, place and
route, and module generation.

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19
3 Computer Aided Design
Technology
 Simulation and Verification Tools.
 The simulation category, which is the most mature
area of VLSI CAD, includes many tools ranging from
circuit level simulation, timing level simulation, logic
level simulation, and behavioral simulation.

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19
4 Outcomes

 From this topic, we come to know about the VLSI

designing methods, the flow of design, the concept of
design and certain set of rules to get proper design of
VLSI chip manufacturing. We also come to know the
various packaging technologies for ICs and also
Computer aided tools which are essential for the VLSI
product design.

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19
5 VTC of inverter

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6 Noise margins

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7 Noise margin..

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8 CMOS Inverter

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19
9 Advantages

 Negligible steady state power dissipation

 As the drain currents Idn=0 when nmos is in cutoff and
Idp=0 when pmos is in cut off hence no direct path exist
in any condition.
 VTC exhibits VOH= VDD and VOL= 0V
 The drain current Idn =Idp=0; hence no voltage drop
across NMOS in ON condition, hence Vout=VOL=0V
 Similarly when PMOS is in ON condition.
 But, as Idp =0, no voltage drop across the PMOS hence
VOH=VDD.

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1

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2

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3

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4

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5

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6

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7 CMOS Inverter
Calculation of VIL ,VIH ,VTH

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8

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9

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0

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1

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2

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3

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4

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5

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6

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7

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8

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9 Example of CMOS Logic
style representation

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0

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1

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2

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3 XOR, XNOR using CMOS
Logic

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4 AOI, OAI gate using CMOS
logic

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5 OAI gate using CMOS logic

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6 OAI gate using Pseudo
nMOS logic

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7

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8 Two input MUX using
Transmission Gate

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9 CMOS TG implementation of
XOR gate

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0 Dynamic Power Dissipation

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1

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2

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3 Power-Delay-Product (PDP)

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4

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5

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6

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7 Back to back inverter VTC

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8 nMOS Pass Transistor

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9 Transfer of Logic “1” in Pass
Transistor

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0 Transfer of Logic “1” in Pass
Transistor

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1 Transfer of Logic “1” in Pass
Transistor

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2 Transfer of Logic “0” in Pass
Transistor

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3 Transfer of Logic “0” in Pass
Transistor

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4 Charge storage and Charge
Leakage in Pass Transistor

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5 Voltage Bootstraping

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6 Bootstraping ..

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7 NOR based SR Latch

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8 NOR based SR Latch using
CMOS logic

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9 NAND based SR Latch using
CMOS logic

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0 NAND based SR Latch

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1 CMOS implementation of D
Latch

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2 D Flip Flop using CMOS Logic

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3 Built-in Self Test (BIST)

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4 Static RAM using CMOS
logic

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5 Different types of faults in
chip

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6 References

 Book: CMOS Digital Integrated Circuit Design - Analysis

and Design by S.M. Kang and Y. Leblebici.
 PPT- Introduction to CMOS VLSI design by Shmuel and
D.Harris
 www.pldworld.org

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THANK YOU

GCE Kalahandi 8/28/2024