TPS65155

www.ti.com.cn ZHCS684 – JANUARY 2012

用于门阵列 (GOA) 面板的具有电平转换器的 LCD 偏置解决方案

查询样品: TPS65155

1特性 说明
• 3V 至 6V 输入电压范围 TPS65155 为 GOA 面板提供一个集成偏置和电平转换
• 具有 1 个 4A 开关电流限制的升压转换器 器。
• 升压转换器输出电压高达 18V
此器件集成了一个升压转换器以生成源驱动器电源电
• 升压转换器过压保护 压(VAVDD)，正负电荷泵控制器用于生成栅极驱动器打
• 可选开关频率 （640kHz 或者 1.2MHz） 开(ON) (VGH)和关闭(OFF) (VGL)电压，和一个安装在
• 可编程升压转换器软启动 单IC中的6通道电平转换器。 正电荷泵控制器支持温度
• 温度补偿正电荷泵控制器 补偿以在高温下减少VGH。
• 负电荷泵控制器
除了上述功能，TPS65155 还生成一个附加的低电平
• 4 + 2通道电平转换器
有效的XAO复位输出。
• XAO复位信号
• 热关断 加电期间的电源排序可由一个外部生成的启用信号控
• 40 引脚 5 × 5 mm 四侧无引脚扁平 (QFN) 封装 制。

应用范围 VIN
3.3 V AVDD Boost Converter
AVDD
9 V/300 mA

• 使用 GOA 技术的 LCD 显示器或者笔记本控制面

板 Positive Charge Pump Controller VGHM
With Temperature Compensation 24 V/20 mA

Negative Charge Pump Controller VGL

-6 V/20 mA

Reset Function XAO

4 4-phase level
4 shifter
4 + 2 Channel
2 Level Shifter
2 STVOUT
RESETOUT

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not English Data Sheet: SLVSB29
necessarily include testing of all parameters.
TPS65155
ZHCS684 – JANUARY 2012 www.ti.com.cn

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION (1)

TA ORDERING PACKAGE PACKAGE MARKING
–40°C to 85°C TPS65155RKPR 40-Pin 5×5 QFN TPS65155

(1) The device is supplied taped and reeled, with 3000 devices per reel.

ABSOLUTE MAXIMUM RATINGS

(1)
over operating free-air temperature range (unless otherwise noted)
VALUE UNIT
FBN, VREF, SCL, SDA, FBP, RESETIN, CLKIN1, CLKIN2, CLKIN3, CLKIN4, FBPH,
7
FREQ, COMP, FB, SS, VIN, DRVN, VDET, STVIN, RNTC, EN, XAO
AVDD, SW 20
Pin Voltage (2) V
DRVP, VGH 40
VGL –20
STVOUT, RESETOUT, CLKOUT1, CLKOUT2, CLKOUT3, CLKOUT4 –20 to 40
Human Body Model 2 kV
ESD Rating Machine Model 200 V
Charged Device Model 500 V
PD Continuous Power Dissipation See Thermal Table W
TA Ambient temperature –40 to 85 °C
TJ Junction temperature –40 to 150 °C
TSTG Storage temperature –65 to 150 °C
Lead temperature (soldering, 10 seconds) 300 °C

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) With respect to the AGND and LGND pins.

THERMAL INFORMATION
TPS65155
THERMAL METRIC (1) QFN UNITS
40 PINS
θJA Junction-to-ambient thermal resistance 36.1
θJC(top) Junction-to-case(top) thermal resistance 30.0
θJB Junction-to-board thermal resistance 10.5
°C/W
ψJT Junction-to-top characterization parameter 0.7
ψJB Junction-to-board characterization parameter 10.5
θJC(bottom) Junction-to-case(bottom) thermal resistance 4.6

(1) 有关传统和新的热度量的更多信息，请参阅 IC 封装热度量 应用报告 SPRA953。

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RECOMMENDED OPERATING CONDITIONS

MIN TYP MAX UNIT
VIN Input voltage range 3 5 6 V
VAVDD Boost converter output voltage range 7 (1) 18 V
VGH Level shifter positive supply voltage range 15 38 V
VGL Level shifter negative supply voltage range –3 –15 V
VDET Panel discharge threshold voltage 2 V
CREF VREF decoupling capacitance 10 100 220 nF
TA Operating ambient temperature –40 25 85 °C
TJ Operating junction temperature –40 85 125 °C

(1) Or VIN + 1 V, whichever is lower.

ELECTRICAL CHARACTERISTICS
VIN = 5 V; VAVDD = 13.6 V, VGH = 28 V, VGL1 = VGL2 = –10 V, TA = –40°C to 85°C; FREQ = high. Typical values are at 25°C
(unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
IIN VIN supply current Device not switching, VFB = VL+ 5% 0.75 mA
ISUP Positive supply current 0.04 mA
IGH Positive supply current STVIN = 0 V, RESETIN = 0 V, CLKIN1-CLKIN4 = 0 V 0.26 mA
IGL Negative supply current STVIN = 0 V, RESETIN = 0 V, CLKIN1-CLKIN4 = 0 V 0.035 mA
VUVLO UVLO threshold VIN rising 2.5 V
VHYS UVLO hysteresis VIN falling 0.25 V
VREF External reference voltage IL = 100 µA 1.215 1.24 1.265 V
IREF Reference voltage maximum output current VL = 1.24 V ± 2% 250 µA
CONTROL SIGNALS (EN, FREQ)
VIH High input voltage threshold EN, FREQ rising 2.0 V
VIL Low input voltage threshold EN, FREQ falling 0.5 V
RPULL-UP Pull-up resistor EN, FREQ 50 kΩ
RESET (XAO)
VOL Low level output voltage IXAO = 1 mA, sinking 0.5 V
IOH High level leakage current VXAO = 5 V 2 µA

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ELECTRICAL CHARACTERISTICS (continued)

VIN = 5 V; VAVDD = 13.6 V, VGH = 28 V, VGL1 = VGL2 = –10 V, TA = –40°C to 85°C; FREQ = high. Typical values are at 25°C
(unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BOOST CONVERTER (AVDD)
VAVDD Output voltage IAVDD = 0.5 A 7 18 (1) V
VOVP Overvoltage threshold VAVDD rising 18.0 19.0 20.0 V
VOVP(HYS) Overvoltage hysteresis VAVDD falling 0.3 V
VAVDD rising, during power-up 2.6
VSCP(AVDD) Short-circuit threshold voltage V
VFB falling, during normal operation 0.36
VFB rising 97 % of
VFB(PG) Power good threshold
VFB falling 91.7 VREF

OFF time 55
tSCP(AVDD) Short circuit timer ms
ON time 15
VFB Feedback regulation voltage 1.228 1.240 1.252 V
IFB Feedback input bias current VFB = 1.24 V –100 100 nA
gm Error amplifier transconductance 80 140 µA/V
rDS(ON) Switch ON resistance VIN = 5 V, ISW = ILIM 0.13 0.18 Ω
ILIM Switch current limit 4.0 4.8 5.6 A
ILK Switch leakage current EN = 0 V, VSW = 18.5 V 30 µA
ISS Soft-start capacitor charge current VSS = 1.24 V 4.4 µA
FREQ connected to VIN 900 1200 1500
fSW Oscillator frequency kHz
FREQ connected to 0V 470 640 790
Line regulation VIN = 4 V to 6 V, IAVDD = 0.5 A 0.01 %/V
Load regulation IAVDD = 0.1 A to 0.5 A 0.2 %/A
POSITIVE CHARGE PUMP CONTROLLER (VGH)
VDRVP Base drive voltage range With external pull-up resistor 40 V
Normal operation, sinking, VFBP = 1.575 V, VDRVP = 28 V 2.5 mA
IDRVP Base drive sink current
Short-circuit operation, sinking, VFBP = 0 V, VDRVP = 28 V 40 72 µA
Lower limit; VRNTC = 2 V, VFBPH = 1.75 V 1.663 1.75 1.838
VFBP Feedback regulation voltage Lower limit; VRNTC = 1.5 V, VFBPH = 1.75 V 1.425 1.50 1.575 V
Lower limit; VRNTC = 1.0 V, VFBPH = 1.75 V 1.178 1.24 1.302
VFBP rising, during power-up 124
VFBP(SCP) Short circuit threshold voltage mV
VFBP falling, during normal operation 340
VFBP rising 97.5 % of
VFBP(PG) Power good threshold
VFBP falling 92.5 VREF

tSCP(VGH) Short circuit timer Starts from boost converter power good 15 ms
IFBP FBP input bias current VRNTC = 1 V, VFBPH = 1.75 V, VFBP = 1.24 V –100 100 nA
IRNTC RNTC output current VRNTC = 1.5 V, matched to IFBPH; at TA = 25 °C 190 200 210 µA
IFBPH FBPH output current VFBPH = 1.75 V, trimnmed; at TA = 25 °C 195 200 205 µA
Load regulation IGH = 1 mA to 50 mA 0.05 %/mA

(1) Limited by overvoltage protection function.

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ELECTRICAL CHARACTERISTICS (continued)

VIN = 5 V; VAVDD = 13.6 V, VGH = 28 V, VGL1 = VGL2 = –10 V, TA = –40°C to 85°C; FREQ = high. Typical values are at 25°C
(unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
NEGATIVE CHARGE PUMP CONTROLLER (VGL)
IDRVN Base drive current Normal operation, sourcing, VFBN = 25 mV, VDRVN = 0.7V 2.5 mA
Short-circuit operation, sourcing, VFBN = 1.116 V,
200 300 480 µA
VDRVN = 0.7 V
VFBN Feedback regulation voltage IDRVN = 1 mA, sourcing –15 15 mV
IFBN FBN input bias current VFBN = 0 V –100 100 nA
VFBN falling, during start-up 794
VFBN(SCP) Short circuit threshold voltage mV
VFBN rising, during normal operation 817
VFBN falling 2.8 % of
VFBN(PG) Power good threshold
VFBN rising 7.5 VREF

tSCP(VGL) Short circuit timer Starts from boost converter power good 15 ms
Load regulation IGL1 = 1 mA to 50 mA 0.05 %/mA
LEVEL SHIFTERS (CLK1 to CLK4)
VUVLO UVLO threshold VGH rising. 5.0 7.5 10.0 V
VIH Level shifter high level input threshold VCLKINx rising 1.5 V
VIL Level shifter low level input threshold VCLKINx falling 0.5 V
High side ON resistance ICLKOUTx = 10 mA, sourcing 14
rDS(ON) Ω
Low side ON resistance ICLKOUTx = 10 mA, sinking 8
LEVEL SHIFTERS (STV, RESET)
VIH Level shifter high level input threshold VSTVIN, VRESETIN rising 1.5 V
VIL Level shifter low level input threshold VSTVIN, VRESETIN falling 0.5 V
High side ON resistance ISTVOUT, IRESETOUT = 10 mA, sourcing 35
rDS(ON) Ω
Low side ON resistance ISTVOUT, IRESETOUT = 10 mA, sinking 15
I2C INTERFACE
Bus address 4Fh
VIL Low level input voltage VIN = 4 V to 6 V 0.7 V
VIH High level input voltage VIN = 4 V to 6 V 1.5 V
VOL Low level output voltage Sinking 3 mA 0.4 V
THERMAL SHUTDOWN
TSD Thermal shutdown threshold 138 °C
THYS Thermal shutdown hysteresis 8 °C

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DEVICE INFORMATION

PIN ASSIGNMENT

CLKIN1
DRVN
RNTC
DRVP
FBPH

VREF

VGH
FBN
FBP

VGL
35

34

33

32

31
40

39

38

37

36
COMP 1 30 CLKIN 2
AGND 2 29 ClKIN 3
SS 3 28 CLKIN 4
NC 4 27 STVIN
FB 5 26 RESETIN
ePAD
PGND 6 25 NC
SW 7 24 RESETOUT
FREQ 8 23 STVOUT
VIN 9 22 CLKOUT 4
XAO 10 21 CLKOUT 3
11

12

13

14

15

16

17

18

19

20
EN

GND
AVDD
GND

CLKOUT1
CLKOUT2
LGND
SCL
SDA
VDET

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PIN FUNCTIONS
PIN
I/O DESCRIPTION
NAME NO.
COMP 1 I Boost converter compensation
AGND 2 P Analog ground
SS 3 I Boost converter soft-start capacitor connection
NC 4 O No connection. Leave the pin floating
FB 5 I Boost converter feedback
PGND 6 P Power ground
SW 7 P Boost converter switch node
FREQ 8 I Boost converter frequency select
VIN 9 P Supply voltage
/XAO 10 O Reset
EN 11 I Device enable
VDET 12 I Panel discharge input
GND 13 I Ground
AVDD 14 P High voltage analog supply
GND 15 I Ground
SCL 16 I/O I2C interface clock
SDA 17 I/O I2C interface data
LGND 18 P Level shifter ground connection
CLKOUT1 19 O Level shifter input
CLKOUT2 20 O Level shifter input
CLKOUT3 21 O Level shifter input
CLKOUT4 22 O Level shifter input
STVOUT 23 O Level shifter input
RESETOUT 24 O Level shifter input
NC 25 No connection. Leave this pin floating.
RESETIN 26 I Level shifter input
STVIN 27 I Level shifter input
CLKIN4 28 I Level shifter input
CLKIN3 29 I Level shifter input
CLKIN2 30 I Level shifter input
CLKIN1 31 I Level shifter input
VGH 32 P Level shifter positive supply
VGL 33 P Level shifter negative supply
FBN 34 I Negative charge pump regulator feedback
VREF 35 O Internal voltage reference
DRVN 36 O Negative charge pump regulator drive signal (connects to base of external NPN transistor)
FBP 37 I Positive charge pump regulator feedback
DRVP 38 O Positive charge pump regulator drive signal (connects to base of external PNP transistor)
RNTC 39 I Positive charge pump LDO thermistor connection
FBPH 40 I Positive charge pump LDO temperature-setting resistor connection
ePAD P Exposed pad. Connect to the system GND

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TYPICAL CHARACTERISTICS

TABLE OF GRAPHS
FIGURE
BOOST CONVERTER
VIN = 5 V, VAVDD = 13.6 V, IAVDD = 0 A to 1 A Figure 1
Efficiency
VIN = 5 V, VAVDD = 18 V, IAVDD = 0 A to 1 A Figure 2
vs Load current VIN = 5 V, VAVDD = 13.6 V, IAVDD = 0 A to 0.8 A Figure 3
Frequency
vs Supply voltage VIN = 3.5 V to 6.0 V, VAVDD = 13.6 V, IAVDD = 0.5 A Figure 4
Undervoltage
fSW=1.2MHz, L=4.7µH VIN = 5 V, VAVDD = 13.6 V (10 V transient) Figure 5
Protection
Load Transient fSW=640kHz, L=10µH VIN = 5 V, VAVDD = 13.6 V, IAVDD = 250 mA/750 mA step Figure 6
Response fSW=1.2MHz, L=4.7µH Figure 7
Soft-start CSS=22nF VIN = 5 V, VAVDD = 13.6 V, IAVDD = 0.5 A Figure 8
Overvoltage
Duration = 75 ms Figure 9
Protection
Short-Circuit Duration = 75 ms VIN = 5 V, VAVDD = 13.6 V, IAVDD = 0.5 A Figure 10
Protection Duration = 25 ms VIN = 5 V, VAVDD = 13.6 V, IAVDD = 0.5 A Figure 11
Switch Node CCM operation VIN = 5 V, VAVDD = 13.6 V, IAVDD = 0.5 A Figure 12
Waveform DCM operation VIN = 5 V, VAVDD = 13.6V, IAVDD = 0.1A Figure 13
POSITIVE CHARGE PUMP
Load Transient fSW = 640kHz, L = 10µH VIN = 5V, VAVDD = 13.6V, IAVDD = 0.5A VGH = 28V, Figure 14
Response fSW = 1.2MHz, L = 4.7µH IGH = 10 mA/50 mA step Figure 15
VIN = 4 V to 6 V, VAVDD = 13.6 V, IAVDD = 0.5A,
Temperature
VGH(COLD) = 28 V, VGH(HOT) = 24 V, TCOLD = -10°C, Figure 16
Compensation
THOT = 10°C, IGH = 25 mA
NEGATIVE CHARGE PUMP
Load Transient fSW = 640kHz, L = 10µH VIN = 5 V, VAVDD = 13.6 V, IAVDD = 0.5 A, VGL = –10 V, Figure 17
Response fSW = 1.2MHz, L = 4.7µH IGL = 10 mA/50 mA step Figure 18
START-UP SEQUENCING
Power-Up Sequence VIN, VAVDD, VGH, VGL VIN = 5V, VAVDD = 13.6 V, VGH = 28 V, VGL = –10 V Figure 19
VIN, CLKOUTx, STVOUT,
Power-Up Sequence VIN = 5V, VAVDD = 13.6 V, VGH = 28 V, VGL = –10 V Figure 20
RESETOUT
Power-Down VIN, CLKOUTx, STVOUT,
VIN = 5V, VAVDD = 13.6 V, VGH = 28 V, VGL = –10 V Figure 21
Sequence RESETOUT
LEVEL SHIFTERS
CLKOUTx Figure 22
Peak Output Current VGH = 28V, VGL = –10V, 10 nF load
STVOUT, RESETOUT Figure 23
CLKOUTx Figure 24
Rise Time VGH = 28 V, VGL = –10 V, 47Ω + 10 nF load
STVOUT, RESETOUT Figure 25
CLKOUTx Figure 26
Fall Time VGH = 28 V, VGL = –10 V, 47Ω + 10 nF load
STVOUT, RESETOUT Figure 27

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BOOST CONVERTER EFFICIENCY (VAVDD = 13.6 V) BOOST CONVERTER EFFICIENCY (VAVDD = 18 V)

100 100
FREQ = Low FREQ = Low
90 90

80 80
FREQ = High
70 70
FREQ = High
Efficiency – %

Efficiency – %
60 60

50 50
40 40

30 30

20 20
10 10

0 0
0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.2 0.4 0.6 0.8 1.0
IAVDD – Output Voltage Current – A IAVDD – Output Voltage Current – A

Figure 1. Figure 2.

BOOST CONVERTER FREQUENCY vs. LOAD CURRENT BOOST CONVERTER FREQUENCY vs. SUPPLY VOLTAGE
1400 1400
FREQ = High FREQ = High
1200 1200
Boost Converter Frequency – kHz

Boost Switching Frequency – kHz

1000 1000

800 800
FREQ = Low FREQ = Low

600 600

400 400

200 200

0 0
0 100 200 300 400 500 600 700 800 3.5 4.0 4.5 5.0 5.5 6.0
Output Current – mA VIN – Input Voltage – V

Figure 3. Figure 4.

BOOST CONVERTER UNDERVOLTAGE PROTECTION BOOST CONVERTER LOAD TRANSIENT RESPONSE

AVDD
Converter Load

AVDD

Converter O/P

IAVDD

AVDD
fSW=640kHz, L=10µH

Figure 5. Figure 6.

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BOOST CONVERTER LOAD TRANSIENT RESPONSE BOOST CONVERTER SOFT-START

AVDD

AVDD

IIN
IAVDD

fSW=1.2MHz, L=4.7µH

Figure 7. Figure 8.

BOOST CONVERTER OVERVOLTAGE PROTECTION BOOST CONVERTER SHORT-CIRCUIT PROTECTION

AVDD
Short
Circuit
Duration AVDD

VSW
VGD

Figure 9. Figure 10.

BOOST CONVERTER SHORT-CIRCUIT PROTECTION BOOST CONVERTER SWITCH NODE WAVEFORM (CCM)

AVDD

VSW
VGD

IL

Figure 11. Figure 12.

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BOOST CONVERTER SWITCH NODE WAVEFORM (DCM) POSITIVE CHARGE PUMP LOAD TRANSIENT RESPONSE

VGH

VSW

IGH

IL fSW=640kHz, L=10µH

Figure 13. Figure 14.

POSITIVE CHARGE PUMP TEMPERATURE

POSITIVE CHARGE PUMP LOAD TRANSIENT RESPONSE COMPENSATION
28.5
VGH(HOT) = 28 V
28.0
VGH – Level Shifter Voltage Range – V
VGH(COLD) = 24 V
TCOLD = –10 °C
27.5
THOT = 10 °C
VGH
27.0

26.5

26.0

25.5

25.0

24.5
IGH
24.0

fSW=1.2MHz, L=4.7µH 23.5

-20 -15 -10 -5 0 5 10 15 20
Temperature – °C

Figure 15. Figure 16.

NEGATIVE CHARGE PUMP LOAD TRANSIENT RESPONSE NEGATIVE CHARGE PUMP LOAD TRANSIENT RESPONSE

VGL VGL

IGL IGL

fSW=640kHz, L=10µH fSW=1.2MHz, L=4.7µH

Figure 17. Figure 18.

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POWER-UP SEQUENCE #1 POWER-UP SEQUENCE #2

VIN VIN

AVDD VCLKOUTx

VGH

VSTVOUT

VRESETOUT
VGL

Figure 19. Figure 20.

POWER-DOWN SEQUENCE #1 PEAK OUTPUT CURRENT (CLKx)

VIN
544mA

VCLKOUTx

ICLKOUT1

VSTVOUT

VRESETOUT
564mA

Figure 21. Figure 22.

PEAK OUTPUT CURRENT (STVOUT, RESETOUT) RISE TIME (CLKOUTx)

258mA

ISTVOUT VCLKOUT1

302mA
Load=47Ω+10nF

Figure 23. Figure 24.

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RISE TIME (STVOUT, RESETOUT) FALL TIME (CLKOUTx)

VSTVOUT

VCLKOUT1

Load=47Ω+10nF Load=47Ω+10nF

Figure 25. Figure 26.

FALL TIME (STVOUT, RESETOUT)

VSTVOUT

Load=47Ω+10nF

Figure 27.

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DETAILED DESCRIPTION

An internal block diagram of the TPS65155 is shown in Figure 28.

SS COMP SW

EN
VAVDD +
Boost
VOVP - Converter PGND
FREQ
FB

+
DRVP
VPG - EN
+
VIN -

VIN + FBP
Internal
VUVLO - Bias
Temperature RNTC
AGND Compensation FBPH

XAO Buffer
VREF
VIN

-
+

DRVN

FBN
-
Discharge VDET
+
VGH VREF
STVIN STVOUT
RESETIN RESETOUT
CLKIN1 CLKOUT1
CLKIN2 Level CLKOUT2
CLKIN3 Shifter CLKOUT3
CLKIN4 CLKOUT4

LGND

VGL

EEPROM

SDA 2
IC LOGIC
SCL Interface

Note:
For clarity, duplicate pins not shown.

Figure 28. Internal Block Diagram

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Boost Converter
An internal block diagram of the boost converter is contained in Figure 29.
L1 D1
VIN VAVDD
C1 C2

EN VIN SW AVDD

VOVP

+
-
Bias
UVLO
Thermal SD

FREQ tOFF R1
Generator FB

SS Current Limit -
PWM R2
& Soft Start
+ Generator
C4

COMP + VREF
-
R4
PGND
C5 C3

Figure 29. Boost Converter Internal Block Diagram

The boost converter is designed for output voltages up to 18V with a switch current limit of 4 A (guaranteed
minimum). The converter uses a current mode, quasi-constant frequency topology, and is externally
compensated for maximum flexibility. A soft-start feature limits the current drawn from VIN during start-up, and
the converter's switching frequency can be selected between 640 kHz and 1.2 MHz.
The converter's adaptive off-time topology achieves superior transient response and operates over a wider range
of applications than conventional converters.

Design Procedure (Boost Converter)

The first step in the design procedure is to calculate the peak switch current. The simplest way to do this is to
use the curves in the typical characteristics section to estimate converter efficiency in the intended application.
Alternatively, a conservative worst-case value such as 85% can be used.
Once a value for the converter's efficiency η is available, Equation 1 can be used to calculate its duty cycle.
V ´ η
D = 1 - IN
VAVDD (1)
The next step is to use Equation 2 to calculate the change in inductor current per cycle.
V ´ D
ΔIL = IN
¦ ´ L (2)
Finally, the peak switch current can be calculated using Equation 3.
IA VDD ΔIL
IS W (P K) = +
1 - D 2 (3)

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The value for peak switch current calculated using Equation 3 must be lower than the minimum specified for the
device, and should be calculated under worst-case conditions (minimum VIN and maximum IAVDD).

Inductor Selection (Boost Converter)

The boost converter in the TPS65155 has been optimized for inductors in the range 3.3 µH to 6.8 µH when using
the higher switching frequency and in the range 7 µH to 13 µH when using the lower switching frequency.
The saturation current of the inductor must be greater than the peak switch current plus an additional margin to
allow for heavy load transients. A saturation current of 130% of the value calculated using Equation 3 is
adequate for most applications.
Table 1 shows a selection of inductors suitable for use with the TPS65155.

Table 1. Boost Converter Inductor Selection

INDUCTANCE MANUFACTURER PART NUMBER SIZE DCR ISAT
1.2 MHz OPERATION
4.7 µH Coiltronics UP2B-4R7-R 14.0 × 10.4 × 6.0 17 mΩ 5.5 A
4.7 µH Sumida CDRH12NP-4R7-M 12.3 × 12.3 × 4.5 18 mΩ 5.7 A
4.7 µH Sumida CDRH127 12.3 × 12.3 × 8.0 12 mΩ 6.8 A
640 kHz OPERATION
10 µH Coilcraft DS3316P 13.0 × 9.4 × 5.1 70 mΩ 3.5 A
10 µH Sumida CDRH8D43 8.3 × 8.3 × 4.5 29 mΩ 4.0 A
10 µH Sumida CDRH127 12.3 × 12.3 × 8.0 16 mΩ 5.4 A
10 µH Sumida CDRH127LD 12.3 × 12.3 × 8.0 15 mΩ 6.7 A

Rectifier Selection (Boost Converter)

A Schottky type is recommended for the boost converter rectifier diode because its low forward voltage improves
efficiency. The diode's reverse voltage rating must be greater than 20 V, which is the maximum it will experience
(the TPS65155's overvoltage protection function prevents this voltage being any higher). The diode's average
rectified current rating must be at least as high as the maximum IAVDD. A 2 A rating is sufficient for most
applications.
Equation 4 can be used to calculate the power dissipated in the diode. The diode must be capable of handling
this power without overheating. A power rating of 500 mW is sufficient for most applications.
P = VF ´ IAVDD (4)
Where:
VF is the diode's forward voltage
IAVDD is the average (mean) boost converter output current
Table 2 shows a selection of rectifier diodes suitable for use with the TPS65155.

Table 2. Boost Converter Rectifier Selection

CURRENT MANUFACTURER PART NUMBER SIZE VR VF
2A Vishay SL22 SMA 20 V 0.44 V at 2 A
2A Vishay SS22 SMA 20 V 0.5 V at 2 A

Input Capacitor Selection (Boost Converter)

For good supply voltage filtering, low ESR capacitors are recommended. The TPS65155 has an analog supply
voltage pin (VIN) that should be decoupled with a ceramic capacitor in the range 100 nF to 1 µF, connected
close to the VIN pin.
The main boost converter (i.e. where VIN is connected to the inductor of the boost converter) should also be
decoupled. Two 10 µF or one 22 µF ceramic capacitor are adequate for most applications, however, these
values can be increased if improved filtering is required.

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Setting the Output Voltage (Boost Converter)

The output voltage of the boost converter is set by a resistor divider connected to the FB pin. The boost
converter's main error amplifier compares the feedback voltage with the internal reference voltage VREF so that
the output is regulated at a voltage given by Equation 5.
æR ö
VAVDD = 1.24 × ç 1 + 1÷
è R2 ø (5)

Soft-Start (Boost Converter)

To reduce the inrush current drawn from VIN during start-up the boost converter includes a soft-start feature.
Soft-start is controlled by a capacitor connected to the soft-start (SS) pin. During soft-start, this capacitor is
charged up by a current source and the voltage across the capacitor determines the switch current limit: the
larger the capacitor, the slower the ramp of the switch current limit and therefore the longer the soft-start time.
The maximum switch current limit is achieved when the voltage connected to the boost converter's feedback pin
(FB) reaches its power good threshold (approximately 97 percent of its nominal value).
A 22 nF soft-start capacitor is suitable for most applications.
When the EN pin is pulled low, the soft-start capacitor is discharged.

Frequency Select (FREQ)

The frequency select (FREQ) pin can be used to set the nominal boost converter switching frequency to either
640 kHz (FREQ=low) or 1.2 MHz (FREQ=high). A higher switching frequency improves the load transient
response and output voltage ripple; a lower switching frequency usually improves efficiency.
A switching frequency of 1.2 MHz is recommended for most applications unless efficiency is the primary concern.
The FREQ pin features an internal pull-up resistor that ensures the higher switching frequency is used if the pin
is left floating.

Compensation (COMP)
The boost converter uses an external compensation network connected to its COMP pin to stabilize its feedback
loop. The COMP pin is connected to the output of the boost converter's transconductance error amplifier, and a
series resistor and capacitor connected between this pin and AGND is sufficient to achieve good performance in
most applications. The capacitor primarily influences low frequency gain and the resistor primarily influences high
frequency gain. Lower output voltages require higher loop gain and therefore a larger compensation capacitor.
Good starting values, which will work for most applications running from a 5 V supply voltage, are 47 kΩ and 3.3
nF.
In some applications (e.g. those using electrolytic output capacitors), it may be necessary to include a second
compensation capacitor between the COMP pin and AGND. This has the effect of adding an additional pole in
the feedback loop's frequency response, which can be used to cancel the zero introduced by the electrolytic
output capacitor's ESR. It is recommended to include a footprint on the PCB for this optional capacitor, even if it
is not used initially.

Overvoltage Protection (Boost Converter)

The boost converter contains an overvoltage protection (OVP) feature that limits its output voltage to a safe
maximum if the FB pin is floating or shorted to ground. Overvoltage conditions are detected when the voltage
applied to the AVDD pin (VAVDD) exceeds the overvoltage threshold (VOVP). As soon as this happens, the boost
converter switch is turned off. It remains off until VAVDD falls below VOVP (minus hysteresis), at which point the
boost converter automatically starts switching again.

NOTE
The AVDD pin must be connected to the boost converter output for the overvoltage
protection feature to operate correctly.

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Short-Circuit and Undervoltage Protection (Boost Converter)

During normal operation (i.e., once the boost converter has reached its power good threshold) a short circuit is
detected if the feedback voltage VFB falls below 30% of VREF. If this happens, the boost converter is disabled.
Either VIN or EN must be cycled to recover normal operation.

Undervoltage Lockout Protection (Boost Converter)

During operation, if the output of the boost converter falls below its power good threshold for longer than 55ms,
the TPS65155 will detect an undervoltage condition and turn itself off. VIN or EN must be cycled to recover
normal operation.

Positive Charge Pump

Figure 30 shows the internal block diagram of the positive charge pump.
The positive charge pump is driven directly from the boost converter's switch node and then post-regulated by an
external PNP transistor. The controller is optimized for transistors having a DC gain (hFE) in the range 100 to
300. The positive charge pump is temperature compensated so that its output voltage decreases at high
temperatures (see Figure 16).
SW

VAVDD

UVP (Normal)
+
1.15V* 55 ms
- Timer
VREF VREF
DRVP
Short
200µA

200µA

340mV* + SCP (Normal) Control Circuit

55µA
- Logic
VGH
124mV* + SCP (Start-Up)
- Normal
2.5 mA
+ R15
x1
-
Error
VREF
Clamp
Amplifier FBP
R16

RNTC FBPH

R11 R10

R12 RNTC

Figure 30. Positive Charge Pump Internal Block Diagram

Setting the Output Voltage (Positive Charge Pump)

The positive charge pump in the TPS65155 is temperature compensated such that its output voltage decreases
at high temperatures (see Figure 31). For a detailed description about how to set the output voltage see
Temperature Compensation section below.

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A current of the order of 1 mA through the feedback resistor network ensures good accuracy and increases the
circuit's immunity to noise. It also ensures a minimum load on the charge pump, which reduces output voltage
ripple under no-load conditions. A good approach is to assume a value of about 1.2 k for the lower resistor (R16)
and then select the upper resistor (R15) to set the desired output voltage.
Note that the maximum voltage in an application is determined by the boost converter's output voltage and the
voltage drop across the diodes and PNP transistor. For a typical application in which the positive charge pump is
configured as a voltage doubler, the maximum output voltage is given by Equation 6.
VGH(MAX) = (2 ´ VAVDD ) - (2 × VF ) - VCE
(6)
Where VAVDD is the output voltage of the boost converter, VF is the forward voltage of each diode and VCE is the
collector-emitter voltage of the PNP transistor (recommended to be at least 1 V, to avoid transistor saturation).

Selecting the PNP Transistor (Positive Charge Pump)

The PNP transistor used to regulate VGH should have a DC gain (hFE) of at least 100 when its collector current is
equal to the charge pump's output current. The transistor should also be able to withstand voltages up to VGH
across its collector-emitter junction (VCE).
The power dissipated in the transistor is given by Equation 7. The transistor must be able to dissipate this power
without its junction becoming too hot. Note that the ability to dissipate power depends heavily on adequate PCB
thermal design.
PQ = éë (2 ´ VAVDD ) - (2 ´ VF ) - VGH ùû ´ IGH
(7)
Where IGH is the mean (not RMS) output current drawn from the charge pump.
A pull-up resistor is also required between the transistor's base and emitter. The value of this resistor is not
critical, but it should be large enough not to divert significant current away from the base of the transistor. A
value of 100 kΩ is suitable for most applications.

Selecting the Diodes (Positive Charge Pump)

Small-signal diodes can be used for most low current applications (<50 mA) and higher rated diodes for higher
power applications. The average current through the diode is equal to the output current, so that the power
dissipated in the diode is given by Equation 8.
PD = IGH ´ VF (8)
The peak current through the diode occurs during start-up and for a few cycles may be as high as a few amps.
However, this condition typically lasts for <1 ms and can be tolerated by many diodes whose repetitive current
rating is much lower. The diodes' reverse voltage rating should be equal to two times VAVDD.

Table 3. Positive Charge Pump Diode Selection

PART NUMBER IAVG IPK VR VF COMPONENT SUPPLIER
BAV99W 150 mA 1 A for 1 ms 75 V 1 V at 50 mA NXP
BAT54S 200 mA 600 mA for 1s 30 V 0.8 V at 100 mA Fairchild Semiconductor
MBR0540 500 mA 5.5 A for 8 ms 40 V 0.51 at 500 mA Fairchild Semiconductor

Selecting the Capacitors (Positive Charge Pump)

For lowest output voltage ripple, low-ESR ceramic capacitors are recommended. The actual value is not critical
and values in the range 1 µF to 10 µF are suitable for most applications. Larger capacitors provide better
performance in applications where large load transient currents are present.
A flying capacitor in the range 100 nF to 1 µF is suitable for most applications. Larger values experience a
smaller voltage drop by the end of each switching cycle, and allow higher output voltages and/or currents to be
achieved. Smaller values tend to be physically smaller and a bit cheaper. For best performance, it is
recommended to include a resistor of a few ohms (2 Ω is a good value to start with) in series with the flying
capacitor to limit peak currents occurring at the instant of switching.

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Temperature Compensation (Positive Charge Pump)

The output voltage (VGH) of the positive charge pump controller is defined by two voltages and two temperatures,
as illustrated in Figure 31. The temperature compensation scheme is optimized for use with 10 kΩ NTC
thermistors.
Positive Charge Pump
Output Voltage

VGH(COLD)

VGH(HOT)

T1 T2 Temperature

Figure 31. Positive Charge Pump Temperature Compensation

The error amplifier's non-inverting input, which is the reference voltage for VGH, is derived from the FBPH and
RNTC pins. A higher reference voltage generates a higher VGH.
VGH(COLD) is determined by the resistor connected to the FBPH and FBP pins:
æ R ö
VGH(COLD) = IFBPH ´ R10 ´ ç 1 + 15 ÷
è R16 ø (9)
VGH(HOT) is set by an internal clamping circuit and the resistor divider connected to the FBP pin:
æ R ö
VGH(HOT) = VREF × ç1 + 15 ÷
è R16 ø
(10)
The NTC network connected to the RNTC pin defines the temperatures T1 and T2.

Temperature compensation can be disabled by connecting a 10 kΩ resistor between the FBPH pin and AGND
and by tying the RNTC pin directly to AGND, in which case Equation 10 should be used to calculate VGH.

Suppose a circuit with the following characteristics is required:

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Example

A Microsoft Excel spreadsheet is available that allows easy calculation of temperature compensation
components and eliminates the need for the following expressions to be calculated manually. Contact the
factory to receive a free copy.

Suppose a circuit with the following characteristics is required:

T1 = 40°C
T2 = 60°C
VGH(COLD) = 28 V
VGH(HOT) = 20 V
Space
1. The first step is to calculate the resistance of the NTC at temperatures T1 and T2
At temperature T1, RNTC(T1) = 5302 Ω
At temperature T2, RNTC(T2) = 2486 Ω
Space
2. The next step is to calculate the feedback resistors R15 and R16 as follows:
R15 VGH(HOT)
= -1
R16 VREF

R15 20V
= - 1 = 15.13 V
R16 1.24V (11)
Suitable standard values from the E96 series would be R15 = 19.6 kΩ and R16 = 1.3 kΩ. With these values,
the current through the feedback divider is of the order of 1mA and the nominal output voltage at high
temperatures is:
æR ö
VGH(HOT) = VREF ´ ç 15 + 1 ÷
è R16 ø

æ 19.6 kΩ ö
VGH(HOT) = 1.24 V ´ ç + 1÷ = 19.94 V
è 1.3 kΩ ø (12)
Space
3. Now calculate VFBPH as follows:
æ R16 ö
VFBPH = VGH(HOT) × ç ÷
è R15 + R16 ø

æ 1.3 kΩ ö
VFBPH = 28 V × ç ÷ = 1.742 V
è 19.6 kΩ + 1.3 kΩ ø (13)
Space
The value of R10 required to generate VFBPH can now be calculated, as follows:
V
R10 = FBPH
IFBPH

1.742 V
R10 = = 8.71 kΩ
200 μA (14)

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Two 17.4 kΩ resistors in parallel would be suitable for R10, giving an output voltage at low temperatures
given by:
æR ö
VGH(COLD) = IFBPH ´ R10 ´ ç 15 + 1÷
è R16 ø

17.4 kΩ æ 19.6 kΩ ö
VGH(COLD) = 200 μA ´ ´ ç + 1÷ = 28.0 V
2 è 1.3 kΩ ø (15)
Space
The value of R12 can be calculated by solving a standard quadratic equation:
-b ± b2 - 4 ´ a ´ c
R12 =
2 ´ a (16)
Where:

a=
ISET
VFBPH - VREF
(
´ RNTC(T1) - RNTC(T2) - 1 )
200 μA
a= ´ (5.30 kΩ - 2.49 kΩ ) - 1 = 0.124
1.74 V - 1.24 V
Space
b = RT1 + RT2
b = 5.30 kΩ + 2.49 kΩ = 7.79 kΩ
Space
c = RT1 ´ RT2
c = 5.30 kΩ ´ 2.49 kΩ = 13.2 ´ 10 6 Ω2
Space
Using the coefficients a, b, and c we can solve for R12:

7.79 kΩ + 7.79 kΩ 2 + 4 × 0.124 × 13.2 × 10 6Ω 2

R12 =
2 × 0.124
R12 = 64.5 kΩ

A standard value of 64.9 kΩ can be used for R12.

Space
4. The final step is to calculate the value of R11 using Equation 10.
VREF R T2 ´ R12
R11 = -
IRNTC R T2 + R12

1.24 V 2.49 kΩ × 64.9 kΩ

R11 = - = 3.8 kΩ
200 μA 2.49 kΩ + 64.9 kΩ (17)
A standard value of 3.83 kΩ can be used for R12.
Figure 32 shows the temperature dependence of VGH resulting from the above calculated values.

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www.ti.com.cn ZHCS684 – JANUARY 2012

30

28

26

24
VGH - V

22

20

18

16
0 10 20 30 40 50 60 70 80 90 100
Temperature - °C

Figure 32. Temperature Compensated VGH

Short-Circuit Protection (Positive Charge Pump)

During start-up, the positive charge pump limits the current available from VGH until VFBP > 124 mV. If VFBP is still
less than 124 mV after 15 ms, the boost converter, and positive and negative charge pumps are disabled. Either
VIN or EN must be cycled to recover normal operation.
During normal operation (i.e. once the positive charge pump has reached its power good threshold) short circuits
are detected if VFBP falls below 0.34 V (approx. 30% of VREF). If this happens the boost converter and positive
and negative charge pumps are disabled. Either VIN or EN must be cycled to recover normal operation.

Undervoltage Protection (Positive Charge Pump)

During operation, if the output of the positive charge pump falls below its power good threshold for longer than
55ms, the TPS65155 will detect an undervoltage condition and turn itself off. VIN or EN must be cycled to recover
normal operation.

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Negative Charge Pump Controller

The negative charge pump controller uses an external NPN transistor to regulate an external charge pump
circuit. The controller is optimized for transistors having a DC gain (hFE) in the range 100 to 300. Regulation of
the charge pump's output voltage is achieved by using the external transistor as a controlled current source
whose output current depends on the voltage applied to the FBN pin. The higher the transistor's output current,
the higher (i.e., more negative) the charge pump's output voltage.

UVP (Normal) VAVDD

-
93 mV 55 ms
+ Timer

Short-Circuit
- Mode
850 mV SCP (Normal) Control 300 μA
+ Logic

Normal
SW
794 mV - SCP (Start-Up) Mode
2.5 mA
+
R8
FBN
+
- Error C10
Amplifier D7 VGL

VREF DRVN D6 C11

Q2
C13
R22
R14

R13

Figure 33. Negative Charge Pump Internal Block Diagram

Setting the Output Voltage (Negative Charge Pump)

The negative charge pump's output voltage is programmed by a resistor divider according to Equation 18.
R
VGL = - VREF ´ 13
R14 (18)
Rearranging Equation 18, the values of R13 and R14 can be easily calculated.
VGL
R13 = R14 ´
VREF (19)
Because of its limited output current capability, it is recommended to keep the current drawn from the VREF pin
below 250 µA to achieve best accuracy. A good approach is to use a value of at least 5.1 kΩ for the lower
resistor (R14) and then select the upper resistor (R13) to set the desired output voltage. If a minimum charge
pump load is desired (e.g. to improve regulation at very low load currents), it is best to add an additional resistor
between VGL and GND, rather than reduce the values of R13 and R14.
Note that the maximum voltage in an application is determined by the boost converter's output voltage and the
voltage drop across the diodes and NPN transistor. For a typical application in which the negative charge pump
is configured as a voltage inverter, the maximum (i.e., most negative) output voltage is given by Equation 20.
VGL(MAX) = - VAVDD + (2 ´ VF ) + VCE
(20)
Where VF is the forward voltage of each diode and VCE is the collector-emitter voltage of the NPN transistor
(recommended to be at least 1 V, to avoid transistor saturation).

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Selecting the NPN Transistor (Negative Charge Pump)

The NPN transistor used to regulate VGL should have a DC gain (hFE) of at least 100 when its collector current is
equal to the charge pump's output current. The transistor should also be able to withstand voltages up to VAVDD
across its collector-emitter (VCE).
The power dissipated in the transistor is given by Equation 21. The transistor must be able to dissipate this
power without its junction becoming too hot. Note that the ability to dissipate power depends heavily on adequate
PCB thermal design.
PQ = éë V AVDD - (2 ´ VF ) - VGL ûù ´ IGL
(21)
Where IGL is the mean (not RMS) output current drawn from the charge pump.

Selecting the Diodes (Negative Charge Pump)

Small-signal diodes can be used for most low current applications (<50 mA) and higher rated diodes for higher
power applications. The average current through the diode is equal to the output current, so that the power
dissipated in the diode is given by Equation 22.
PD = IGL ´ VF (22)
The peak current through the diode occurs during start-up and for a few cycles may be as high as a few amps.
However, this condition typically lasts for <1 ms and can be tolerated by many diodes whose repetitive current
rating is much lower. The diodes' reverse voltage rating should be equal to at least 2×VAVDD.

Table 4. Negative Charge Pump Diode Selection

PART NUMBER IAVG IPK VR VF COMPONENT SUPPLIER
BAV99W 150 mA 1 A for 1 ms 75 V 1 V at 50 mA NXP
BAT54S 200 mA 600 mA for 1 s 30 V 0.8 V at 100 mA Fairchild Semiconductor
MBR0540 500 mA 5.5 A for 8 ms 40 V 0.51 at 500 mA Fairchild Semiconductor

Selecting the Capacitors (Negative Charge Pump)

For lowest output voltage ripple, low-ESR ceramic capacitors are recommended. The actual value is not critical
and 1 µF to 10 µF is suitable for most applications. Larger capacitors provide better performance in applications
where large load transient currents are present.
A flying capacitor in the range 100 nF to 1 µF is suitable for most applications. Larger values experience a
smaller voltage drop by the end of each switching cycle, and allow higher output voltages and/or currents to be
achieved. Smaller values tend to be physically smaller and a bit cheaper.
A collector capacitor in the range 100 nF to 1 µF is suitable for most applications. Larger values are more
suitable for high current applications but can affect stability if they are too big.

Short-Circuit Protection (Negative Charge Pump)

During start-up the negative charge pump limits the current available from VGL until VFBN is less than 794 mV. If
VFBN is still higher than 794 mV after ≈ 20 ms (1), the boost converter, and positive and negative charge pumps
are disabled. Either VIN or EN must be cycled to recover normal operation.
During normal operation (i.e., once the negative charge pump has reached its power good threshold), short
circuits are detected if VFBN rises above 850 mV. If this happens, the boost converter, and positive and negative
charge pumps are disabled. Either VIN or EN must be cycled to recover normal operation.

Undervoltage Protection (Negative Charge Pump)

During operation, if the output of the negative charge pump falls below its power good threshold for longer than
55ms, the TPS65155 will detect an undervoltage condition and turn itself off. VIN or EN must be cycled to recover
normal operation.

(1) Actually 10ms after the boost converter's power good.

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Reset Generator (XAO)

The TPS65155 generates an open-drain reset signal that can be used to disable the T-CON during power-down.
The XAOsignal is pulled low when VDET < VREF and is high impedance when VDET > VREF (+ hysteresis). The
reset generator is not disabled when VIN falls below the UVLO threshold, and continues to function down to very
low values of VIN.

I2C Interface
The TPS65155 has an I2C serial interface for internal test purpose. Both the SCL and SDA need be pulled to
VIN.

Level Shifters
The TPS65155 contains six level shifter channels (see Figure 34). Each channel features a logic-level input
stage and a high-level output stage powered from VGH and VGL. The output stages are capable of generating
high peak currents to drive the capacitive loads typically present in an LCD panel. Because the capacitive load
typically connected to the STV and RESET channels is relatively small, the peak current available from these two
channels is slightly lower than that available from the CLK channels.
During power-up, the level shifter outputs track VGL. During power-down, the level shifter outputs track VGH.
Power-up and power-down conditions are determined by the VDET threshold of the panel discharge function,
which also controls the level shifter channels during power-up and power-down.

VGH

CLKIN1 to CLKIN4 Level CLKOUT1 to CLKOUT4

Shifter

VGL
STRONG
NORMAL
VGH

STVIN, RESETIN Level STVOUT, RESETOUT

Shifter

VGL

Figure 34. Level Shifter Block Diagram

Power Supply Sequencing (Boost and Charge Pumps)

• When VIN < VUVLO, all functions are disabled. (2)
• When VIN > VUVLO, all functions are disabled if EN is low.
• When VIN > VUVLO and EN goes high, the boost converter and negative charge pump are enabled first. When
the output of the boost converter reaches its power good threshold, the positive charge pump is enabled.
• If EN goes low, all functions are disabled.

Power Supply Sequencing (Level Shifters)

• During power-up, when VDET is below its input threshold, the level shifter outputs track VGH. (3)
• During normal operation, when VDET is above its input threshold, the level shifter outputs follow their inputs.
• During power-down, when VDET falls below its input threshold, the level shifter outputs track VGH.

(2) The level shifter discharge function continues to function for as long as there is sufficient operating voltage on VGH and VGL
(3) The level shifter discharge function continues to function for as long as there is sufficient operating voltage on VGH and VGL
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Power Supply Sequencing (XAO)

• During power-up, when VDET is still below its input threshold, XAOis pulled low.
• During normal operation, when VDET is above its input threshold, XAO is high impedance.
• During power-down, when VDET falls below its input threshold, XAO is pulled low.

VIN > VUVLO VIN < VUVLO

VIN VIN > VDET VIN < VDET

EN

VAVDD > VPG

VAVDD

Minimum operating VGL (≈-2V)

VGL

VGH VGH > VUVLO (≈8V)

VGH < VUVLO (≈3V)

Tracks VGH

Level Shifter
Outputs

Tracks VGL

Figure 35. Power Supply Sequencing Using EN Pin, VDET < VUVLO

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VIN > VDET VIN < VDET

VIN VIN < VUVLO
VIN > VUVLO

EN

VAVDD > VPG

VAVDD

Minimum operating VGL (≈-2V)

VGL

VGH VGH > VUVLO (≈8V)

VGH > VUVLO (≈3V)

Tracks VGH

Level Shifter
Outputs

Tracks VGL

Figure 36. Power Supply Sequencing Using EN Pin, VDET > VUVLO

VIN > VUVLO VIN < VUVLO

VIN VIN > VDET VIN < VDET

VAVDD > VPG

VAVDD

Min. Operating VGL (≈-2V)

VGL

VGH VGH > VUVLO (≈8V)

VGH < VUVLO (≈3V)

Tracks VGH

Level Shifter
Outputs

Tracks VGL

Figure 37. Power Supply Sequencing with EN Pin Tied to VIN, VDET < VUVLO

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www.ti.com.cn ZHCS684 – JANUARY 2012

VIN > VDET VIN < VDET

VIN VIN > VUVLO VIN < VUVLO

VAVDD < VPG

VAVDD

Minimum operating VGL (≈-2V)

VGL

VGH VGH > VUVLO (≈8V)

VGH < VUVLO (≈3V)

Tracks VGH

Level Shifter
Outputs

Tracks VGL

Figure 38. Power Supply Sequencing with EN Pin Tied to VIN, VDET > VUVLO

Undervoltage Lockout
The TPS65155 features an undervoltage lockout (UVLO) function that disables the LCD bias functions if the
supply voltage (VIN) is below the minimum needed for correct operation (VUVLO).

Thermal Shutdown
A thermal shutdown function automatically disables all LCD bias functions if the device’s junction temperature
exceeds the safe maximum. The device automatically starts operating again once it has cooled down.

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APPLICATION INFORMATION
4u7
VIN VAVDD
10u 16.1V
40u

12k
SW SW
AVDD
VIN
47k 22n FB
SS 2R2
3n3 COMP 1k

470n
FREQ
7k32 VAVDD
FBPH 1u

100k
1k05
RNTC
3.3V DRVP
6k98 28.3 V @ T < –10°C
VGH
10k 24 V @ T > +10°C

22k SW
XAO XAO
10u
FBP
2R2
1k2
470n

DRVN 100n

EN 100k

VIN SCL
VGL –10V
SDA
10k
10u
80k6
VDET
FBN

10k 10k

VREF
100n
STVIN STVOUT
RESETIN RESETOUT
CLKIN1 CLKOUT1
CLKIN2 CLKOUT2
CLKIN3 CLKOUT3
CLKIN4 CLKOUT4

GND

PGND AGND LGND

Figure 39. Typical Application Circuit Using Positive Charge Pump in ×2 Configuration

30 Copyright © 2012, Texas Instruments Incorporated

 TPS65155
www.ti.com.cn ZHCS684 – JANUARY 2012

4u7
VIN VAVDD

10u 10u 40u

SW SW
AVDD
VIN
47k 22n FB
SS 2R2
3n3 COMP 1k

470n 470n
FREQ
VIN
7k32
FBPH 1u 1u

100k
1k05
RNTC
3.3V DRVP
6k98 28.3 V @ T < –10°C
VGH 24 V @ T > +10°C
10k
22k SW
XAO XAO
10u
FBP
2R2
1k2
470n

DRVN 100n

EN 100k

VIN SCL
VGL –10V
SDA
10k
10u
80k6
VDET
FBN

10k 10k

VREF
100n
STVIN STVOUT
RESETIN RESETOUT
CLKIN1 CLKOUT1
CLKIN2 CLKOUT2
CLKIN3 CLKOUT3
CLKIN4 CLKOUT4

GND

PGND AGND LGND

Figure 40. Typical Application Circuit Using Positive Charge Pump in ×2.5 Configuration

Copyright © 2012, Texas Instruments Incorporated 31

 PACKAGE OPTION ADDENDUM

www.ti.com 6-Apr-2024

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TPS65155RKPR ACTIVE VQFN RKP 40 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS Samples
65155

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 GENERIC PACKAGE VIEW
RKP 40 VQFN - 1 mm max height
5 x 5, 0.4 mm pitch PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4229305/A

www.ti.com
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