MODULE IV

SEQUENTIAL CIRCUITS
 Sequential Circuits
• In a sequential circuit, the outputs depends on both the present
inputs as well as the previous outputs.
• The previous outputs are also called present state of the circuit.
• The present outputs are also called next state of the circuit.
• A sequential circuit most often contains memory storage
elements.
• It may also need clock signals.
Comparison between Combinational and Sequential Circuits
 Asynchronouse & Synchronous Sequential
Circuits
• There are two types of Sequential Circuits:
• Synchronous Sequential Circuits.
• Asynchronous Sequential Circuits.
 Synchronous Sequential Circuits
• In a synchronous sequential circuit, the outputs depends on
both the present inputs as well as the previous outputs.
• The outputs also depend on clock signals.
• It most often contains memory storage elements.
• Synchronous Sequential circuits are slow. But, they are easy
to design.
 Asynchronous Sequential Circuits
• In an asynchronous sequential circuit, the outputs depends
on both the present inputs as well as the previous outputs.
• It does not need clock signals.
• It most often contains memory storage elements.
• Asynchronous Sequential circuits are fast. But, they are not
easy to design.
 S – R Latch (using NOR gate)
• A latch is a memory element that can
store one bit of information.
• A latch is an asynchronous circuit,
because it does not require clock.
• An S-R latch has two cross-coupled NOR
gates.
• It has two inputs (R and S) and two
outputs (Q and Q)ഥ
• If R=0 & S=0, the outputs do not change
(ie. the outputs Q and Qഥ retain their
present state (No Change))
• If R=1 & S=0, Q will become 0 (and Q ഥ will
become 1). This is called RESET state.
• If R=0 & S=1, Q will become 1 (and Q ഥ will
become 0). This is called SET state.
• If R=1 & S=1, both the NOR gets will force
the outputs(Q and Q) ഥ to become 0 which
is an indeterminate or undefined state.
 S – R Latch (using NAND gate)
• An S-R Latch is a memory element that
can store one bit of information.
• It has two inputs (R and S) and two
outputs (Q and Q)ഥ
• If R=0 & S=0, the outputs do not
change (ie. the outputs Q and Q ഥ retain
their present state (No Change))
• If R=1 & S=0, Q will become 0 (and Q ഥ
will become 1). This is called RESET
state.
• If R=0 & S=1, Q will become 1 (and Q ഥ
will become 0). This is called SET state.
• If R=1 & S=1, both the NOR gets will
force the outputs(Q and Q ഥ ) to become
0 which is an indeterminate or
undefined state.
 S – R Latch with control input
• An S-R Latch is a memory
element that can store one bit of
information.
• It has two inputs (R and S) and
two outputs (Q and Q ഥ)
• It also has a control input ‘C’.
• The Set and Reset operations of
the latch will happen only when
the value of the control input C
is 1. If C=0, no change in output.
• The S=1, R=1 state is
indeterminate or undefined.
 D Latch
• One way to eliminate the
indeterminate state of S-R Latch is
to ensure R and S are never equal
to 1 at the same time. This is D C
Latch.
• D Latch is constructed from a gated
SR latch with an inverter added
between the S and R inputs to
allow for a singe D (data) input.
• It also has a control input ‘C’.
• D input is directly connected to S
input and its complement is
connected to R input.
 Flip Flop (S-R Flip Flop)
• A flip flop is a memory element that can store one bit of
information just like a latch.
• But, a flip flop is a synchronous circuit.
• So, a flip flop requires a clock input for its working.
• It has two inputs (R and S) and two outputs (Q and Q ഥ)
• It also has a clock input CP (clock pulse)
• The Set and Reset operations of the flip flop will happen
only when the value of the clock input CP is 1. If C=0, no
change in output.
• When CP=S=R=1, both the outputs Q and Q ഥ will be 1 which
is an Invalid or Undefined state.
 Edge Triggered Flip Flops
• An edge-triggered flip-flop changes state either at the positive
edge (rising edge) or at the negative edge (falling edge) of the
clock pulse.
• So they are either positive edge-triggered or negative edge-
triggered FFs.
• There are 2 types of edge-triggered flip flops : D and J-K.

(Positive Edge-triggered D Flip Flop) (Negative Edge-triggered D Flip Flop)

 Edge Triggered D Flip Flop
• D flip-flop is constructed
from a gated SR flip-flop
with an inverter added
between the S and R
inputs to allow for a singe
D (data) input.
• D input is directly
connected to S input and
its complement is
connected to R input.
• A negative edge-triggered
D flip-flop changes state
at the negative edge
(falling edge) of the clock
pulse.
 J-K Flip Flop
• It is a refinement of S-R
flip flop.
• In J-K flip flop, the
indeterminate state of RS
flip flop is defined.
• The inputs, J and K,
behave like input S and R,
to set and reset the flip
flop.
• When both inputs J and K
are equal to 1, the flip
flop changes (or toggles)
to its complement state.
 Race Around Condition in J-K Flip Flop
• When J=K=1, output of JK flip-flip toggles.
• If width of clock pulse is too long compared to the propagation delay of
NAND gates, then output Q will change from 1 to 0 and 0 to 1
continuously.
• At the end of the clock pulse, it is uncertain to predict whether the value
of Q will be 1 or 0.
• This is called Race Around Condition.

• Race around condition can be avoided by two

methods:
1. Using Edge-Triggered Flip Flop
2. Master-Slave Flip Flop.
 Master Slave J-K Flip Flop

The Master Slave J-K Flip Flop is used to overcome the race condition problem of
J-K Flip Flop
 Registers & Shift Registers
• Register
• A flip flop can store one bit (0 or 1) of data.
• A register contains a number of flip flops to store a group of bits.
• So, a register is an important memory device.
• Usually, D flip flops are used in registers.
• Shift register
• A shift register contains a number of flip flops to store groups of bits.
• It can also shift bits of data.
• This capability is used to transfer data.
• A shift register can shift data left or right.
• Usually, D flip flops are used in shift registers.
(SISO)
(SIPO)
(PISO)
• Load mode
• The bits B0, B1, B2, and B3 are passed to the corresponding flip flops when the
second, fourth, and sixth "AND" gates are active.
• These gates are active when the shift or load bar line set to 0.
• The binary inputs B0, B1, B2, and B3 will be loaded into the respective flip-
flops when the edge of the clock is low.
• Thus, parallel loading occurs.
• Shift mode
• The second, fourth, and sixth gates are inactive when the load and shift line
set to 0.
• At this time, the first, third, and fifth gates will be activated, and the shifting
of the data will be left to the right bit. I
• In this way, the "Parallel IN Serial OUT" operation occurs.
Parallel In Parallel Out (PIPO)
• In "Parallel IN Parallel OUT", the inputs and the outputs come in a parallel
way in the register.
• The inputs B0, B1, B2, and B3, are directly passed to the data inputs D0, D1, D2,
and D3 of the respective flip flop.
• The bits of the binary input is loaded to the flip flops when the clock is
applied.
• The clock pulse is required for loading all the bits.
• At the output side, the loaded bits appear.
 Counters
• A counter is a sequential device used for counting (up or down) clock
pulses.
• It is a group of flip flops with a clock signal applied.
• There can be Up counter, Down counter and Up/Down counter
• Types of counters:
• Asynchronous counter (or Ripple counter)
• Synchronous counter.

Here is an example of a 2-bit

asynchronous counter.
 Asynchronous Counter (Ripple Counter)
• In these counters, each flip flop output serves as the clock input signal for
the next FF in the sequence, except for the first FF which is clocked by the
system clock.
• The FFs don’t change states at exactly the same time as they don’t have a
common clock pulse.
• There can be Up counter, Down counter and Up/Down counter.
• We can use JK flip flops or T flip flops to construct asynchronous counters.

Here is an example of a 2-bit

asynchronous counter.
 Synchronous Counter
• In these counters, the clock pulse is applied to all the flip flops exactly
at the same time.
• The FFs change states at exactly the same time as they have a
common clock pulse.
• There can be Up counter, Down counter and Up/Down counter
• We can use JK flip flops or T flip flops to construct asynchronous
counters.
 Modulus of a Counter
• The modulus of a counter is the number of states in its count
sequence.
• The maximum
n
possible modulus is determined by the number of flip
flops. (2 , where n is the number of bits of flip flops).
• For example, a counter with 2 flip flops (or2 a 2-bit counter or Mod-4
counter ) can have a modulus of upto 4 (2 ). The states are 0,1,2 and
3.
• Likewise, a counter with 3 flip flops (or a 3-bit
3
counter or Mod-8
counter) can have a modulus of upto 8 (2 ). The states are
0,1,2,3,4,5,6 and 7. A 4-bit counter (Mod-16 Counter) have a
modulus of upto 16 (24). The states run through 0 to 15.
• A modulus 5(or Mod-5) counter have the counting sequence 0,1,2,3
and 4. (In binary, the counting sequence is 000,001,010,011,100).
 State diagram (or State Transition Diagram) of a Counter
• It is a graphical way of representing the sequence of states through which a particular
type of counter progresses.

Mod-4 (or 2 Bit) Counter

Mod-5 Counter
Mod-8 (or 3 Bit) Counter

Mod-10 (or BCD/Decade) Counter

Mod-16 (or 4 Bit) Counter
 2-Bit (or Mod-4) Asynchronous Counter
• It consists of 2 JK flip flops.
• In order to achieve toggle condition, all the inputs are connected to
logical high input (J=1, K=1).
• The initial clock is applied to the first flip flop directly. The clock is
negative edge triggered to eliminate race condition.
• The output of 1st flip flop (QA)is connected to the clock of 2nd flip flop.

Mod-4 (or 2 Bit) Counter

 3-Bit (or Mod-8) Asynchronous Counter
• It consists of 3 JK flip flops.
• In order to achieve toggle condition, all the inputs are connected to logical
high input (J=1, K=1).
• The initial clock is applied to the first flip flop directly. The clock is negative
edge triggered to eliminate race condition.
• The output of 1st flip flop (QA)is connected to the clock of 2nd flip flop.
• The output of the 2nd flip flop (QB) is connected to the clock of 3rd flip flop.

Mod-8 (or 3 Bit) Counter

 4-Bit (or Mod-16) Asynchronous Counter
• It consists of 4 JK flip flops.
• In order to achieve toggle condition, all the inputs are connected to logical
high input (J=1, K=1).
• The initial clock is applied to the first flip flop directly. The clock is negative
edge triggered to eliminate race condition.
• The output of 1st flip flop (QA)is connected to the clock of 2nd flip flop.
• The output of the 2nd flip flop (QB) is connected to the clock of 3rd flip flop
and so on.

Mod-16 (or 4 Bit) Counter

 BCD (or MOD-10 or DECADE) counter
• A binary coded decimal (BCD) is a serial digital counter that counts
ten digits.
• It counts from 0 to 9.
• When the clock pulse advances to 10 (binary 1010) the FFs QB and
QD become high and thus NAND gate’s output will become low which
will reset all the flip flops (ie. the output will be come 0000).

Mod-10 (or BCD/Decade) Counter

 Ring Counter
• A ring counter is a special type of application of the Serial IN Serial OUT Shift register.
• In the ring counter, the output of last FF is passed to the first flip flop as an input.
• Below is the block diagram of the 4-bit ring counter.
• Here, we use 4 D flip flops.
• The same clock pulse is passed to the clock input of all the flip flops as a synchronous
counter.
• The Overriding input is used as clear and pre-set.
• The output is 1 when the pre-set set to 0. The output is 0 when the clear set to 0.