III

20ESEC502

Microprocessors and Microcontrollers

UNIT No. 2

2.2 Instruction set

Version: 1.0
 EC8691
MICROPROCESSORS AND MICROCONTROLLERS

INSTRUCTION SET OF 8086

The 8086 instructions are categorized into the following main types

1. Data copy /transfer instructions: These type of instructions are used to transfer data from source operand to destination
operand. All the store, load, move, exchange input and output instructions belong to this category.

2. Arithmetic and Logical instructions: All the instructions performing arithmetic , logical, increment, decrement,
compare and ASCII instructions belong to this category.

3. Branch Instructions: These instructions transfer control of execution to the specified address. All the call, jump,
interrupt and return instruction belong to this class.

4. Loop instructions: These instructions can be used to implement unconditional and conditional loops. The LOOP,
LOOPNZ , LOOPZ instructions belong to this category.

5. Machine control instructions: These instructions control the machine status. NOP, HLT, WAIT and LOCK instructions
belong to this class.

6.Flag manipulation instructions: All the instructions which directly effect the flag register come under this group of
instructions. Instructions like CLD, STD, CLI, STI etc.., belong to this category of instructions.

7.Shift and Rotate instructions: These instructions involve the bit wise shifting or rotation in either direction with or
without a count in CX.
8. String manipulation instructions: These instructions involve various string manipulation operations like Load, move,
scan, compare, store etc..,

Data Copy/ Transfer Instructions:

The following instructions come under data copy / transfer instructions:

MOV, PUSH, POP, IN, OUT,PUSHF, POPF, LEA, LDS/LES, XLAT, XCHG, LAHF, SAHF

Data Copy/ Transfer Instructions:

 EC8691
MICROPROCESSORS AND MICROCONTROLLERS

MOV: MOVE: This data transfer instruction transfers data from one register / memory location to another register /
memory location. The source may be any one of the segment register or other general purpose or special purpose registers
or a memory location and another register or memory location may act as a destination.

Syntax:

1.MOVmem/reg1, mem/reg2 [mem/reg1] [mem/reg2]

Ex: MOV BX, 0210H, MOV AL, BL

MOV [SI], [BX] is not valid

Memory uses DS as a segment register. No memory to memory operation is allowed. It won’t affect flag bits in the flag
register.
2. MOV mem, data [mem]
Ex:
MOV [BX], 02H

MOV [DI], 1231H

3. MOV reg, data [reg]

Ex: MOV AL, 11H

MOV CX, 1210H

In the case of immediate addressing mode, a segment register cannot be a destination register. In other words,
direct loading of the segment registers with immediate data is not permitted. To load the segment registers with
immediate data, one will have to load any general-purpose register with the data and then it will have to be moved to that
particular segment register.

Ex: Load DS with 5000H

1) MOV DS, 5000H; Not permitted (invalid)

Thus to transfer an immediate data into the segment register, the convert procedure is given below:

2) MOV AX, 5000H MOV DS, AX

Both the source and destination operands cannot be memory locations (Except for string instructions)

Other MOV instructions examples are given below with the corresponding addressing modes.

3) MOV AX, 5000H; Immediate

4) MOV AX, BX; Register

 EC8691
MICROPROCESSORS AND MICROCONTROLLERS

5) MOV AX, [SI]; Indirect

6) MOV AX, [2000H]; Direct

7) MOV AX, 50H[BX]; Based relative, 50H displacement

PUSH: Push to Stack: This instruction pushes the contents of the specified register/memory location on to the stack. The
stack pointer is decremented by 2, after each execution of the instruction. The actual current stack-top is always occupied
by the previously pushed data. Hence, the push operation decrements SP by two and this store the two-byte contents of the
operand onto the stack. The higher byte is pushed first and then the lower byte. Thus out of the two decremental stack
addresses the higher byte occupies the higher address and the lower byte occupies the lower address.

Syntax: PUSH reg Ex:

1. PUSH AX
2. PUSH DS

3. PUSH [5000H]; content of location 5000H & 5001H in DS are pushed onto the stack.

POP: Pop from stack: This instruction when executed, loads the specified register / memory location with the contents
of the memory location of which address is formed using the current stack segment and stack pointer as usual. The stack
pointer is incremented by 2. The POP instruction serves exactly opposite to the PUSH instruction.
Syntax:

a. POP mem

b. POP reg

Ex:

1. POP AX

2. POP DS 3. POP [5000H]

XCHG: Exchange: This instruction exchanges the contents of the specified source and destination operands, which may be
registers or one of them may be a memory location. However, exchange of data contents of two memory locations is not
permitted.

Syntax:

i) XCHG AX, reg 16 [AX]

Ex: XCHG AX, DX
ii) XCHG mem, reg [mem]
iii) Ex: XCHG [BX], DX
 EC8691
MICROPROCESSORS AND MICROCONTROLLERS

I/O Operations:
IN: Input the port: This instruction is used for reading an input port. The address of the input port may be specified in the
instruction directly or indirectly AL and AX are the allowed destinations for 8 and 16-bit input operations. DX is the only
register (implicit), which is allowed to carry the port address.

Ex: 1. IN AL, DX
2.IN AX, DX

OUT: Output to the Port: This instruction is used for writing to an output port.The address of the output port may be
specified in the instruction directly or implicitly in DX. Contents of AX or AL are transferred to a directly or indirectly
addressed port after execution of this instruction. The data to an odd addressed port is transferred on D8 –D15 while that to
an even addressed port is transferred on D0-D7.The registers AL and AX are the allowed source operands for 8- bit and 16-
bit operations respectively.

Ex:

1. OUT DX,AL
2. OUT DX,AX
3. OUT PORT,AL

. 2. Arithmetic Instructions:

These instructions usually perform the arithmetic operations, like addition, subtraction, multiplication and division along
with the respective ASCII and decimal adjust instructions. The increment and decrement operations also belong to this type
of instructions. The arithmetic instructions affect all the conditional code flags. The operands are either the registers or
memory locations immediate data depending upon the addressing mode.

ADD: Addition: This instruction adds an immediate data or contents of a memory location specified in the instruction or
a register (source) to the contents of another register (destination) or memory location. The result is in the destination
operand. However, both the source and destination operands cannot be memory operands. That means memory to
memory addition is not possible. Also the contents of the segment registers cannot be added using this instruction. All the
condition code flags are affected depending upon the result.

Syntax: i. ADD mem/reg1, mem/reg2

[mem/reg1] = [mem/reg2] + [mem/reg2]

Ex : ADD BL, [ST]

ADD AX, BX
 EC8691
MICROPROCESSORS AND MICROCONTROLLERS

ii)ADD mem, data [mem]

Ex: ADD Start, 02H

ADD [SI], 0712H

Examples with addressing modes:

• ADD AX, 0100H Immediate

• ADD AX, BX Register

• ADD AX, [SI] Register Indirect

• ADD AX, [5000H] Direct

• ADD [5000H], 0100H Immediate

• ADD 0100H Destination AX (implicit)

ADC: Add with carry: This instruction performs the same operation as ADD instruction, but adds the carry flag bit (which
may be set as a result of the previous calculations) to the result. All the condition code flags are affected by this instruction.

Syntax: i.ADCmem/reg1,mem/reg2

[mem/reg1]=[mem/reg1]+[mem/reg2]+CY

Ex: ADC BL, [SI] ADC AX, B

ii) ADC mem,data [mem]

Ex: ADC start, 02H

ADC [SI],0712H

Examples with addressing modes:

 EC8691
MICROPROCESSORS AND MICROCONTROLLERS

o ADC 0100H Immediate(AX implicit)

o ADC AX,BX Register

o ADC AX,[SI] Register indirect

o ADC AX,[5000H] Direct

o ADC [5000H],0100H Immediate

SUB: Subtract: The subtract instruction subtracts the source operand from the destination operand and the result is left in
the destination operand. Source operand may be a register or a memory location, but source and destination operands
both must not be memory operands. Destination operand cannot be an immediate data. All the condition code flags are
affected by this instruction.

Syntax: Submem/reg1,mem/reg2

[mem/reg1]=[mem/reg2]-[mem/reg2]

Ex: SUB BL,[SI]

SUB AX, BX

Ex: SUB start, 02H

SUB [SI],0712H

ii. SUB A,data [A]

iii. Ex: SUB AL, 02H

IV. SUB AX, 1211H

Examples with addressing modes:

1. SUB 0100H Immediate [destination AX]

2. SUB AX, BX Register

3. SUB AX,[5000H] Direct

4. SUB [5000H], 0100 Immediate

 EC8691
MICROPROCESSORS AND MICROCONTROLLERS

SBB: Subtract with Borrow: The subtract with borrow instruction subtracts the source operand and the borrow flag
(CF) which may reflect the result of the previous calculations, from the destination operand. Subtraction with borrow,
here means subtracting 1 from the subtraction obtained by SUB ,if carry (borrow) flag is set.

The result is stored in the destination operand. All the conditional code flags are affected by this instruction.
Ex: SBB BL,[SI] SBB AX,BX

INC: Increment: This instruction increments the contents of the specified register or memory location by 1. All the
condition flags are affected except the carry flag CF. This instruction adds a to the content of the operand. Immediate
data cannot be operand of this instruction.

Syntax: i. INCreg16

Ex: INC BX

Segment register cannot be incremented. This

operation does not affect the carry flag.

Examples with addressing modes:

1. INC AX Register

2. INC [BX] Register indirect

3. INC [5000H] Direct

DEC: Decrement: The decrement instruction subtracts 1 from the contents of the specified register or memory location. All
the condition code flags except carry flag are affected depending upon the result. Immediate data cannot be operand of the
instruction.

Syntax:

Ex: DEC reg16

Ex: DEC BL
 EC8691
MICROPROCESSORS AND MICROCONTROLLERS

Examples with addressing mode

1. DEC AX Register

2. DEC [5000H] Direct

MUL: Unsigned multiplication Byte or Word: This instruction multiplies unsigned byte or word by the content of AL. The
unsigned byte or word may be in any one of the general-purpose register or memory locations. The most significant word
of result is stored in DX, while the least significant word of the result is stored in AX. All the flags are modified depending
upon the result. Immediate operand is not allowed in this instruction. If the most significant byte or word of the result is ‘0’
IF and OF both will be set.

Syntax: MUL mem/reg

Ex: MUL BL

Ex: MUL BX

DIV: Unsigned division: This instruction performs unsigned division. It divides an unsigned word or double word by a
16-bit or 8-bit operand. The dividend must be in AX for 16-bit operation and divisor may be specified using any one of
the addressing modes except immediate. The result will be in AL (quotient) while AH will contain the remainder. If the
result is too big to fit in AL, type 0(divide by zero) interrupt is generated. In case of a double word dividend (32-bit), the
higher word should be in DX and lower word should be in AX. The divisor may be specified as already explained. The
quotient and the remainder, in this case, will be in AX and DX respectively. This instruction does not affect any flag.

Syntax: DIV mem/reg

Ex: DIV BL (i.e. [AX]/[BX])

Ex: DIV BX
 EC8691
MICROPROCESSORS AND MICROCONTROLLERS

Logical Instructions
AND, OR, NOT, XOR, TEST

These byte of instructions are used for carrying out the bit by bit shift, rotate or basic logical operations. All the
conditional code flags are affected depending upon the result. Basic logical operations available with 8086 instruction set
an AND, OR, NOT and XOR.

AND: Logical AND: This instruction bit by bit ANDs the source operand that may be an immediate, a register, or a
memory location to the destination operand that may be a register or a memory location. The result is stored in the
destination operand. At least one of the operand should be a register or a memory operand. Both the operands cannot be
memory locations or immediate operand.

The examples of this instruction are as follows:

Syntax: i. AND mem/reg1, mem/reg2

Ex: AND BL, CH

ii. AND mem,data Ex: AND start,05H

Ex: AND AL, FOH

OR: Logical OR: The OR instruction carries out the OR operation in the same way as described in case of the AND
operation. The limitations on source and destination operands are also the same as in case of AND operation.

Syntax: i. OR mem/reg1, mem/reg2

Ex:OR BL, CH
NOT: Logical Invert: The NOT instruction complements (invents) the contents of an operand register or a memory
location bit by bit.

Syntax: i.Ex: NOT reg NOT AX

Ex: NOT [SI]

XOR: Logical Exclusive OR: The XOR operation is again carried out in a similar way to the AND and OR operation.
The constraints on high output, when the 2 input bits are dissimilar. Otherwise, the output is zero.

Syntax: i. XOR mem/reg1, mem/reg2

Ex: XOR BL, CH

 EC8691
MICROPROCESSORS AND MICROCONTROLLERS

ii. XOR mem,data Ex: XOR start, 05H

iii. XOR reg, data Ex: XOR AL, FOH

CMP: Compare: This instruction compares the source operand, which may be a register or an immediate data or a
memory location, with a destination operand that may be a register or a memory location. For comparison, it subtracts
the source operand from the destination operand but does not store the result anywhere. The flags are affected depending
on the result of subtraction. If both the operands are equal, zero flag is set. If the source operand is greater than the
destination operand, carry flag is set or else, carry flag is reset.

Syntax: CMP mem/reg1, mem/reg2 [mem/reg1] – [mem/reg2]

CMP CX, BX

TEST: Logical Compare Instruction: The TEST instruction performs a bit by bit logical AND operation on the two
operands. Each bit of the result is then set to 1, if the corresponding bits of both operands are1, else the result bit is rest to
0. The result of this and operation is not available for further use, but flags are affected. The affected flags are OF, CF,
ZF and PF. The operands may be register, memory or immediate data.

Syntax: i. TEST mem/reg1, mem/reg2

Ex: Test CX,BX

ii. TEST mem/reg, data [mem/reg] data

Ex:TEST CH, 03H

iii. TEST A, data

2. Shift Instructions:

SHL/SAL SHR SAR

SHL/SAL: Shift Logical/ Arithmetic Left: These instructions shift the operand word or byte bit by bit to the left and
insert zeros in the newly introduced least significant bits. In case of all the SHIFT and ROTATE instructions, the count is
either 1 or specified by register CL. The operand may reside in a register or memory location but cannot be immediate
data. All flags are affected depending on the result.

Ex:

Syntax: i. SAL mem/reg,1

Shift arithmetic left once

 EC8691
MICROPROCESSORS AND MICROCONTROLLERS

ii. SAL mem/reg, CL

Shift arithmetic left a byte or word by shift count in CL register.

iii. SHL mem/reg,1 Shift Logical Left

Ex: SHL BL, 01H

iv. SHL mem/reg, CL

Shift Logical Left once a byte or word in mem/reg.

SHR: Shift Logical Right: This instruction performs bit-wise right shifts on the operand word or byte that may reside in a
register or a memory location, by the specified count in the instruction and inserts zeros in the shifted positions. The
result is stored in the destination operand. This instruction shifts the operand through carry flag.

SAR: Shift Arithmetic Right: This instruction performs right shifts on the operand word or byte, that may be a register or a
memory location by the specified count in the instruction and inserts the most significant bit of the operand the newly
inserted positions. The result is stored in the destination operand. All the condition code flags are affected. This shift
operation shifts the operand through carry flag.

Syntax: i. SAR mem/reg,1

ii. SAR mem/reg, CL

3. Rotate Instructions:

ROR ROL RCR RCL

ROR: Rotate Right without Carry: This instruction rotates the contents of the destination operand to the right (bit- wise)
either by one or by the count specified in CL, excluding carry.

The least significant bit is pushed into the carry flag and simultaneously it is transferred into the most significant bit
position at each operation. The remaining bits are shifted right by the specified positions. The PF, SF, and ZF flags are
left unchanged by the rotate operation. The operand may be a register or a memory location but it can’t be an immediate
operand. The destination operand may be a register (except a segment register) or a memory location.

Syntax: i.Ex: mem/reg, 01

ROR BL, 01
ROL: Rotate Left without Carry: This instruction rotates the content of the destination operand to the left by the specified
count (bit-wise) excluding carry. The most significant bit is pushed into the carry flag as well as the least significant bit
position at each operation. The remaining bits are shifted left subsequently by the specified count positions. The PF, SF
and ZF flags are left unchanged by this rotate operation. The operand may be a register or a memory location.
 EC8691
MICROPROCESSORS AND MICROCONTROLLERS

Syntax: i. ROL mem/reg,

1 Rotate once left

ii. ROL mem/reg, CL

Rotate once left a byte or a word in mem/reg.

RCR: Rotate Right Through Carry: This instruction rotates the contents (bit-wise) of the destination operand right by the
specified count through carry flag (CF) For each operation, the carry flag is pushed into the MSB of the operand, and the
LSB is pushed into carry flag. The remaining bits are shifted right by the specified count positions. The SF, PF, ZF are left
unchanged. The operand may be a register or memory location.

Syntax: i. RCL mem/reg, 1

Ex: RCL BL, 1

ii. mem/reg, CL

Ex: RCL BX, CL

RCL: Rotate Left through Carry: This instruction rotates (bit-wise) the contents of the destination operand left by the
specified count through the carry flag (CF) For each operation, the carry flag is pushed into LSB, and the MSB of the
operand is pushed into carry flag. The remaining bits are shifted left by the specified positions. The SF, PF, ZF are left
unchanged. The operand may be a register or a memory location.
The count for rotation or shifting is either 1 or is specified using register CL, in case of all the shift and rotate instructions.

4. String Manipulation Instructions:

A series of data bytes or words available in memory at consecutive locations, to be referred to collectively or individually
are called as byte strings or word strings.

REP MOVSB/MOVSW CMPSB/CMPSW SCASB/SCASW STOSB/STOSW

LODSB/LODSW

REP: Repeat Instruction Prefix: This instruction is used as a prefix to other instructions. The instruction to which the REP
prefix is provided, is executed repeatedly until the CX register becomes zero (at each iteration CX is automatically
decremented by one) When CX becomes zero, the execution proceeds to the next instruction in sequence. There are two
more options of the REP instruction. The first is REPE/REPZ (i.e. repeat operation which equal/zero. The second is
REPNE/REPNZ allows for repeating the operation which not equal/not zero. These options are used for CMPS, SCAS
instructions only, as instruction prefixes.
 EC8691
MICROPROCESSORS AND MICROCONTROLLERS

MOVSB/MOVSW: Move String Byte or String Word: Suppose a string of bytes, stored in a set of consecutive memory

locations is to be moved to another set of destination locations. The starting byte of the source string is located in the
memory location whose address may be computed using SI (Source Index) and DS (Data Segment) contents. The starting
address of the destination locations where this string has to be relocated is given by DI (Destination Index) and ES (Extra
Segment) contents. The starting address of the source string is 10H * DS
+ [SI] while the starting address of the destination string is 10H * ES + [DI]. The MOVSB/MOVSW instruction thus,
moves a string of bytes/words pointed to by DS:SI pair (source) to the memory location pointed to by ES:DI pair
(destination)
After the MOVS instruction is executed once, the index registers are automatically updated and CX is decremented. The
incrementing or decrementing of the pointers, i.e. SI and DI depend upon the direction flag DF. If DF is 0, the index
registers are incremented, otherwise, they are decremented, in case of all string manipulation instructions.

(a) Memory map (b) AL program.

The single 8086 instruction MOVSB will perform all the actions in the REPEAT-UNTIL loop. The MOVSB instruction
will copy a byte from the location pointed to by the DI register. It will then automatically increment SI to point to next
destination location. The repeat (REP) prefix in front of the MOVSB instruction, the MOVSB instruction will be
repeated and CX decremented until CX is counted down to zero. In other words, the REP MOVSB instruction will move
the entire string from the source location to the destination location if the pointers are properly initialized.

CMPSB/CMPSW: Compare String Byte or String Word: The CMPS instruction is used to compare two strings of bytes or
words. The length of the string must be stored in the register CX. If both the byte or word strings are equal, zero flag is set.
The flags are affected in the same way as CMP instruction. The DS:SI and ES:DI point to the two strings. The REP
instruction prefix is used to repeat the operation till CX (counter) becomes zero or the condition specified by the REP
prefix is false.

The following string of instructions explain the instruction. The comparison of the string starts from initial or word of the
string, after each comparison the index registers are updated depending on the direction flag and the counter is
decremented. This byte by byte or word by word comparison continues till a mismatch is found. When, a mismatch is
found, the carry and zero flags are modified appropriately and the execution proceeds further.

SCAS: Scan String BYTE or String Word: This instruction scans a string of bytes or words for an operand byte or word
specified in the register AL or AX. The string is pointed to by ES:DI register pair. The length of the string is stored in
CX. The DF controls the mode for scanning ofthe string as stated in case of MOVSB instruction. Whenever a match to
the specified operand, is found in the string, execution stops and the zero flag is set. If no match is found, the zero flag is
reset. The REPNE prefix is used with the SCAS instruction. The pointers and counters are updated automatically, till a
match is found.
 EC8691
MICROPROCESSORS AND MICROCONTROLLERS

LODS: Load string Byte or String word: The LODS instruction loads the AL/AX register by the content of a string
pointed to by DS:SI register pair. The SI is modified automatically depending on DF. If it is a byte transfer (LODSB), the
SI is modified bye one and if it is a word transfer (LODSW), the SI is modified by two. No other flags are affected by
this instruction.

STOS: Store String Byte or String Word: The STOS instruction stores the AL/AX register contents to a location in the
string pointed by ES:DI register pair. The DI is modified Accordingly. No flags are affected by this instruction.
The direction flag controls the string instruction execution. The source index SI and destination index DI are modified
after each iteration automatically. If DF=1, then the execution follows auto decrement mode. In this mode, SI and DI are
decremented automatically after each iteration (by1 or 2 depending on byte or word operations) Hence, in auto
decrementing mode, the string are referred to by their ending addresses. If DF=0, then the execution follows auto
increment mode. In this mode, SI and DI are incremented automatically (by 1 or 2 depending on byte or word operation)
After each iteration, hence the strings, in this case, are referred to by their starting addresses.

5. Control Transfer or Branching Instruction:

The control transfer instructions transfer the flow of execution of the program to a new address specified in the instruction
directly or indirectly. When this type of instruction is executed, the CS and IP registers get loaded with new values of CS
and IP corresponding to the location where the flow of execution is going to be transferred.

These types of instructions are classified in two types:

i. Unconditional control Transfer (Branch) Instructions:

In case of unconditional control transfer instructions; the execution control is transferred to the specified location
independent of any status or condition. The CS and IP are unconditionally modified to the new CS and IP.

ii. Conditional Control Transfer (Branch) Instructions:

In the conditional control transfer instructions, the control is transferred to the specified location provided the result of
the previous operation satisfies a particular condition, otherwise, the execution continues in normal flow sequence. The
results of the previous operations are replicated by condition code flags. In other words, using type of instruction the
control will be transferred to a particular specified location, if a particular flag satisfies the condition.

Unconditional Branch Instructions:

CALL RET

JUMP

IRET INT N INT O LOOP

 EC8691
MICROPROCESSORS AND MICROCONTROLLERS

CALL: Unconditional Call: This instruction is used to call a subroutine procedure from a main program. The address of
the procedure may specify directly or indirectly depending on the address mode.

There are again two types of procedures depending on whether it is available in the same segment (Near CALL, i.e. + 2K
displacement) or in another segment (Far CALL, i.e. anywhere outside the segment). The modes for them are respectively
called as intrasegment and intersegment addressing (i.e. address of the next instruction) and CS onto the stack along with
the flags and loads the CS and IP registers, respectively, with the segment and offset addresses of the procedure to be
called.

RET: Return from the Procedure: At each CALL instruction, the IP and CS of the next instruction is pushed onto stack,
before the control is transferred to the procedure. At the end of the procedure, the RET instruction must be executed.
When it is executed, the previously stored content of IP and CS along with flags are retrieved into the CS, IP and flag
registers from the stack and the execution of the main program continues further. In case of a FAR procedure the current
contents of SP points to IP and CS at the time of return. While in case of a NEAR procedure, it points to only IP.
Depending on the byte of procedure and the SP contents, the RET instruction is of four types:
i. Return within a segment.

ii. Return within a segment adding 16-bit immediate displacement to the SP contents.

iii. Return intersegment.

iv. Return intersegment adding 16-bit immediate displacement to the SP contents.

INT N: Interrupt Type N: In the interrupt structure of 8086/8088, 256 interrupts are defined corresponding to the types
from 00H to FFH. When an INT N instruction is executed, the TYPE byte N is multiplied by 4 and the contents of IP and
CS of the interrupt service routine will be taken from the hexadecimal multiplication (N * 4) as offset address and 0000 as
segment address. In other words, the multiplication of type N by 4 (offset) points to a memory block in 0000 segment,
which contains the IP and CS values of the interrupt service routine. For the execution of this instruction, the IP must be
enabled.

INTO: Interrupt on overflow: This is executed, when the overflow flag OF is set. The new contents of IP an CS are taken
from the address 0000:0000 as explained in INT type instruction. This is equivalent to a type 4 instruction.

JMP: Unconditional Jump: This instruction unconditionally transfer the control of execution to the specified address using
an 8-bit or 16-bit displacement (intrasegment relative, short or long) or CS:IP (intersegment direct for) No flags are
affected by this instruction. Corresponding to the three methods of specifying jump address, the JUMP instruction has the
following three formats.

JUMP Intrasegment, relative, near jump

JUMP Intrasegment, relative, For jump

 EC8691
MICROPROCESSORS AND MICROCONTROLLERS

JUMP Intersegment, direct, jump

IRET: Return from ISR: When interrupt service routine is to be called, before transferring control to it, the IP, CS and
flag register are stored on to the stack to indicate the location from where the execution is to be continued, after the ISR
is executed. So, at the end of each ISR, when IRET is executed, the valuesof IP, CS and flags are retrieved from the stack
to continue the execution of the main program. The stack is modified accordingly.

LOOP: Loop unconditionally: This instruction executes the part of the program from the label or address specified in the
instruction up to the loop instruction, CX number of times. At each iteration, CX is decremented automatically, in other
words, this instruction implements DECREMENT counter and JUMP IF NOT ZERO structure.

When these instructions are executed, they transfer execution control to the address specified relatively in the instruction,
provided the condition in the opcode is satisfied, otherwise, the execution continues sequentially. The conditions, here
means the status of the condition code flags. These type of instructions don’t affect any flags. The address has to be
specified in the instruction relatively in terms of displacement, which must lie within – 80H to 7FH (or –128 to 127) bytes
from the address of the branch instruction. In other words, only short jumps can be implemented using conditional branch
instructions. A label may represent the displacement, if it has within the above- specified range.