1076 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO.

5, MAY 2007

An IF-to-Baseband Modulator for AM/FM/IBOC 61

Radio Receivers With a 118 dB Dynamic Range
Paulo G. R. Silva, Member, IEEE, Lucien J. Breems, Senior Member, IEEE,
Kofi A. A. Makinwa, Senior Member, IEEE, Raf Roovers, Member, IEEE, and Johan H. Huijsing, Fellow, IEEE

an AM channel filter. This modulator combines the anti-aliasing

61
Abstract—A single-bit fifth-order complex continuous-time
IF-to-baseband modulator for AM/FM/IBOC receivers is suppression of a CT loop filter, the low-jitter sensitivity of a
presented. The input IF is 10.7 MHz and the sampling frequency switched-capacitor (SC) DAC implementation, and a quadrature
is 41.7 MHz. The modulator achieves a dynamic range of 118 dB
in AM mode (3 kHz BW), 98 dB in FM mode (200 kHz BW), passive mixer for IF-to-baseband down-conversion.
and 86 dB in IBOC mode (500 kHz BW). The modulator’s high The paper is organized as follows. Section II describes the
dynamic range enables the realization of an AM radio receiver state-of-the-art architecture for DSP-based AM/FM receivers,
without a VGA and without an AM channel-selection filter, and then describes the proposed receiver architecture. The IF-to-
thereby reducing system complexity and cost. The elimination of baseband conversion system is discussed in Section III. The
the VGA also improves the sensitivity and the overall noise figure
of the receiver. The modulator’s spurious free dynamic range is modulator architecture is discussed in Section IV. Section V
88 dB in the bandwidth from 25 to 525 kHz. The IM2 distance is presents the building-block circuits. In Section VI, some ex-
92 dB, and the IM3 distance is 91 dB. The ADC was fabricated in perimental results are shown. The conclusions are presented in
a one-poly five-metal 0.18- m CMOS process with an active area Section VII.
of 6.0 mm2 . It consumes 210 mW from a 1.8-V supply.
Index Terms—AM/FM radio receivers, analog-to-digital con- II. RECEIVER TOPOLOGIES
version, CMOS analog integrated circuits, continuous-time Fig. 1 shows the architecture of a typical DSP-based AM/FM
sigma-delta modulation, IF mixer. radio receiver [3], [6]. Two separate radio front-ends mix both
AM and FM signals to a 10.7 MHz IF. The IF signals are fil-
tered by external AM and FM channel-selection filters (30 kHz,
I. INTRODUCTION
and 200 kHz BW), and amplified by a high-linearity/low-noise
VGA. The VGA provides the analog input for the IF-to-base-
OWADAYS, AM/FM radios are found in almost all au- band modulator and has programmable levels of gain,
N tomotive products. It is a very competitive and very high
volume market, where the best way to further reduce fabrication
varying from 0 to 18 dB.
The combined effect of the channel-selection filter and the
costs is to decrease the bill of materials, i.e., by decreasing the VGA is shown in Fig. 2 for the FM reception mode. In the
number of components and reducing the complexity of the en- Americas, the FM band carrier spacing and the modulated
tire system [1]. channel width are both 200 kHz. When the wanted channel is
The current generation of DSP-based AM/FM radio receivers very strong, the AGC loop sets the gain of the VGA to 0 dB
(Fig. 1) rely on analog-to-digital converters (ADCs) and dig- Fig. 2(a). The unwanted channels are 40 dB attenuated [6] by
ital signal processing to achieve high-quality reception [2]–[7]. the channel-selection filter. Fig. 2(b) shows the other extreme
Analog signal conditioning like filtering and amplification is case: the wanted FM channel is so small that the VGA is set to
used to relax ADC specifications. Two external AM and FM its maximum gain. The wanted signal can be properly amplified
channel filters limit the bandwidth of the IF signal delivered to because all strong unwanted channels are filtered out before the
the ADC, while an automatic gain control (AGC) loop relaxes VGA. In the case where the VGA is not preceded by filtering,
the ADC’s dynamic range (DR) requirements [3], [6]. In order the strong unwanted signals saturate the VGA output and the
to eliminate the AGC loop, the variable gain amplifier (VGA) wanted signal is blocked. The whole receiver is desensitized in
and the AM filter, an ADC with larger DR ( 100 dB) is re- this situation.
quired (Fig. 4). The availability of such an ADC would simplify The AM channel spacing is 10 kHz in the Americas and 9 kHz
the design of the receiver, and reduce the total cost of the radio. elsewhere. This means that a 30 kHz channel-selection filter is
In this paper, the design of a 118 dB DR continuous-time (CT) not sufficiently able to attenuate adjacent channels (Fig. 3). The
IF-to-baseband modulator is presented. The modulator’s average attenuation of this ceramic filter is 1 dB at the edge of
high DR means that the receiver no longer requires a VGA and the 10 kHz BW, 3 dB at 20 kHz, 12 dB at 30 kHz and 38 dB at
50 kHz [23]. When the wanted channel is very strong, the VGA
Manuscript received July 19, 2006; revised December 11, 2006.
gain is set to 0 dB and the ADC input is the wanted channel sur-
P. G. R. Silva, K. A. A. Makinwa, and J. H. Huijsing are with the Electronic rounded by two weakly attenuated adjacent channels [Fig. 3(a)].
Instrumentation Lab, Department of Microelectronics, Delft University of Tech- The final AM channel-selection is then performed in the digital
nology, Delft 2628 CD, The Netherlands (e-mail: [email protected]). domain. When the wanted AM channel is very weak, again the
L. J. Breems and R. Roovers are with NXP Semiconductors, Eindhoven 5656
AE, The Netherlands. maximum 18 dB VGA gain is selected. If the adjacent chan-
Digital Object Identifier 10.1109/JSSC.2007.894820 nels are also weak [Fig. 3(b)], the whole 30 kHz BW around the
0018-9200/$25.00 © 2007 IEEE

Authorized licensed use limited to: National Taiwan University. Downloaded on September 21,2022 at 12:15:11 UTC from IEEE Xplore. Restrictions apply.
SILVA et al.: AN IF-TO-BASEBAND MODULATOR FOR AM/FM/IBOC RADIO RECEIVERS WITH A 118 dB DYNAMIC RANGE 1077

Fig. 1. State-of-the-art DSP-based AM/FM radio receiver.

Fig. 2. FM filter and VGA: (a) strong wanted channel and VGA = 0 dB;
(b) weak wanted channel and VGA = 18 dB.

10.7 MHz IF is amplified and good quality reception is achieved.

However, when the adjacent channels are very strong [Fig. 3(c)],
Fig. 3. AM filter and VGA: (a) strong wanted channel and VGA = 0 dB;
the insufficiently attenuated unwanted signals can saturate the (b) weak wanted channel with weak adjacent channels and VGA = 18 dB;
VGA and block the wanted channel. Although the receiver’s (c) weak wanted channel with strong adjacent channels and VGA = 18 dB,
sensitivity could be improved by a high quality-factor 10 kHz the wanted channel is blocked.
AM channel filter, this option increases the overall cost of the
radio. In Fig. 3(c), the intermodulation products among the AM
channels are not depicted.
The IF-to-baseband modulator is responsible for the dig-
itization of the filtered analog signals around the 10.7 MHz IF.
The same ADC is used in all operating modes, and has a DR
of 100 dB for AM and 80 dB for FM reception [3], [6]. This
ADC alone is not enough to cope with AM/FM reception DR
requirements. The combination of a 0–18 dB gain VGA with a
100 dB DR ADC can achieve an input-referred DR of 118 dB
required in AM mode. Fig. 4 illustrates this situation for a VGA
with four gain settings. The ADC I/Q output bitstreams are then
processed in the DSP. This processing consists of additional fil-
tering, decimation, demodulation and the implementation of the
AGC loop. However, the VGA consumes 230 mW, while the
AM filter is quite costly. To eliminate both, the modulator’s DR
must be increased by at least 18 dB. This implies that the total Fig. 4. Input-referred DR of a 100 dB DR ADC (AM mode) preceded by a
0/6/12/18 dB gain VGA. The DR of an 118 dB DR ADC (AM mode) is also
in-band noise power of the modulator must be reduced by shown for comparative purpose.
the same factor.
Fig. 5 shows a receiver without the AM channel-selection
filter and the VGA. This architecture demands a very linear (200 kHz BW) is used in both modes of operation. The input of
ADC (IM3 85 dB) with 118 dB DR in AM mode, and the new IF-to-baseband ADC is therefore 20 AM channels or a
98 dB DR in FM mode. Separate front-ends are still needed single FM channel. Overall, the linearity and DR requirements
for AM and FM reception. A single FM channel-selection filter for this ADC are defined by the AM reception requirements

Authorized licensed use limited to: National Taiwan University. Downloaded on September 21,2022 at 12:15:11 UTC from IEEE Xplore. Restrictions apply.
1078 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 5, MAY 2007

Fig. 5. Proposed DSP-based AM/FM radio receiver without AM channel filter and without a VGA.

ADC. Bandpass modulators directly process the IF

input and can provide high resolution in a certain BW of in-
terest. However, it is more difficult to design resonators with
the required quality factors at the IF than to design resonators
at baseband frequencies. This is because the opamps used will
have reduced gain near the IF, and also the effects of the para-
sitics will be much more pronounced. For the same reason, the
linearity requirements for multi-channel AM reception are also
more difficult to meet around 10.7 MHz. For the same appli-
cation, bandpass modulators have relatively higher power con-
Fig. 6. FM-IBOC channel frequency spectrum. sumption and are less linear than IF-to-baseband modulators [4],
[5], [8]–[10].
because of the presence of strong channels together with very IF-to-baseband ADCs [15] are the more power-efficient so-
weak channels inside the signal band. In AM mode, most of the lution for the combined digitization of AM and FM signals. In
channel-selection is performed in the digital domain. Because IF-to-baseband ADCs, a mixer is integrated with a baseband
the VGA has been removed, the noise figure of the whole re- modulator. For the same specifications, they achieve higher
ceiver improves for both AM and FM reception. Also the AGC linearity and lower power consumption than bandpass modula-
loop does not need to be implemented anymore. Furthermore, tors [3], [6]. The analog input around the 10.7 MHz IF can be
the sensitivity of the receiver is improved in AM mode: strong converted directly to DC (zero-IF) or to a lower intermediate
adjacent channels can not block the wanted channel anymore frequency (low-IF) [13]. The location of the ADC signal band
because all the required DR is provided by the ADC. is lowest when zero-IF down-conversion is used, but the ADC’s
This ADC also complies with the IBOC (In-Band performance is then very sensitive to DC offset and noise.
On-Channel) specification. IBOC is a standard for digital In the case of low-IF mixing, the wanted channel is mixed down
audio broadcasting that allows a digital channel to be added to to an offset frequency greater than half the channel bandwidth.
the existing analog broadcast signals [11], [12]. Because of the In both cases, quadrature mixers and two independent in-phase
200 kHz FM carrier spacing used in the Americas, digital infor- (I) and quadrature-phase (Q) signal paths are necessary to re-
mation can be transmitted as sidebands adjacent to the standard duce image rejection requirements [14]. The major drawback
analog information, as shown in Fig. 6. OFDM modulation is of the IF-to-baseband architecture is the unwanted mixing of
used for the FM-IBOC transmission. In Europe however, where RF signals around 3 times the IF with the third harmonic of the
the FM channel width is 150 kHz and the carrier spacing is mixer frequency. These signals are then down-converted to the
100 kHz, this approach is not possible. In order to implement same low-IF as the wanted channel. Therefore, some filtering
FM-IBOC reception, a larger 500 kHz BW channel-selection is required before the ADC. In car radio receivers, the AM/FM
filter and a second IF-to-baseband ADC have to be added to band filters after the antenna and the FM channel filter provide
the system (Fig. 7). The ADC must provide a SFDR 70 dB enough attenuation at those frequencies.
through the entire 500 kHz signal band for proper reception Fig. 8 shows the block diagram of the quadrature IF-to-base-
of the IBOC digital bands. In IBOC mode, the DSP processes band conversion system with two CT modulators and in-
both the selected analog FM and the digital FM-IBOC signals, tegrated quadrature mixers. In this design, the modulator
the IBOC algorithm then chooses the one that provides the best sampling frequency is 41.7 MHz. The positive frequen-
audio quality to the user. cies signal band ranges from 25 to 525 kHz in FM-IBOC
The 118 dB DR IF-to-baseband ADC that enables the receiver mode, and from 175 to 375 kHz in analog AM/FM mode.
topologies shown in Figs. 5 and 7 is the subject of the following As a result, the oversampling ratio is, respectively, OSR 42
sections in this paper. and OSR 105. In order to obtain a signal band centred on the
single-sided 275 kHz low-IF, the mixer switching frequency
III. IF-TO-BASEBAND CONVERSION SYSTEM is 10.425 MHz. Two I and Q mixer driver signals are gen-
The ADC required by the AM/FM receiver of Fig. 5 can be erated on-chip (divided by 4) from the modulators’ sampling
implemented as a bandpass ADC or as an IF-to-baseband clock.

Authorized licensed use limited to: National Taiwan University. Downloaded on September 21,2022 at 12:15:11 UTC from IEEE Xplore. Restrictions apply.
SILVA et al.: AN IF-TO-BASEBAND MODULATOR FOR AM/FM/IBOC RADIO RECEIVERS WITH A 118 dB DYNAMIC RANGE 1079

Fig. 7. Proposed DSP-based AM/FM/IBOC radio receiver.

high-frequency components generated by the mixers are then

easily removed [15]. A single-bit quantizer is used together with
a single-bit, inherently linear, switched-capacitor (SC) feedback
DAC. In this case, most of the feedback charge is integrated at
the beginning of the DAC duty-cycle. As a result, a CT mod-
ulator implemented with a SC DAC can tolerate larger delays
between the quantizer and feedback DAC clock signals. This ar-
chitecture is also less sensitive to jitter-induced errors. The com-
bination of a CT modulator with SC feedback was proposed by
[16] and successfully implemented in [17] for a radio receiver
application.

A. Complex Loop Filter

Fig. 8. IF-to-baseband conversion system with CT 61 modulators and quadra- Fig. 9 shows the single-bit fifth-order loop filter with feedfor-
ture passive mixers. ward coefficients used in this design. Two modulators process
I and Q analog inputs. The feedforward coefficients provide
Mismatch between the quadrature paths leads to quantization first-order roll-off at the unity open-loop gain frequency and
noise leakage problems [14]. Quantization noise in the image ensure the modulator’s stability [18]. Fig. 10 shows the Bode
band leaks into the desired signal band, and vice versa. This is plots for the complex loop filter. The loop filter phase shift is
less problematic when quadrature zero-IF mixing is used, as the about 100 at half the sampling frequency . Real and
image band is always correlated with the desired band. In the complex resonators (Fig. 9) provide the required quantization
case of low-IF mixing, the power inside the image band may be noise attenuation inside the signal band. The real resonators are
much larger that in the desired channel, which demands much implemented through the local feedback path around the second
more image rejection from the whole quadrature system. The and third integrators, and the cross-connections between I and
image rejection ratio (IRR) translates to a matching requirement Q modulators implement two complex resonators. As a re-
sult, three notches are placed across the positive frequencies to
IRR (dB) (1)
reduce the in-band quantization noise.
The modulator’s simulated output spectrum is shown in
where is the relative gain mismatch and is the phase Fig. 11: the quantization noise in the right side of the spectrum
error in radians between the I/Q paths. The AM/FM receiver (signal band) is much lower than on the left side. Because the
requires 80 dB of image rejection [6]. Because the FM channel analog input current is a complex signal, the frequency location
filter has 40 dB out-of-band attenuation, at least 40 dB of image of the input tone is also asymmetrical related to the DC. The
rejection must be provided by the matching of the I/Q paths. notch on the left side is very important because it reduces quan-
This is equivalent to a gain error mismatch below 1.4% and a tization noise leakage from the image band to the signal band,
phase error smaller than 0.8 . for instance due to mismatch between I and Q modulators [14].
The spread in the resonators’ passive components (resistors
IV. MODULATOR ARCHITECTURE and capacitors) cause deviation of the position of the notches.
A continuous-time modulator is chosen for this design However, the impact of these non-idealities is small since, by
because of its inherent low-pass filtering characteristics. The design, the overall noise in the band of interest is dominated by

Authorized licensed use limited to: National Taiwan University. Downloaded on September 21,2022 at 12:15:11 UTC from IEEE Xplore. Restrictions apply.
1080 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 5, MAY 2007

Fig. 9. Single-bit fifth-order CT IF-to-baseband complex 61 modulator.

Fig. 10. Fifth-order complex loop filter Bode plots (logarithmic frequency scale).

circuit thermal noise (Fig. 11). In this way, even with maximum
spread, the quantization noise will still be below the circuit
noise.
The loop filter coefficients are scaled in order to guarantee
that the differential output swing of each integrator is bounded
to 0.4 V. This value was chosen to keep each loop filter opera-
tional transconductance amplifier (OTA) operating in the linear
region, as the internal common-mode (CM) voltages were set
to 0.7 V ( 1.8 V). As a consequence of the scaling,
the first integrator’s unity gain frequency is 30% smaller
than the second integrator’s unity gain frequency . The fre-
quency could have been increased if were increased, but
41.7 MHz is a system-level design constraint. Fig. 12
shows the fifth-order loop filter internal voltages (simula-
tion) for a differential 0.5 V maximum sinusoidal input. All
internal states are bounded to the 0.4-V limit. Fig. 11. Simulated (MatLab) complex output spectrum.
All the loop filter’s building blocks contribute to the in-band
noise budget and the quantification of dominant circuit noise building block. Because of the high gain of the first integrator
sources is essential to achieve the required 118 dB DR. Fig. 13 at low frequencies, the circuit noise and the harmonic distor-
shows the input-referred noise contribution of each loop filter tion from the other integrators are highly attenuated. The loop

Authorized licensed use limited to: National Taiwan University. Downloaded on September 21,2022 at 12:15:11 UTC from IEEE Xplore. Restrictions apply.
SILVA et al.: AN IF-TO-BASEBAND MODULATOR FOR AM/FM/IBOC RADIO RECEIVERS WITH A 118 dB DYNAMIC RANGE 1081

Fig. 12. 61 modulator differential internal voltages for a 0.5 V maximum input sinusoidal.

TABLE I
BIAS TAIL CURRENT AND POWER CONSUMPTION
OF EACH LOOP FILTER BUILDING BLOCK

Fig. 13. Input-referred thermal noise contribution from each loop filter zero [15]. The RHP zero introduces an extra phase shift and
building-block.
makes the loop filter less stable. The other integrators and res-
onators are implemented by - stages. The feedforward co-
filter is designed to be thermal-noise-limited by the front-end efficients, which connect the output of each integrator to the
circuitry. The input-referred noise of the first integrator and the single-bit quantizer, are implemented by transconductors.
DAC determine the ADC’s noise floor at low frequencies. The
input-referred noise of the second integrator is also relevant B. CT Modulator With SC Feedback DAC
at the edge of the AM/FM signal bandwidth (175–375 kHz). Sensitivity to clock jitter is a major limitation in CT
This happens because the gain of the first integrator is not high modulators [18]. The modulator is affected by timing uncer-
enough at these frequencies. The input-referred noise contribu- tainty in the quantizer during the sampling of the loop filter’s
tion from the high-order integrators, resonators and feedforward analog output, and in the DAC during the generation of the feed-
coefficients is designed to be marginal in the band of interest. back pulses. The errors introduced during the sampling process
The noise (not shown in Fig. 13) has a corner frequency are strongly attenuated by the modulator’s NTF. However, the
of about 70 kHz. The maximum allowed thermal noise con- errors introduced by the DAC are not attenuated and directly
tribution determines the power consumption in each loop filter limit the performance of the entire modulator. CT modu-
building block. Table I shows the static power consumption and lators employing SC DAC are less sensitive to timing uncer-
the tail bias current of each loop filter OTA. tainty [16]. Fig. 14 shows how a return-to-zero (RTZ) pulse and
In order to implement a first integrator with high linearity, an exponential pulse, generated by a SC DAC, are affected by
the integrating capacitors are used in a feedback configura- pulse-width jitter. In the exponential pulse case, the jitter-in-
tion to create a virtual ground between the OTA inputs. The pas- duced error charge also depends on the settling behavior of the
sive mixers are placed between the input resistors and the virtual DAC current . The SNR limitations due to the pulse-width
ground nodes of the first OTA. The first integrator’s input-re- jitter for RTZ and SC DACs, respectively, are expressed as [17]:
ferred noise is determined by the input resistors’ thermal noise
in the band of interest and the thermal noise of the first OTA is OSR
(2)
designed to be below that level. At very low frequencies, the
OTA’s noise and offset dominate. A resistor, with value
, should be placed in series with the integrating capaci- OSR
(3)
tors to compensate for the presence of a right-half-plane (RHP)

Authorized licensed use limited to: National Taiwan University. Downloaded on September 21,2022 at 12:15:11 UTC from IEEE Xplore. Restrictions apply.
1082 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 5, MAY 2007

The noise contribution of the SC DAC is an important part of

the modulator’s input-referred noise budget. The thermal noise
from the MOS switches, the DAC’s reference voltage, and the
first OTA is sampled-and-held by the DAC’s capacitors. In [22],
it is shown that an upper bound for the input-referred noise PSD
from a RC integrator connected to a SC DAC is given by

PSD Hz (5)

where is Boltzman’s constant, is the absolute temperature

in Kelvin, is the input resistor and is the
equivalent resistor from a SC network. The approximation (5)
is valid if the DAC’s reference voltage is designed to have a
Fig. 14. RTZ and exponential DAC pulses affected by pulse-width jitter. thermal noise contribution below the DAC’s switches’ thermal
noise and the modulator’s OSR is high.

V. CIRCUIT BUILDING BLOCKS

The most important circuit building blocks are the input IF
mixers, the loop filter’s OTAs, the quantizer and the SC feed-
back DAC. They are described in the following sub-sections:

A. Input IF Mixers
The input IF mixers (Fig. 16) are implemented with nMOS
switches placed in between the input resistances and the vir-
tual ground nodes of the first OTA of the CT modulator.
The feedback DAC terminals are connected to the same nodes.
In order to operate properly, the mixer switches are driven by
Fig. 15. SNR limitation due to pulse-width jitter in RTZ and SC DACs, and complementary non-overlapping clock phases [15]. Otherwise,
due to pulse-positioning jitter. The SNR due to thermal noise is also shown as
a reference. all switches would conduct for a certain period of time and a low
impedance path would exist between the virtual ground nodes.
As a consequence, the integrated feedback charge would be dis-
where is the DAC’s duty-cycle, is the rms jitter, and torted. The power consumption of these mixers is negligible and
is the relative settling-time of . In high-linearity is obtained because the on-resistance of the
this model, the timing errors are assumed to be a random white switches is quite small compared to the p-poly input resistors
noise process with variance . The term in . In this design, because the 1.65 k , the mixer
(3) is the jitter sensitivity improvement factor from an RTZ to a switches were made very large to implement
SC feedback DAC. , at the expense of larger parasitic capacitances.
CT modulators are also affected by pulse-position jitter Every mixer half-clock cycle, the input resistors are con-
[18]. Due to timing errors, the position of the feedback pulse nected or cross-connected to the input virtual ground nodes.
is shifted in time while the total integrated charge remains con- Because of the finite opamp gain, a residual voltage is
stant. The SNR degradation due to this effect is independent of present at these nodes. When LO is high, the parasitic ca-
the feedback pulse shape and is given by [18] pacitances are charged with [Fig. 16(a)]. This residual
voltage carries an attenuated version of the shaped quantiza-
(4) tion noise. At the beginning of the next mixer clock phase,
the parasitic charge flows back to the virtual ground nodes,
where is the maximum input signal frequency. and is integrated [Fig. 16(b)]. consists of two main com-
For a 50% DAC duty cycle and , a theoretical ponents: the p-poly-to-nwell parasitic capacitance of
SNR improvement of 29.4 dB is achieved. Fig. 15 shows the , and the mixer nMOS switch
peak SNR limitation as a function of the rms jitter , due to capacitance. In this design, fF and fF. In
pulse-width jitter in RTZ and SC DACs, and due to pulse-posi- the time domain, this operation is equivalent to sampling at
tion jitter. The peak SNR due to thermal noise in AM/FM mode twice the mixer switching frequency . The consequences
(OSR 105) is also shown as a reference. Fig. 15 reveals that an of this parasitic sampling then depend on the relation between
oscillator with 0.8 ps is required to achieve the target peak and .
SNR 98 dB if an RTZ DAC is used in this CT modulator. When is sampled at a rate . As a result,
The SC DAC allows the use of an oscillator with 4 ps, the sampled version of contains the same information as the
as the pulse-position limitation becomes dominant over the SC original analog voltage without aliasing and the parasitic charge
DAC pulse-width jitter limitation. The effective SNR improve- stored in is integrated at the same rate as the error signal
ment then becomes 14 dB. coming from the modulator summing node. The spectrum

Authorized licensed use limited to: National Taiwan University. Downloaded on September 21,2022 at 12:15:11 UTC from IEEE Xplore. Restrictions apply.
SILVA et al.: AN IF-TO-BASEBAND MODULATOR FOR AM/FM/IBOC RADIO RECEIVERS WITH A 118 dB DYNAMIC RANGE 1083

Fig. 16. Conventional passive mixer: (a) LO phase. (b) LO phase.

at the output of the first integrator is basically unchanged, and

the noise floor within the signal band is not increased.
When is sampled at a rate . This means
that the spectrum content from to is aliased to base-
band. Spectral components located at an arbitrary frequency
are then down-converted to . This means attenu-
ated replicas of the tones near will be seen near DC after
the subsampling. The final effect of the subsampling on the
modulator output spectrum depends on the fraction of the
charge stored in that is actually transferred to the integrating
capacitor . The charge transfer coefficient is equal to

(6)

where is the output resistance of the signal source driving

the modulator. To illustrate this effect, Fig. 17 shows a
MatLab behavioral simulation of the IF-to-baseband ADC with Fig. 17. Simulation (MatLab) of the fifth-order IF-to-baseband ADC with con-
fF, pF and . Several tones can ventional mixer topology and C = 135 fF.
be seen above the thermal noise floor. To attenuate the effect
of the subsampling of the quantization noise, an isolated mixer
input-referred thermal noise. The DC gain is 95 dB and the
topology was proposed in [3]. In this configuration, each switch
unity gain frequency is 610 MHz. pMOS input transistors are
is connected to its own input resistors (Fig. 22). The charge
used to obtain low noise. The common-mode control is
transfer coefficient from to then becomes
implemented with an error amplifier that compares a reference
level with the actual CM level, generated by the resistive av-
(7)
erage of the two differential outputs. The input and the output
CM levels are, respectively, 0.8 V and 0.7 V.
Most of the parasitic charge will leak away via the input re- The subsequent integrators are implemented with source de-
sistors and will not return to the virtual ground nodes if is generated OTAs in order to increase the differential linear input
low enough. The improvement factor from the traditional mixer range to 0.4 V and to better define the transconductance. As
to the isolated mixer topology is given by the ratio between ex- the input and output CM levels are the same, a folded cascoded
pressions (6) and (7). For k and , it is topology (Fig. 19) was chosen for these single-stage OTAs.
about 30 dB. The low-frequency tones seen in Fig. 17 are 30 dB Triode-biased transistors are employed in the common-mode
attenuated and stay below the thermal noise floor. As a result, control circuitry. The parasitic capacitances , from the nodes
the modulator’s performance is not impaired anymore by this A and B to the ground, impact the frequency response of the
parasitic effect. -C resonators. The value of the parasitic capacitance
is determined mainly by the p-poly-to-nwell capacitance.
B. Loop Filter and Quantizer The effect of is to reduce the magnitude of the loop filter
The modulator’s first integrator employs a single-stage resonances. When is too large, the resonant peak vanishes
telescopic OTA (Fig. 18) with gain boosted [19] nMOS and completely and the expected NTF notch is suppressed. As a
pMOS cascodes to achieve a high DC gain in a 0.18- m CMOS result, the quantization noise power increases inside the signal
process. It is biased with a tail current mA in order to band. To prevent this effect, the degeneration resistors
achieve a large transconductance mA/V and low were designed with minimum area.

Authorized licensed use limited to: National Taiwan University. Downloaded on September 21,2022 at 12:15:11 UTC from IEEE Xplore. Restrictions apply.
1084 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 5, MAY 2007

Fig. 18. Single-stage telescopic OTA employed in the first integrator.

Fig. 19. Single-stage folded-cascoded degenerated OTA employed in the remaining integrators and resonators.

Fig. 20(a) depicts the nMOS-in-nwell capacitors used in this mulation region is required between the G and N terminals for
design [17]. Besides the high capacitance per area, MOSCAPs linear operation. Single MOSCAPs are employed as grounded
present a capacitance with large voltage dependence [20]. A capacitors in the -C integrators, but cannot be used as the
positive voltage large enough to bias the device in the accu- floating capacitors required by the first integrator. Series con-

Authorized licensed use limited to: National Taiwan University. Downloaded on September 21,2022 at 12:15:11 UTC from IEEE Xplore. Restrictions apply.
SILVA et al.: AN IF-TO-BASEBAND MODULATOR FOR AM/FM/IBOC RADIO RECEIVERS WITH A 118 dB DYNAMIC RANGE 1085

output current is then subtracted from the input current at the

virtual ground node and integrated on the capacitors of the first
integrator. To reduce charge injection, S1 opens slightly before
S1d, and S2 opens slightly before D or DN. As the inputs of
the IF-to-baseband ADC are capacitively coupled to the
radio front-end, the input CM level of the first OTA follows
the DAC common-mode voltage CM V.
Fig. 23 shows the timing diagram for the SC feedback DAC
and input IF mixers.
The size of the DAC capacitors are obtained from the
scaling relation between and the equivalent resistor of a SC
network [17]:

(8)

Fig. 20. (a) nMOS-in-nwell MOSCAP device and (b) series-connected

MOSCAPS used as a floating capacitor in the first integrator and SC feedback
where is the maximum input rms voltage and is the
DAC. DAC equivalent differential voltage. Because the DAC capac-
itors are cross-connected to ground and V during
the discharging phase by switches S2, . As a re-
nected MOSCAPs that can be used as floating capacitors, are sult, 4.5 pF for the parameters in this design. Each se-
show in Fig. 20(b). The series connection, together with the ries-connected 9 pF capacitor presents a total top-plate area of
differential structure of the first integrator, provide a cancella- 980 m . The length of each unity MOSCAP was minimized
tion of the even-order non-linearities and an attenuation of the in order to implement a low parasitic series resistance.
odd-order non-linearities if the 2 (4 in a differential structure) The total DAC series resistance was
capacitors are equal [20]. In order to keep the devices in the ac- sized in order to allow the DAC output current to settle within
cumulation region, a MOS diode pulls the MOSCAP gates to 10 time constants inside the interval. The
(1.8 V). After the gates are charged to , the diode is p-poly resistors , placed between the capacitors
turned-off as its becomes zero [17]. The capacitors of and the bitstream independent switches S1/S2, are used to
the first integrator are implemented as two 110pF series-con- linearize the settling behavior of the DAC output current
nected MOSCAPs, and the total top-plate area of each is and to limit its peak value [16]. With , the peak
about 24000 m . The parasitic series resistance of was is limited to 6.1 mA, preventing slewing of
used to implement the RHP zero compensation resistor the first OTA.
(Fig. 22). Due to the SC DAC discharge, the voltage across the vir-
The feedforward coefficients are implemented as MOSFET- tual ground nodes can experience large transients every time
only degenerated transconductors [21] with current output. the DAC capacitors are connected to the OTA inputs. In a SC
Fig. 21 shows one of the feedforward coefficients connected modulator, just the final values of the internal loop filter
to the current-input summing-node of the single-bit quantizer, states are relevant. However, in a CT modulator, the instan-
where an internal latch performs the current-to-voltage conver- taneous values of the internal states are important as the inte-
sion. The differential latch output is then fed into AND gates, grators process the analog signals continuously. Therefore, the
producing a true digital differential output, which is stored in dynamic behavior of the voltage across the first OTA inputs may
a flip-flop. All quantizer control signals are provided by an affect the linearity of the first integrator if the peak value of
internal DLL. is too large. If the first OTA is modelled as a transconductance
, a closed form expression for the single-ended during
C. Switched-Capacitor DAC the discharging phase can be calculated:
The complete modulator front-end circuitry for one
ADC channel is shown in Fig. 22. The SC DAC is implemented (9)
with series-connected nMOS-in-nwell floating capacitors and
MOS switches [17]. Different switches were implemented According to (9), the first OTA should be designed with
with nMOS or pMOS 120 mA/V in order to keep the peak virtual ground
transistors, according to the internal DAC voltages. As a result, voltage below 50 mV (100 mV differential). The actual
the discharging transients in the pMOS and nMOS DAC paths dynamic behavior of was obtained from SPICE simu-
are slightly different. Because a single-bit differential DAC lations (Fig. 23) of the IF-to-baseband modulator. For
is used, the mismatch between the paths just causes an offset the parameters in this design and first OTA sized for
error. In the first clock phase, the capacitors are charged to 120 mA/V and 610 MHz, the circuit simulation predicts
by closing switches S1 and S1d (switches S2 open). 38 mV (76 mV differential). The discrepancy be-
In the second clock phase, switches S2 are closed (switches tween the circuit simulation and the analytical derivation, can
S1 and S1d open) and the capacitors are discharged in a be in part explained by the fact that of the MOS switches
data-dependent way by closing switches D or DN. The DAC increases when is peaking.

Authorized licensed use limited to: National Taiwan University. Downloaded on September 21,2022 at 12:15:11 UTC from IEEE Xplore. Restrictions apply.
1086 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 5, MAY 2007

Fig. 21. Feedforward coefficient implementation and current-input single-bit quantizer.

Fig. 22. IF-to-baseband ADC front-end: passive mixer, first integrator and SC feedback DAC.

The passive mixers also require quiet virtual ground nodes to The DLL generates delayed clocks to control the quantizer and
implement a linear V–I conversion [15]. Therefore, in this de- the buffers generate 1.6 V from a stable external 1.2 V ref-
sign, the mixer switches change state just after the virtual ground erence. The 41.7 MHz clock is provided externally. The mod-
nodes have had 10 time-constants to settle from the SC DAC dis- ulator operates from a 1.8 V supply and consumes 210 mW
charge. (I Q). The total active area is 6.0 mm , while the area of each
modulator is 2.1mm .
VI. EXPERIMENTAL RESULTS In Fig. 25, the modulator’s SNDR is plotted as a function of
The prototype chip in Fig. 24 was fabricated in a one-poly the input signal. The input tone is at 10.7 MHz and it is down-
five-metal (1P5M) 0.18- m CMOS process. The IC includes a converted to the 275 kHz low-IF. The full scale (FS) input is
clock divider, a DLL, two buffers, and LVDS transmitters. defined as 0.5 V ( 6 dB). In AM mode (3 kHz BW), the DR

Authorized licensed use limited to: National Taiwan University. Downloaded on September 21,2022 at 12:15:11 UTC from IEEE Xplore. Restrictions apply.
SILVA et al.: AN IF-TO-BASEBAND MODULATOR FOR AM/FM/IBOC RADIO RECEIVERS WITH A 118 dB DYNAMIC RANGE 1087

Fig. 23. IF-to-baseband ADC front-end timing and SPICE circuit simulation
results.

Fig. 26. Measured output spectrum with mixer OFF and two-tone input at 250
and 300 kHz.

Fig. 24. Fabricated prototype micrograph.

Fig. 27. Measured output spectrum with mixer ON and two-tone input at
10.625 and 10.675 MHz.

signal at 10.625 and 10.675 MHz. The absolute input amplitude

is 4 dB higher to compensate for the passive mixers 4 dB gain.
The IM2 distance is 92 dB, and the IM3 distance is 91 dB. The
SFDR is 88 dB in the 25–525 kHz band. Some spurious tones
can be seen inside the signal band. The strongest tones are in
fact coming from the arbitrary waveform generator (AWG). The
signal generator used in this measurement is the same as used in
Fig. 26. For the measurement with mixer on, however, the AWG
oversampling ratio is reduced by a factor 40 and its output noise
and non-linearity are increased. The high noise floor around the
Fig. 25. Measured SNDR as a function of the input signal level in AM and FM
modes. two input tones is due to the multiplication of the mixer clock
phase noise with the signal generator phase noise. Because of
is 118 dB and the peak SNR is 113 dB. In FM mode, (200 kHz the noise coming from the signal generator, it is not possible
BW) the DR is 98 dB and the peak SNR is 90 dB. For IBOC to see the asymmetrical noise shaping. The FFT of the com-
(500 kHz BW), the DR is 86 dB and the peak SNDR is 78 dB. plex output spectrum for an idle input measurement is plotted
Fig. 26 shows the FFT of the measured modulator output in Fig. 28. In this case it is possible to notice the asymmetrical
bitstream with the mixer off. The input is a 6 dB FS two- noise shaping: the left side of the spectrum is quantization noise
tone signal at 250 and 300 kHz. In this measurement, the IM2 limited, while the right side (signal band centred on 275 kHz) is
distance is 102 dB, and the worst case IM3 distance is 96 dB. thermal-noise-limited.
The SFDR is greater than 90 dB in the 500 kHz band. The leakage tones in the image band in Fig. 27 are 74 dB
Fig. 27 shows the FFT of the measured modulator output below the input tones for the measured sample. The image re-
bitstream with the mixer on. The input is a 6 dB FS two-tone jection ratio (IRR) was measured for all 32 available samples.

Authorized licensed use limited to: National Taiwan University. Downloaded on September 21,2022 at 12:15:11 UTC from IEEE Xplore. Restrictions apply.
1088 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 5, MAY 2007

TABLE II
SUMMARY OF PERFORMANCE

Fig. 28. Measured output spectrum for an idle input.

is now performed in the digital domain. The ADC consumes

210mW, about 8 times more than the current generation of
IF-to-baseband ADCs. However, the ADC eliminates the need
for a 230 mW VGA, and so the total power consumption of the
radio receiver remains about the same.

ACKNOWLEDGMENT
The authors would like to thank H. Termer for laying out
part of the prototype chip, and C. Dijkmans, R. van Veldhoven,
K. Philips, and P. Nuijten for their comments during the design
Fig. 29. Image rejection ratio histogram for 32 measured samples.
and test of this modulator.

REFERENCES
An IRR histogram based on those measurements (mixer on) is
[1] R. C. Lind, H. W. Yen, and D. L. Welk, “Evolution of the car
presented in Fig. 29. The mean IRR is 63 dB and the calcu- radio—From vacuum tubes to satellite and beyond,” presented at the
lated standard deviation is 6 dB. The 3 lower boundary SAE Convergence International Congress & Exposition on Trans-
for the IRR is 45 dB, 5 dB beyond the 40 dB IRR required ex- portation Electronics, Oct. 2004.
[2] M. Sala, F. Salidu, F. Stefani, C. Kutschenreiter, and A. Baschi-
clusively from the quadrature IF-to-baseband ADC. This result rotto, “Design considerations and implementation of a DSP-based
was obtained exclusively through careful attention to lay-out. car-radio IF processor,” IEEE J. Solid-State Circuits, vol. 39, no. 7,
No dynamic element matching techniques were used in this de- pp. 1110–1118, Jul. 2004.
[3] Q. Sandifort, L. J. Breems, C. Dijkmans, and H. Schuurmans, “IF-to-
sign. Table II presents the summary of performance for this digital converter for FM/AM/IBOC radio,” in Proc. 29th ESSCIRC,
IF-to-baseband ADC. Sep. 2003, pp. 707–710.
[4] V. Colonna, G. Gandolfi, F. Stefani, and A. Baschirotto, “A 10.7 MHz
VII. CONCLUSION
self-calibrated SC multibit 2nd-order banpass 61 Modulator,” in Proc.
28th ESSCIRC, Sep. 2002, pp. 575–578.
[5] P. Cusinato, D. Tonietto, F. Stefani, and A. Baschirotto, “A 3.3-V
The high-resolution quadrature modulator presented in
this paper combines the anti-aliasing suppression of a CT loop
CMOS 10.7- MHz sixth-order bandpass 61 modulator with 74-dB
dynamic range,” IEEE J. Solid-State Circuits, vol. 36, no. 4, pp.
filter, the low jitter sensitivity of a SC feedback DAC implemen- 629–638, Apr. 2001.
tation, and the low power consumption of passive mixers for [6] E. J. van der Zwan, K. Philips, and C. A. A. Bastiaansen, “A 10.7- MHz
IF-to-baseband sigma delta A/D conversion system for AM/FM radio
IF-to-baseband down-conversion. It achieves a DR of 118 dB in receivers,” IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1810–1819,
AM mode, 98 dB in FM mode. The SFDR is 88 dB within the Dec. 2000.
extended FM-IBOC bandwidth. This high DR IF-to-baseband [7] J. W. Whikehart, “DSP-based radio with IF processing,” presented at
the SAE World Congress, Mar. 2000.
ADC enables the development of new AM/FM/IBOC receivers [8] J. A. E. P. van Engelen, R. J. van de Plassche, E. Stikvoort, and A.
for car radios. G. Venes, “A sixth-order continuous-time bandpass sigma-delta mod-
The proposed radio does not require the use of a VGA or ulator for digital radio IF,” IEEE J. Solid-State Circuits, vol. 34, no. 12,
pp. 1753–1764, Dec. 1999.
an expensive ceramic AM channel-selection filter. As a result, [9] L. Louis, J. Abcarius, and G. W. Roberts, “An eight-order bandpass
the total cost and complexity of the radio system has been 16 modulator for A/D conversion in digital radio,” IEEE J. Solid-State
reduced compared to the previous generation [2]–[6]. The Circuits, vol. 34, no. 4, pp. 423–431, Apr. 1999.
[10] L. Vogt, D. Brookshire, S. Lottholz, and G. Zwiehoff, “A two-chip
new architecture also improves the radio’s noise figure and digital car radio,” in IEEE ISSCC Dig. Tech. Papers, 1996, vol. 1, pp.
AM sensitivity. Most of the channel-selection in AM mode 350–351.

Authorized licensed use limited to: National Taiwan University. Downloaded on September 21,2022 at 12:15:11 UTC from IEEE Xplore. Restrictions apply.
SILVA et al.: AN IF-TO-BASEBAND MODULATOR FOR AM/FM/IBOC RADIO RECEIVERS WITH A 118 dB DYNAMIC RANGE 1089

[11] B. W. Kroeger and P. J. Peyla, “Compatibility of FM hybrid in-band Kofi A. A. Makinwa (M’97–SM’05) received the
on-channel (IBOC) system for digital audio broadcasting,” IEEE Trans. B.Sc. and M.Sc. degrees from Obafemi Awolowo
Broadcasting, vol. 43, pp. 421–430, Dec. 1997. University, Nigeria, in 1985 and 1988, respectively.
[12] J. R. Detweiler, “Conversion requirements for AM & FM IBOC trans- In 1989, he received the M.E.E. degree from the
mission,” iBiquity Digital Corp., White Paper. Philips International Institute, The Netherlands, and
[13] J. Crols and M. S. J. Steyaert, “Low-IF topologies for high-perfor- in 2004, the Ph.D. degree from Delft University
mance analog front-ends of fully integrated receivers,” IEEE Trans. of Technology, The Netherlands, for a thesis on
Circuits Syst. II, Analog Digit. Signal Process., vol. 45, no. 3, pp. electrothermal sigma-delta modulators.
269–282–1950, Mar. 1998. From 1989 to 1999, he was a research scientist at
[14] S. A. Jantzi, K. W. Martin, and A. S. Sedra, “Quadrature bandpass 16 Philips Research Laboratories, where he designed
modulation for digital radio,” IEEE J. Solid-State Circuits, vol. 32, no. sensor systems for interactive displays and analog
12, pp. 1935–1950, Dec. 1997. front-ends for optical and magnetic recording systems. In 1999, he joined
[15] L. J. Breems, E. J. van der Zwan, E. C. Dijkmans, and J. H. Huijsing, Delft University of Technology, where he is currently an Associate Professor
“A 1.8 mW CMOS 61 modulator with integrated mixer for A/D con- in the Faculty of Electrical Engineering, Computer Science and Mathematics.
version of IF signal,” IEEE J. Solid-State Circuits, vol. 35, no. 4, pp. His main research interests are in the design of precision analog circuitry,
468–475, Apr. 2000. sigma-delta modulators, and sensor interfaces. His research has resulted in nine
[16] M. Ortmanns, Y. Manoli, and F. Gerfers, “A continuous-time sigma- U.S. patents and over 40 technical papers.
delta modulator with reduced jitter sensitivity,” in Proc. 28th ESSCIRC, Dr. Makinwa is on the program committees of several international con-
Sep. 2002, pp. 287–290. ferences, including the IEEE International Solid-State Circuits Conference
[17] R. H. M. van Veldhoven, “A triple-mode continuous-time 61 mod- (ISSCC) and the International Solid-state Sensors and Actuators Conference
ulator with switched-capacitor feedback DAC for a GSM-EDGE/ (Transducers). He has presented tutorials at many conferences, including the
CDMA200/UMTS receiver,” IEEE J. Solid-State Circuits, vol. 38, no. ISSCC. He is a co-recipient of the ISSCC 2006 Jan van Vessem award for best
12, pp. 2069–2076, Dec. 2003. European paper, the JSSC 2005 best paper award and the ISSCC 2005 Jack
[18] E. J. van der Zwan and E. C. Dijkmans, “A 0.2-mW CMOS 61 modu- Kilby Award for best student paper. In 2005, he received a Veni award from the
lator for speech coding with 80-dB dynamic range,” IEEE J. Solid-State Netherlands Organization for Scientific Research and the Simon Stevin Gezel
Circuits, vol. 31, no. 12, pp. 1873–1880, Dec. 1996. award from the Technology Foundation STW.
[19] K. Bult and G. J. G. M. Geelen, “A fast-settling CMOS op amp for SC
circuits with 90-dB DC gain,” IEEE J. Solid-State Circuits, vol. 25, no.
12, pp. 1379–1384, Dec. 1990.
[20] H. Yoshizawa, Y. Huang, P. F. Ferguson, Jr., and G. C. Temes, Raf Roovers (S’89–M’95) received the Master’s
“MOSFET-only switched-capacitor circuits in digital CMOS tech- degree in electrical and mechanical engineering and
nology,” IEEE J. Solid-State Circuits, vol. 34, no. 6, pp. 734–747, Jun. the Ph.D. degree in electrical engineering from the
1999. Katholieke Universiteit Leuven, Belgium, in 1990
[21] F. Krummenacher and N. Joehl, “A 4-MHz CMOS continuous-time and 1996, respectively.
filter with on-chip automatic tuning,” IEEE J. Solid-State Circuits, vol. From 1990 to 1995, he was a research assistant
23, no. 6, pp. 750–758, Jun. 1983. in the ESAT-MICAS Laboratory of the Katholieke
[22] P. Silva, L. Breems, K. Makinwa, and J. Huijsing, “Noise analysis of Universiteit Leuven. In 1995, he joined Philips Re-
continuous-time sigma-delta modulators with switched-capacitor feed- search Laboratories, Eindhoven, The Netherlands, in
back DAC,” in Proc. IEEE ISCAS, May 2006, pp. 3790–3793. the Mixed-Signal Circuits and Systems group, where
[23] CERAFIL Catalog. [Online]. Available: www.murata.com he designed A/D and D/A converters for various con-
sumer and communication systems. His research interests are in analog-to-dig-
Paulo G. R. Silva (S’97–M’07) was born in Rio de ital and digital-to-analog conversion circuits, high frequency integrated circuit
Janeiro, Brazil, in 1976. He received the electrical design and mixed-signal circuits and architectures for communication systems.
engineering degree from the State University of Currently, he is department head of the Integrated RF solutions research group
Campinas (UNICAMP), Brazil, in 1998. From in NXP Semiconductors, the semiconductor division spun out of Philips Elec-
February to December 1998, he was an intern at tronics.
the Motorola IC Design Center, Campinas, Brazil, Dr. Roovers is a member of the technical program committee of the IEEE
in the field of Analog Microelectronics. In 1999, International Solid-State Circuits Conference.
he joined the Magneti-Marelli Research Lab at
the same university, where he received the M.Sc.
degree in 2001. Since February 2002, he has been
pursuing the Ph.D. degree at the Delft University of
Technology, Delft, The Netherlands, in cooperation with the Philips Research Johan H. Huijsing (SM’81–F’97) was born on May
21, 1938. He received the M.Sc. degree in electrical
Labs, Eindhoven, The Netherlands.
His research interests include analog and mixed-mode circuit design, data engineering from the Delft University of Technology,
Delft, The Netherlands in 1969, and the Ph.D. degree
converters, sigma-delta modulators, and precision interface electronics.
from the same university in 1981 for his thesis on op-
erational amplifiers.
He has been an Assistant and Associate Professor
in electronic instrumentation at the Faculty of Elec-
Lucien J. Breems (S’97–M’00–SM’07) was born in trical Engineering of the Delft University of Tech-
Haarlem, The Netherlands, on March 4, 1973. He re- nology since 1969, where he became a full Professor
ceived the M.Sc. and Ph.D. degrees in electrical en- in the chair of Electronic Instrumentation since 1990,
gineering from the Delft University of Technology, and Professor Emeritus since 2003. From 1982 through 1983, he was a Senior
Delft, The Netherlands, in 1996 and 2001, respec- Scientist at Philips Research Labs, Sunnyvale, CA. From 1983 to 2005, he was
tively. a consultant for Philips Semiconductors, Sunnyvale, and since 1998 has also
From 2000 to 2006, he was with Philips Research been a consultant for Maxim in Sunnyvale. His research work is focused on
Laboratories, Eindhoven, The Netherlands. In 2006, the systematic analysis and design of operational amplifiers, analog-to-digital
he joined NXP Semiconductors Research, where he converters and integrated smart sensors. He is author or coauthor of some 250
is currently a Senior Scientist. He is the author of the scientific papers, 40 patents and 13 books, and co-editor of 13 books.
book Continuous-Time Sigma-Delta Modulation for Dr. Huijsing is a Fellow of IEEE for contributions to the design and analysis
A/D Conversion in Radio Receivers (Kluwer, 2001). His research interests in- of analog integrated circuits. He was awarded the title of Simon Stevin Meester
clude sigma-delta A/D conversion and mixed-signal circuit design. for applied Research by the Dutch Technology Foundation.
Dr. Breems is a member of the technical program committees of the IEEE In-
ternational Symposium on Low Power Electronics and Design and the Sympo-
sium on VLSI Circuits. He received the Jan van Vessem Award for outstanding
European Paper at the 2001 IEEE International Solid-State Circuits Conference.

Authorized licensed use limited to: National Taiwan University. Downloaded on September 21,2022 at 12:15:11 UTC from IEEE Xplore. Restrictions apply.