Part 5: Monograph 3

Low noise JFET pre-amplifiers

1. Introduction

Junction field effect transistors (JFETs) have a higher noise voltage, compared to bipolar junction transistors
(BJTs) [1] but much lower noise current. Their noise resistance is much higher and suited to applications where the
source impedance is greater than about 100kΩ.

Whereas excellent integrated circuits are available (e.g. the Analogue Devices AD 645 op-amp and the Burr-Brown
INA126 instrumentation amplifier) the absolute best noise performance is achieved with discrete transistors or
proprietary matched pairs.

The most frequently used pre-amplifier circuit is the differential in/out long tail pair. The long tail pair can be used
on its own, if accuracy and stability of the gain is not critical (e.g. as the pre-amp of a null detector) or as the first
stage, inside the loop, of a composite amplifier/integrator, employing an operational amplifier with negative
feedback for greater accuracy. In high accuracy applications JFETs are mostly employed at the front end of a
charge amplifier, as part of a capacitance bridge, typically operating at 1.6kHz.

The choice of operating current depends mainly on the type of JFET. Generally speaking a higher current results in
a lower noise voltage and higher noise current but not in simple inverse proportion as with BJTs. The best way to
match source resistance is by selecting the right type of JFET (larger area devices have lower noise resistance). The
best choice of operating current is at the upper end of the device capability as the gain is also higher and the noise
voltage (usually the main issue) is lowest. One must be aware, however, of self heating and heat dissipation (good
ventilation and a heat sink help) as noise current increases significantly with temperature.

DC performance is not particularly good, in terms of both initial matching and temperature stability. The best (and
most expensive) proprietary matched pairs have a mismatch of 10mV or more and often require an offset trim.

Other parameters, on the other hand, are quite well matched, especially when the DC is trimmed (precisely matched
operating current) and a common mode rejection ratio of over 100dB (105) is readily achieved.

An alternative to the long tail pair is a differential source follower. The main advantage is speed (no Miller
capacitance) and a bandwidth of many MHz The main disadvantage is low gain (approximately ×1) and the need
for a low noise amplifier stage to follow. There are, however, a number of applications where a source follower
pre-amplifier could be a useful extra. In a multi-purpose instrument, for example, a wide range of source
impedance can be catered for with a BJT front end and a source follower. The source follower is switched in for the
higher impedance ranges.

An N-type JFET is basically a thin conduction channel of N-type semiconductor material embedded in a P-type
substrate forming a high quality PN junction. At each end of the conduction channel connections are brought to the
surface with N-type material (drain and source). An insulating depletion region is formed at the PN junction [2].

VD Drain
Source Gate Drain
IDS
Gate
VG

Source
VS
P-type substrate

Fig. 1.1 A basic model for the JFET (N-type)

1. Part 5, monograph 2: “Low noise BJT pre-amplifiers.”

2. Part 5, monograph 4: “JFET Theory.”

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High Accuracy Electronics
A single connection is made to the substrate (the gate). The extent of charge carrier depletion and, therefore, the
shape and thickness of the conduction channel depend on the relative voltages of all three connections. Whereas
some devices are precisely symmetrical, with regard to drain and source, others are designed to minimise on-chip
capacitance between the gate and drain. At low frequency the drain and source are usually interchangeable.

In most applications the PN junction is reverse biased and the current flowing in or out of the gate is negligible (a
few pA at ambient temperature). The current flowing “down the drain” is almost exactly the same as that flowing
“out of the source” (hence the silly names). The most frequently used mode of operation is the “pinched-off” mode
where the drain-gate voltage is strongly reverse biased and the conduction channel at the drain end is extremely
thin (“pinched off”). In this mode the drain-source current, I DS , depends mainly on the gate-source voltage but it is
also a function of the drain-gate voltage. The latter effect is small but not negligible. According to a fairly basic
model, to a good approximation [1]: -

VGS  VP  I DS  I DS VGS ,VDG   k VGS  VP 

2
with k and VP approximately constant
and
VGS  VP  I DS  0

Where: VGS  VG  VS and VDG  VD  VG

Both VGS and VP are numerically negative. The small signal analysis is usually defined by: -

I DS I
dI DS  dVGS  DS dVDG
VGS VDG

The first partial derivative defines the small signal forward transconductance and the second defines the small
signal output conductance (in data sheets often referred to as gFS and gOS respectively): -

I DS I DS 1
Define parameters: g FS  gOS  
VGS VDG RDO

g FS and gOS are themselves functions of the drain-source current. RDO defines the drain output resistance and is
analogous to the collector output resistance as in the case of BJTs. The parameters k , VP , g FS and g OS depend on
the type of device and also vary from device to device of the same type. Fortunately there are some fundamental
relationships between them which allow some useful design rules of thumb. The main one is that characteristics
match very closely for devices of the same type when operated at precisely the same current [1]. One need not pay
top dollar to achieve excellent performance with either an integrated pair or with two single transistors glued
together.

An equally valid form of the equation, preferred by this author, employs the (numerically positive) variable source-
gate voltage (VSG).
VSG  VP  I DS  k VSG  VP  VSG  VP  I DS  0
2
and

Take the square root for the linear equation: I DS  k VSG  VP 

The other mode of operation is as a voltage controlled resistor (VCR). This has a potential benefit which is
explored in section 4.

1. Part 5, monograph 4: “JFET Theory.”

2
 Part 5: Monograph 3

2. The long tail pair

The most frequently used JFET pre-amplifier is the differential “long tail pair” of matched low noise transistors
operated in the pinched-off mode. The differential structure and constant current source ensure a high level of
rejection of common mode voltage at the inputs and power supply variations. DC offset is not particularly accurate
or stable, with respect to temperature, compared to a BJT matched pair or even a low cost op-amp. An input offset
of 10mV is considered a good one.

The JFET high input impedance is easily damaged by electrostatic discharge and low leakage back-back diodes are
recommended for protection. These are basically JFETs with drain and source connected together to form the
cathode.

+15V

2×RD

IDS IDS VOUT

U430
or similar
VIN ≈ 0V V

Current regulator 2IDS

-15V

Fig. 2.1 Outline schematic of a long-tail pair.

As a rule of thumb the gain is, to a good approximation (see appendix section A1): -

dVOUT R R 1
G  g FS RDE with RDE  D DO and RDO 
dVIN RD  RDO gOS

g FS is the forward transconductance of the JFET and RDE is the effective drain resistance (the component resistance
in parallel with the drain output resistance, RDO).

The choice of operating current depends mainly on the type of JFET. Generally speaking a higher current results in
lower noise voltage and higher noise current but not in simple inverse proportion as with BJTs. The best way to
match source resistance is by selecting the right type of JFET (larger area devices have lower noise resistance). The
best choice of operating current is usually a trade-off between voltage noise and stage gain. Whereas higher current
results in higher forward transconductance the gain is lower – the drain resistors can be higher. See the monograph
“JFET theory” for more detail [1].

Other parameters, on the other hand, are quite well matched, especially when the DC is trimmed (precisely matched
operating current) and a common mode rejection ratio of over 100dB (105) is readily achieved.

Typical values for a dual matched JFET (U430) are: -

Current (mA) VN nV Hz  IN  fA Hz  PN (W) RN (MΩ) TN (K)

1 4 ≈1 (@25ºC) 4×10 -24
4.0 0.07

1. Part 5, monograph 4: “JFET Theory”. See section 2.6.

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High Accuracy Electronics
3. A differential source follower

An alternative to the long tail pair is a differential source follower. The main advantage is speed (no Miller
capacitance) and a bandwidth of many MHz The main disadvantage is low gain (approximately ×1) and the need
for a low noise amplifier stage to follow. There are, however, a number of applications where a source follower
pre-amplifier could be a suitable add-on extra. In a multi-purpose instrument, for example, with a low noise BJT
front end, the source follower could be switched in for a high source impedance range.

+15V

VIN ≈ 0V
U430
or similar
VOUT

2×RS

-15V

Fig. 3.1 A differential source follower

The input impedance is extremely high and the output resistance is moderately low – suitable for input to a BJT
matched pair. According to Ohm’s law and JFET theory [1], for each transistor: -

dVS  RS dI DS and dI DS  g FS dVGS  gOS dVDG

The change in drain-gate voltage has a very small affect on the gain: gOS  0  dI DS  g FS dVGS

dVS g FS RS
With a little algebra, for each JFET: dVGS  dVG  dVS  G  
dVG 1  g FS RS

The output resistance is also easy to calculate. If one holds the input constant and then takes a small bit of extra
current from the source, the source voltage must fall according to: -

dI DS  g FS dVGS  g FS dVG  dVS    g FS dVS  RSO  

dVS 1

dI DS g FS

The result is typically between 100Ω and 1kΩ. With a following input capacitance of a few pF a bandwidth in
excess of 100MHz is easily achieved.

A differential follower can also be used on its own, if accuracy and stability of the gain is not critical (e.g. as the
pre-amp of a null detector). It can also be used as the first stage, inside the loop, of a composite op-amp, employing
a low noise (BJT input) operational amplifier with negative feedback. A source follower would be particularly
useful in the front end of a high speed charge amplifier, operating at a frequency of 160kHz or even higher, as part
of a high speed capacitive transducer signal conditioner. Whereas such measurement systems are only moderately
accurate (to 0.01% at best) they are often key subsystems in much higher accuracy measurement and control
systems (e.g. nano-positioners and high accuracy optical instruments).

With a gain of only ×1 the stability of a feedback system is readily achieved.

1. Part 5, monograph 4: “JFET Theory.”

4
 Part 5: Monograph 3

4. An ultra-low input current pre-amplifier

The input (leakage) current of a JFET, in pinch-off mode, is largely dependent on the drain-gate voltage as well as
temperature. Unfortunately there is very little information available on gate leakage in voltage controlled resistance
(VCR) mode. A typical datasheet contains the following: -

Fig. 4.1 Gate leakage current versus drain-gate voltage (J112 courtesy Siliconix)

It should be possible to operate a JFET pair in VCR mode with much reduced drain-gate and source-gate potential
differences, resulting in very much reduced leakage current and, therefore, much lower current noise. The J112, for
example, is a symmetrical device and, if the drain and source are maintained at equally positive and negative
potentials, relative to the gate, the net leakage current should be extremely small. A reasonably good model is an
ideal (zero leakage) JFET with two very large resistors (typically >1012Ω) with leakage currents of the order
<100fA (10-13A) through each. In practice this would require the transistor package to be extremely clean (degrease
with fresh cotton wool and methylated spirits) with complete screening/guarding and a very good insulator (PTFE
or sapphire) for the gate terminal post [1].

VD

VIN

VS

Fig. 4.2 A symmetrical JFET model

The resistors are temperature sensitive as well as non-linear, depending on the potential differences. It should be
possible, however, to employ negative feedback to adjust the drain and gate DC potentials on a relatively long
timescale, relative to the operating frequency, with guaranteed loop stability over a useful range of conditions.

It is also possible to arrange for the drain and source voltages to “follow”, almost exactly, the gate AC potential
thus “bootstrapping” the drain-gate and source-gate resistances and capacitances [2].

1. Yeager, John. & Hrusch-Tupta, Mary Anne et al: “Low Level Measurement”, 5th edition.
Keithley Instruments Inc. For more practical tips on very high resistance and very low current measurements
see sections 2 and 4.
2. Part 2, monograph 3: “An ultra-high input impedance high-pass filter”

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High Accuracy Electronics
A practical circuit could be a differential cascode stage with a matched (low noise) BJT pair. This is preferable to a
long-tail pair (operated in the VCR mode) as the gain is much greater (see appendix A3). The resistors (R1 and R2)
determine the drain-source operating voltage (typically 0.1V). The diode compensates for the base-emitter voltage
and its variation with temperature. If the BJTs are perfectly matched the voltage developed across R2 is then
imposed across both JFETs. The value of resistor, R3, is chosen so that the drain and source voltages are
approximately equal and opposite relative to 0V (VC = 0V). Fine adjustment is then provided by the control voltage.

The 100kΩ potentiometer allows for a slight mismatch between the JFETs (up to 15mV difference in pinch-off
voltage). The input JFET must have the lower “on” resistance when tested with a meter (VGS = 0V). The
potentiometer is then set for zero output when the input gate is connected to 0V.

The input capacitors represent the ground capacitance, including the input capacitance of the JFET and a transducer
capacitance/reference and/or the feedback capacitance if configured as a charge amplifier.

100nF +15V
RC R1 RC

VOUT
VC K

Diff amp

R2 100k
100k
VIN ≈ 0V
0V

100Ω 10μF
Total input VS VC
capacitance, C
R4
R3
100nF -15V

Fig. 4.3 A differential cascode input stage with gate leakage control

If the JFETs, BJTs and collector resistors are perfectly matched the output should not change, at least not
instantaneously, when the control voltage is adjusted. If, however, there is a net leakage current the potential at the
gate of the input JFET will gradually ramp up or down resulting in a slowly varying output. This “DC” component
can then be fed back, with a suitable dynamic response, to automatically adjust the leakage current and maintain the
gate voltage at 0V. The adjustment range of VS is small and depends on the ratio of R3 and R4 (typically a control
signal of ±10V is reduced to ±0.1V). A reasonably good model would be, in the (very low frequency) complex
representation s  j  : -

RS C VE
VIN VOUT
G
R

VS H(s)

Fig. 4.4 The pre-amp feedback model

At the operating frequency the signal passes through the capacitor, is amplified, and appears at the output.

6
 Part 5: Monograph 3

 1 
The most basic feedback network is an integrator, based on an op-amp  H s     . The differential amplifier
  I s 
must be connected the right way round to ensure that the feedback is negative.

The JFETs are, in effect, constant current sources (inputs constant) and the biasing resistors (R1 and R2) can be
relatively large – the JFET source node is a high resistance point. The attenuation of the control signal is
determined, therefore, almost entirely by resistors R3 and R4. The effective time constant of the integrator is
increased so that with integrator components RI and C I : -

R3  R4
R4  100R3   I  RI CI  101RI CI
R3

For the model (see fig. 4.4) with negligible source resistance RS  0 and   RC : -

G  1 
H s    VIN  VS  VIN 
1 G
 VS   VE   
Is Is Is  1  s 

 G  G  s 
 VS 1      V
  I s1  s    I s  1  s  IN

VS  Gs
The transfer function, from VIN to VS is, therefore: 
VIN G   I s   Is 2

Divide top and bottom by G and the result is a second order band-pass characteristic: -

VS  s 
 with  I  I
VIN 1   I s   Is 2
G

This time the effective time constant of the integrator is reduced - by the preceding gain. In standardised and
normalised form s  j N  : -
VS  ks

VIN 1  2s  s 2
1 1  I
The natural frequency is:  and damping ratio: 
 I 2 

The constant k is related to the peak gain:

VS
s  jN       k
VIN  I 2

Loop stability depends on the damping ratio. A reasonable compromise is slight underdamping   0.5 so that the
time constants need to be approximately the same.

For stable operation, therefore:  I  

A large source resistance will also affect stability, limiting the range of applications. There is little point in detailed
analysis as the leakage resistance is highly unpredictable. It will be necessary to experiment with a prototype.

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High Accuracy Electronics
The transfer function from VIN to the main signal output is: -

VOUT 1 VS  Is 2
 
VIN H s  VIN 1   I s   Is 2

As expected this is a second order high-pass filter with the same natural frequency and damping ratio as above.

From the monograph “JFET theory” the current in VCR mode is [1. See section 2.5]: -

VDS  VG  RC dVG
VD  VS  0  I DS  1    dVC  RC dI DS  VDS
R0  VP  R0 VP

VDS dVC R I
By definition, when VG  0V :  I DS    C DS
R0 dVG VP

The overall gain, including differential amplifier (gain = K) is, therefore: -

dVOUT R I
G  K C DS
dVG VP

4.1 Example calculation

The J112 has an “on” resistance of about 50Ω and a reasonable choice of operating current is 2mA each side. When
stabilised this would result in drain and source voltages of ±50mV relative to the gate (0V). With a drain-gate and
source gate resistances of the order 1012Ω the resulting leakage current is 50fA in each (at 20ºC). This is
comparable with the best MOSFETs with the advantage of lower noise voltage (MOSFETs tend to be noisy). Fine
adjustment, by the action of feedback, then reduces the net average current to near zero, limited only by the leakage
current of the input capacitors.

The input capacitor could be constructed with PTFE or, even better, sapphire insulators with leakage currents at the
limit of measurement (≈10-17A or 10 atto-amps). According to theory the random fluctuation in each of the leakage
currents (current noise) is predicted to be [1. See section 3]: -

 I N  2eI L B and I L  50 fA  I N  0.13 fA Hz

Where e  1.60  1019 C is the quantum of electrical charge (i.e. on a proton) and B is the bandwidth in Hz.

A typical application would have an input capacitance of 10pF. This could be a very low leakage component
capacitor or capacitance transducer. The input capacitance represents the total capacitance at the input, including
ground capacitance and any feedback capacitance, as in the case of a charge amplifier. The resulting time constant
 
is around 10s R  1012  and a natural frequency of 0.16Hz (high-pass cut-off). This should facilitate operation at
half the power supply frequency (25 or 30Hz) or even lower.

The BJTs should be able to operate correctly with a collector-base voltage as low as 5V, allowing a DC voltage
drop across the collector resistors of 10V and collector resistances of 5kΩ. With a pinch-off voltage of -2V the
JFET gain is approximately ×5: -
RC I DS
5
VP

1. Part 5, monograph 4: “JFET theory”.

8
 Part 5: Monograph 3

The gain of the differential amplifier needs to be sufficient for the noise contribution of the following stage to be
negligible. A convenient value is K = 20 so that the overall gain, including JFET stage, is ×100 and compensates
for the effect of the attenuator on the feedback time constant. The actual integrator component values then
determine the time constant.

The voltage noise contribution from the collector resistors is negligible compared to that generated by the noise
current of the JFETs and the noise voltage added by the BJTs. According to theory the “Johnson” current noise and
voltage noise generated by a resistor are [1. See section 2.4]: -

4kTB
IS  and VS  4kTRS B
RS

Where k  1.38  1023 J K = Boltzmann’s constant, T  is the absolute temperature ( T  293K at 20ºC) and
B  Bandwidth in Hz. With a drain-source resistance of 50Ω the noise current is: -

I S  18 pA Hz This flows through 5kΩ  VN 1  91nV Hz at the collectors.

The noise generated by the collector resistor, on the other hand, is negligible: VN 2  9.1nV Hz

The noise of the BJT, referred to the input, at 2mA operating current, is of the order 1nV Hz (SSM2010). This
is then amplified, by approximately the ratio of the collector to the emitter resistance (×100), also resulting in a
noise component of around VN 3  100 nV Hz . The three noise sources are statistically independent and combine
as the root mean square (RMS) [2. See appendix A1]. Also, the same noise from the other side combines to
increase the overall noise by a factor of 2

VT  VN21  VN22  VN23  ...  2  VT  189 nV Hz

The equivalent voltage noise, referred to the input (divide by the voltage gain), is very approximately
VN  40 nV Hz and significantly more than one would expect in the pinched-off mode (typically 5 nV Hz ).

As a ball-park estimate the noise resistance of the pre-amp is the ratio of the noise voltage and noise current: -

VN 40 nV Hz
RN    308M
I N 0.13 fA Hz

Suitable values for R2 and R1 are 1kΩ and 150kΩ respectively, consuming a modest extra 0.1mA of supply current.
The noise voltage developed by R2 and R3 is common to both sides and is easily rejected by the differential
amplifier. Suitable values for R3 and R4 are: -

14.95V
R3   3.65k  R4  365k
4.1mA

A fixed and variable resistor, connected in series, is probably the best solution for R3.

Finally, given the unpredictability of the integrator time constant required, it could be argued that a more adaptive
control loop, consisting of a microcontroller (with ADC and DAC), would be preferable. The algorithm could
continuously analyse the response of the loop and self optimise accordingly. See, also, section 5.4 and [3].
1. Part 5, monograph 4: “Low noise BJT pre-amplifiers”.
2. Part 5, monograph 1: “Null detectors – the basics”.
3. Part 2, monograph 3: “An ultra-high input impedance high-pass filter”
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High Accuracy Electronics
5. Charge amplifiers

5.1 Op-amp based charge amplifiers

The main low noise JFET circuit of interest in high accuracy electronics is a charge amplifier, as part of a null
detector in a capacitance bridge or signal conditioner [1], [2] and [3]. Excellent performance is possible even with a
low cost JFET input op-amp. Numerous types are available with typical RMS input noise of 12nV Hz .

The circuit is very simple – basically an inverting amplifier [4] with input capacitors (typically a variable and
reference capacitor) and a feedback capacitor. The action of feedback is to maintain the inverting input at 0V
(“virtual earth”). The ground capacitance usually consists of coax cable (connecting the transducer to the charge
amplifier) plus stray and input capacitance of the op-amp and capacitance in the transducer. With zero signal
voltage across no current flows through and its existence does not affect the measurement, apart from contributing
to the noise gain. For best noise performance the feedback capacitor should be smaller than the total ground
capacitance, subject to the requirement for closed loop bandwidth and negligible contribution due to noise current.
A smaller feedback capacitor means higher gain but lower bandwidth and more phase error at the operating
frequency. The feedback resistor provides a route for the DC leakage current and needs to be very large to ensure
low phase error and negligible noise current (typically 1GΩ with 10pF or 100pF at 1.6kHz). The precise values of
the feedback resistor and capacitor are not critical and DC at the output is not usually a problem. Much more
important are the provision of an overall screen and the avoidance of earth loops [5].

+15V
RF 100nF

CF

VV CR LF356

VOUT
VR

CT
CG 100nF

0V
-15V

Fig. 5.1.1 An op-amp based charge amplifier

1. Part 1, monograph 3: “Rotary capacitive displacement transducer.”

2. Part 1, monograph 4: “Linear capacitive displacement transducers.”
3. Part 1, monograph 5: “Variable gap displacement transducers”.
4. Part 4, monograph 1: “High gain blocks”. See section 3.
5. Part1, monograph 2: “High accuracy single capacitors”. See section 2.

10
 Part 5: Monograph 3

Stability and noise performance depend on the size of the ground capacitance, CG. The feedback factor, at the
operating frequency, is determined by the feedback capacitor and the ground capacitance in parallel with the total
input capacitance, CT + CR. The latter is usually negligible and the feedback factor is, to a good approximation: -

CF C
Feedback factor: F  F
CT  CR  CG CG

The closed loop upper frequency response is reduced, compared to the open loop bandwidth of the op-amp by the
feedback factor: -
1
Closed loop bandwidth: CL  FB 
 CL

Where  B is usually referred to as the unity gain frequency or gain-bandwidth product.

Typically the op-amp bandwidth is 5MHz (LF356). With a ground capacitance of 100pF (1m of coax cable) the
feedback capacitor can be as low as 10pF (F ≈ 0.1) in which case the closed loop bandwidth is 500kHz and the
phase shift is negligible at an operating frequency of 1.6kHz.

Similarly, the feedback resistor also limits the lower frequency bandwidth. The overall result is a band-pass
characteristic with widely separated poles. It is shown elsewhere [1], and in many elementary texts, that the band-
pass characteristic, with respect to the VR input, can be described with a transfer function of the form s  j  : -

 H s  
TR s  
VOUT Z
 2   
VR Z1  H s    s  

Where Z1 and Z 2 are the input and feedback impedances respectively. H s   1  B s is the open loop characteristic
of the op-amp (an integrator) and  s  is the reciprocal of the feedback factor.

CT  sRF CF   1 
 TR s        
CF  1  sRF CF   1   CL s 

1 
The net phase shift is approximately:  
RF CF CL

One can consider the op-amp noise voltage to be in series with either input. With zero input voltages the equivalent
circuit is a non-inverting amplifier: -

RF

CF
VOUT

LF356
VN
CT + CR + CG

CG + 0V
CG + Fig. 5.1.2 Voltage noise model

1. Part 4, monograph 1: “High gain blocks”. See section 2.

11
High Accuracy Electronics

CT  CR  CG 1
The noise gain is, therefore: GN  1  
CF F

Note that the noise gain is independent of frequency.

For an LF356 the noise voltage is typically 12nV Hz (RMS) and, with a feedback factor of 0.1, the noise level
at the output would be 132nV Hz .

The current noise model consists of current sources due to the op-amp and the feedback resistor. The action of
feedback (virtual earth) ensures that the net noise current flows only through the feedback capacitor.

IN2
22

CF IN

VOUT
IN1 LF356

CT + CR + CG

CG + 0V
CG + Fig. 5.1.3 Current noise model

The current sources are statistically independent so that the RMS net current flowing through CF is: -

I N  I N2 1  I N2 2

IN
The noise at the output is, therefore: VOUT  (RMS due to noise current)
CF

Note that the noise at the output now depends on the magnitude of the capacitive impedance and, therefore,
frequency. Ideal noise matching occurs when the contributions from the noise voltage and noise current are the
same: -
 C  CR  CG  I VN 1
VN 1  T   N  
 CF  CF I N  CT  CR  CG  CF 

One could interpret this as noise resistance match to the magnitude of the total capacitive impedance connected to
the virtual earth node. In practice the noise current of the feedback resistor dominates and it is not practical to trade
off voltage noise against current noise.

For example: The noise current of a 1GΩ resistor at room temperature (300K) is 4 fA Hz and higher than a
suitable op-amp or matched pair (typically  1 fA Hz ). The impedance of 100pF capacitance at 1.6kHz is 1MΩ
and the contribution to noise at the output is only 40nV Hz . This is less than the contribution due to noise
voltage.

Rule of thumb: One may as well choose a low noise JFET op-amp with a noise resistance a little above the
ideal.

12
 Part 5: Monograph 3

5.2 A charge amplifier with long tail pair front end

The best noise performance is achieved by adding a matched pair at the front end of a reasonably low noise op-amp
to make a composite op-amp. Typical values for a dual matched JFET (U430) are: -

Current (mA) VN nV Hz  IN  fA Hz  PN (W) RN (MΩ) TN (K)

1 4 ≈1 (@25ºC) 4×10 -24
4.0 0.07

The extra gain and phase shift of the long tail pair (LTP) can result in instability, depending on the feedback factor.
A snubber (series resistor and capacitor) across the drains may be necessary.

A DC offset trim is included which can correct for up to 15mV of offset. The 100Ω resistor may contribute a small
amount to the noise and a large capacitor (e.g. Tantalum) is added to reduce the AC impedance to 10Ω at 1.6kHz.
Unlike BJT offset trim it is better to keep the drain resistors accurately matched so that, with zero differential
output, the pair are operating at precisely the same current and their characteristics are, therefore, better matched.

Both inputs are maintained at close to 0V so common mode rejection is not an issue and a BJT constant current
source may be a bit of overkill. The balanced structure and current source do, however, also provide a high level of
power supply rejection. With a low noise power supply a JFET based current regulator or even a resistor would
suffice. Otherwise see the monograph “Low noise BJT pre-amplifiers” for more detail.

+15V
100nF
2×RD
CS

VOUT

RS 100k
100k
VIN ≈ 0V
100Ω 0V

2IDS 10μF
100nF
-15V

Fig. 5.2.1 A composite op-amp with a long tail pair

5.2.1 Example calculation

The author found, in a batch of ten, seven single JFETs (low cost, low resistance types J112) with excellent noise
characteristics (typically 5nV Hz ). Two of those had a closely matching pinch-off voltage (10mV difference)
and very closely matching gain characteristic. The models used in text books and application notes are: -

2
 V 
  k VGS  VP 2  k  DSS
I
I DS  I DSS 1  GS
 VP  VP2

The parameter k is the most useful but, unfortunately, it is not provided in data sheets. The values obtained by
linear regression were 7.89 × 10-3 and 7.83 × 10-3 respectively (dimensions: amps/volt2) – a match of about 1%.
Similarly the values of pinch-off voltage were calculated by extrapolation to zero drain-source current.

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High Accuracy Electronics

Fig. 5.2.1.1 A batch of J112 JFETs

I DS
The gate-source voltage is: VGS   VP
k

I DS
The forward transconductance is:  2k VGS  VP   2 kIDS
VGS

For low noise the recommended operating current is about 1mA (not critical). The average gate-source voltage
required is, therefore: -
1
VGS   2.056  1.70V
7.86

The gates are operating at about 0V so that the source voltage is +1.7V.

The average forward transconductance is: g FS  2 7.86  106  5.61mS

(This is consistent with the data sheet that states a typical value of 6mS)

To operate well within the pinched-off mode the drain-gate voltage needs to be at least twice the pinch-off voltage.
Five volts should suffice so one can use a pair of 10kΩ drain resistors (0.1% tolerance, scavenged from an old
decade box). The data sheet is not very helpful with drain output resistance (specified as 25μS at 1mA but a drain-
gate voltage of 20V). The effective drain resistance (component resistance in parallel with the drain output
resistance) is, therefore, 20% lower than the actual resistance: -

RDO RD 40k  10k

RDE    8k
RDO  RD 40k  10k

The gain is, therefore, approximately: G  g FS RDE  5.61mS  8k  45

14
 Part 5: Monograph 3

A typical application requires, for example, a ground capacitance in the range 100 – 500pF (extra long cable) and,
to retain a reasonably high frequency response, the feedback capacitor is chosen to be 100pF (1% polystyrene,
scavenged from an old capacitive decade box). The feedback factor can be as high as 0.5 (100pF feedback into
100pF ground capacitance) and one needs to reduce the gain, at high frequency, inside the feedback loop by an
extra factor of 22.5 in order to retain stability (feedback factor times the extra gain). To be on the safe side I
reduced the gain by 25 and the snubber resistor needs to be a factor of 12.5 lower than the drain resistors (think of
two snubber resistors in series with the centre connected to +15V). The result is 640Ω and, to be on the safe side
again (it’s not critical), I used a 620Ω as I had plenty in stock.

The main aim of the snubber is to reduce the gain of the long tail pair (LTP) to unity well before the op-amp gain
passes through 0dB. The LF356 has lots of phase margin to spare and experiment (and analysis) shows that the
LTP gain must start to level out to unity at a frequency of one fourth the op-amp unity gain frequency (5MHz).

1
Zero frequency, at which the long tail pair (LTP) gain levels out: f2   1MHz
2RS CS

1
The snubber capacitance needs to be, therefore: CS   260 pF
2RS f 2

Once again this is not critical and a component value of 270pF should be satisfactory.

1
Pole frequency, at which the LTP gain starts to fall: f1   30kHz
2 2 RDCS

This is well above the most frequently used operating frequency (1.6kHz) and the extra open loop gain at low
frequency helps with accuracy and low phase error. The resulting charge amplifier is, in fact, usable up to 16kHz.

Clearly there is scope for experimentation if one uses a different op-amp (e.g. a much higher gain-bandwidth
product) and requires more or less stability margin. For more detail and another example on snubber design and
stability see the monograph “Low noise BJT pre-amplifiers” [1].

For higher frequency of operation (e.g. 1MHz) the op-amp can be replaced by an uncompensated RF amplifier (e.g.
the ubiquitous μA733). To ensure stability the snubber resistor is made much smaller or eliminated altogether so
that the LTP provides the dominant pole. Lower drain resistors and higher operating current ensure bandwidth up
to. Say, 50MHz. The size of the capacitor depends on the feedback factor and some experimentation with stability
margin and layout may be necessary. With modern superfast (internally compensated) op-amps, however, there is
another way…

1. Part 5, monograph 2: “Low noise BJT pre-amplifiers”. See section 4.4.1.

15
High Accuracy Electronics
5.3 A charge amplifier with source followers.

For the ultimate high speed a charge amplifier can be implemented with a differential source follower and low
noise high speed op-amp. The source followers do not add extra gain inside the loop and loop stability is simply an
issue of feedback factor. The CLC426 (230MHz unity gain and 1.6nV Hz ), for example, has internal
compensation for stable operation with a feedback factor up to 1.

+15V
VIN ≈ 0V

CLC426
VOUT

2×RS

-15V

Fig. 5.3.1 A composite op-amp with source followers

Such a design is not for the faint heart and considerable RF knowledge and understanding is required (plus some
really good test kit, especially the oscilloscope). Also, this is off at a tangent and the reader, if really interested,
should contact the author for further advice.

5.4 An ultra-low leakage charge amplifier

With an adaptive (microcontroller controlled) ultra-low input current pre-amp (see section 4) it should be possible
to construct a very sensitive charge amplifier. The basic idea is to allow the leakage current control loop to
stabilise, with the input disconnected, before switching to measurement mode. In measurement mode the control
loop is disabled, holding the zero leakage condition, and the input is connected via ultra-low leakage (glass
encapsulated) reed relays. The reeds need to be well screened from the activating coils to prevent charge injection.

CF

VOUT
1
Pre-amp 1
s
VC μC
0V

Fig. 5.4.1 An ultra-low leakage charge amplifier

The differential amplifier in the pre-amp can be given a first order low-pass characteristic. Extra gain in the loop is
then provided by a one-plus integrator. This has the same time constant as the diff-amp so that the combined open
loop gain is that of an integrator, equivalent to an op-amp. A second one-plus-integrator may be added, equivalent
to a two-stage high gain block, for higher accuracy [1].

With such a charge amplifier it should be possible to measure average currents as low as a few atto-amps (< 100
electrons/s). If you are interested in building and testing a prototype please contact the author.

1. Part 4, monograph 1: “High gain blocks”.

16
 Part 5: Monograph 3

6. Transducers incorporating a charge amp or single JFET

For the ultimate noise performance the charge amp (or single JFET), feedback capacitor and resistor can be
incorporated within the transducer (or physically close) to minimise ground capacitance [1]. Noise current becomes
an issue and the feedback resistor needs to be very large (typically > 1GΩ). Care must be taken to keep the op-amp
or JFET cool as leakage current doubles for every 11 degrees. Current noise increases in proportion to I L .

A surface mount style op-amp takes up little space and presents no interfacing problems as the output impedance is
very low.

Virtual earth
+/-15V supply

sensor electrode
output

JFET op-amp
active guard
guard screen (0V)

Epoxy resin earthed screen/casing

Fig. 6.1 A variable gap transducer with built-in charge amplifier [1]

The drain output of a single JFET in pinched-off mode, on the other hand, presents much higher impedance and an
active guard (driven coax screen) is recommended.

The best solution is to operate the JFETs in voltage controlled resistor (VCR) mode with leakage current control.
This mode eliminates the need for a high value resistor. The on resistance is typically 50Ω and interference ceases
to be a problem. Such a design, however, would require a very low noise stage to follow and the cascode circuit is
recommended. See section 4.

Screen
VIN C
Pre-amp

VOUT
Fig.6.2 A single JFET in VCR mode in a special high-pass filter [2]

In a null-balance bridge system it is also possible to eliminate the feedback capacitor (i.e. not a charge amplifier).
The bridge can still be balanced to a null though the gain of the pre-amp stage is less well defined due to the stray
capacitance unless the screen is actively driven. Once again, the special high-pass filter circuit is recommended [2].

For further advice please contact the author.

1. Part 1, monograph 5: “Variable gap capacitive displacement transducers”. See, for example, section 2.1.
2. Part 2, monograph 3: “An ultra-high input impedance high-pass filter”.

17
High Accuracy Electronics
Appendix: Long tail pair theory

A1. Voltage gain

The analysis is simplified if one takes advantage of the symmetry of the circuit. Consider equal and opposite
infinitesimal changes to the inputs. The increase in current down one side is matched by a decrease in the other and
the source voltages remain constant. The gain must be the same if one of the inputs is held constant (e.g. in a
charge amplifier one input is connected to 0V).

+15V
2×RD
±dVD
+dIDS -dIDS VOUT
+dVG

-dVG
VS

Current regulator 2IDS

-15V

Fig. A1.1 Model for gain calculation

By definition, in the pinched-off mode: -

dVDG
dI DS  g FS dVGS  with dVS  0  dVGS  dVG  dVS  dVG and dVDG  dVD  dVG
RDO

g FS  Forward transconductance and RDO  drain output resistance (reciprocal of output conductance)

dVD  dVG
 dI DS  g FS dVG 
RDO

RD dI DS  dVG
By Ohm’s law: dVD   RD dI DS  dI DS  g FS dVG 
RDO
With a little algebra: -
 R  dV g FS RDO dVG  dVG
 1  D dI DS  g FS dVG  G  dI DS 
 RDO  RDO RDO  RD

dVOUT dVD R dI g R R  RD RD
The voltage gain is:    D DS   FS DO D   g FS RDE 
dVIN dVG dVG RDO  RD RDO  RD

RDO RD
RDE   Effective drain resistance (RD in parallel with RDO)
RDO  RD

RD
Usually: g FS RDE  1 and  1  G  g FS RDE
RDO  RD

18
 Part 5: Monograph 3

A2. Common mode rejection ratio

A2.1 Mismatched drain resistors

If one increases the voltage at both inputs dVG  and the total current remains constant then the voltage, VS, at the
current source increases by the same amount. In practice the current source has a finite output conductance,
equivalent to a large resistor, ROS, in parallel with an ideal current source. The current will change by a small
amount and there is a very small difference between dVG and dVS: -

dVS dVG
dI  and dVS  dVG  dI 
ROS ROS

If one assumes that the JFET pair are perfectly matched then the change in current is shared equally. If the
resistances are exactly the same the result is a change in the output common mode but not the difference. The
resistors have a tolerance RD  RD  , however, and, in the worst case (one resistor higher and the other lower than
nominal), the difference between the outputs would change by: -
dI dVG
RD  RD  dVOUT  2RD  RD
2 ROS
The differential gain is, approximately (see previous section): G  g FS RDE

The CMRR is usually defined as the differential gain divided by the common mode gain. To a good approximation,
therefore: -
dVOUT R
G  g FS RDE  OS
dVG RD

The effective drain resistance is usually not much lower than the drain resistor (component) and, therefore: -

RD
RDE  RD  CMRR  g FS ROS 
RD

At a relatively high operating current (1 – 10mA) the forward transconductance is at least 1 - 10 mmho (milli-
Siemens) and a typical output resistance of a BJT current source is at least 10 7Ω. The common mode rejection ratio
is, therefore, a minimum 106 (120dB) with 1% tolerance resistors.

A2.2 Mismatched JFETs

In practice the CMRR is limited by the matching of the JFETs. The effect of an infinitesimal change in drain
voltage is negligible (second order) and to a very good approximation, therefore: -

dVDG
dI DS  g FS dVGS   g FS dVGS
RDO

The change in current is the same but the balance is altered slightly by the mismatch in JFETs.

dVS
dI   dI1  dI 2 with dI1  g FS 1dVGS and dI 2  g FS 2dVGS
ROS

The changes in current are very nearly the same: -

dVS dVS
dI1  dI 2 and dI   dVGS 
ROS 2 g FS ROS

19
High Accuracy Electronics

The change in gate-source voltage is very much less than the change in gate voltage (the source voltage “follows”
the gate common mode). The change in the output is: -

RD g FS
dVOUT  RD (dI1  dI 2 )  RD g FS dVGS  dVS
2 g FS ROS

dVOUT R g
The common mode gain is, therefore: dVS  dVG   D FS
dVG 2 g FS ROS

The CMMR is usually defined as the differential gain divided by the common mode gain: -

dVOUT 2g R
G  g FS RDE  FS OS
dVG g FS RD

The effective drain resistance is usually not much lower than the drain resistor (component): -

g FS
RDE  RD  CMRR  2 g FS ROS 
g FS

As before the product g FS ROS  104 and a mismatch of no more than 1 or 2% is possible so that a CMRR of 106
(120dB) is readily obtained.

With charge amplifiers both inputs are firmly anchored at local PSU 0V and a high CMRR is usually overkill – a
JFET current regulator or resistor to supply the current is usually sufficient.

The matched pair (U430) datasheet quotes the following, re: matching: -

20
 Part 5: Monograph 3

A3. The long-tail pair in VCR mode

With suitable drain resistors and operating current it is possible to operate in the voltage controlled resistor mode.
One possible application is an ultra-low leakage current amplifier (see section 4), with drain and source voltages
equal and opposite, relative to the inputs (0V). The main difference, compared to the differential cascode
recommended there, is a much lower voltage gain, requiring the following stage to have a very low voltage noise
and low noise resistance (i.e. a noise matching transformer [1]).

Here again one can take advantage of the circuit symmetry. Consider equal and opposite changes at the inputs.

+15V

2×RD

+dIDS ±dVD -dIDS VOUT

+dVG

-dVG
VS
RD/2
2IDS

-15V

According to theory the drain source resistance is [2]: -

 VP  dVG RDS
VD  VS  0V  RDS  R0    dRDS  R0VP  dV
 VP  VG  VP  VG  VP  VG G
2

R0
At VG  0 , therefore:  dRDS  dVG (N.B. VP is numerically negative)
VP

The current remains approximately constant, being determined mainly by the power supply voltage and the drain
resistance.
V
RD  RDS and VD  VS  0V  I DS 
RD

The change in drain voltage is determined, therefore, almost entirely due to the change in drain-source resistance: -

dVD I DS dRDS I DS R0
G  
dVG dVG VP

With a typical RDS resistance of 50Ω and pinch-off voltage of -2V and an operating current of 2mA (c.f. example
calculation, section 4.1) the gain is: -
G  0.05

1. Part 3, monograph 5: “Noise matching transformers”

2. Part 5, monograph 4: “JFET theory”. See section 2.5

21