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Logic_Design_II

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shabarish babu
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ANALOG AND DIGITAL ELECTRONICS

[As per Choice Based Credit System (CBCS) scheme]


(Effective from the academic year 2017 -2018)
SEMESTER - III
Subject Code 17CS32 IA Marks 40
Number of Lecture Hours/Week 04 Exam Marks 60
Total Number of Lecture Hours 50 Exam Hours 03
CREDITS – 04
Module -1 Teaching
Hours
Field Effect Transistors: Junction Field Effect Transistors, MOSFETs, Differences between JFETs 10 Hours
and MOSFETs, Biasing MOSFETs, FET Applications, CMOS Devices. Wave-Shaping Circuits:
Integrated Circuit(IC) Multivibrators. Introduction to Operational Amplifier: Ideal v/s practical
Opamp, Performance Parameters, Operational Amplifier Application Circuits:Peak Detector
Circuit, Comparator, Active Filters, Non-Linear Amplifier, Relaxation Oscillator, Current-To-
Voltage Converter, Voltage-To-Current Converter.
Text book 1:- Ch5: 5.2, 5.3, 5.5, 5.8, 5.9, 5.1.Ch13: 13.10.Ch 16: 16.3, 16.4. Ch 17: 7.12, 17.14,
17.15, 17.18, 17.19, 17.20, 17.21.)

Module -2
The Basic Gates: Review of Basic Logic gates, Positive and Negative Logic, Introduction to HDL. 10 Hours
Combinational Logic Circuits: Sum-of-Products Method, Truth Table to Karnaugh Map, Pairs
Quads, and Octets, Karnaugh Simplifications, Don’t-care Conditions, Product-of-sums Method,
Product-of-sums simplifications, Simplification by Quine-McClusky Method, Hazards and Hazard
covers, HDL Implementation Models.
Text book 2:- Ch2: 2.4, 2.5. Ch3: 3.2 to 3.11.

Module – 3
Data-Processing Circuits: Multiplexers, Demultiplexers, 1-of-16 Decoder, BCD to Decimal 10 Hours
Decoders, Seven Segment Decoders, Encoders, Exclusive-OR Gates, Parity Generators and
Checkers, Magnitude Comparator, Programmable Array Logic, Programmable Logic Arrays, HDL
Implementation of Data Processing Circuits. Arithmetic Building Blocks, Arithmetic Logic Unit
Flip- Flops: RS Flip-Flops, Gated Flip-Flops, Edge-triggered RS FLIP-FLOP, Edge-triggered D
FLIP-FLOPs, Edge-triggered JK FLIP-FLOPs.
Text book 2:- Ch 4:- 4.1 to 4.9, 4.11, 4.12, 4.14.Ch6:-6.7, 6.10.Ch8:- 8.1 to 8.5.
Module-4
Flip- Flops: FLIP-FLOP Timing, JK Master-slave FLIP-FLOP, Switch Contact Bounce Circuits, 10 Hours
Various Representation of FLIP-FLOPs, HDL Implementation of FLIP-FLOP. Registers: Types of
Registers, Serial In - Serial Out, Serial In - Parallel out, Parallel In - Serial Out, Parallel In - Parallel
Out, Universal Shift Register, Applications of Shift Registers, Register implementation in HDL.
Counters: Asynchronous Counters, Decoding Gates, Synchronous Counters, Changing the Counter
Modulus.
(Text book 2:- Ch 8: 8.6, 8.8, 8.9, 8.10, 8.13. Ch 9: 9.1 to 9.8. Ch 10: 10.1 to 10.4)
Module-5
Counters: Decade Counters, Presettable Counters, Counter Design as a Synthesis problem, A 10 Hours
Digital Clock, Counter Design using HDL. D/A Conversion and A/D Conversion: Variable,
Resistor Networks, Binary Ladders, D/A Converters, D/A Accuracy and Resolution, A/D Converter-
Simultaneous Conversion, A/D Converter-Counter Method, Continuous A/D Conversion, A/D
Techniques, Dual-slope A/D Conversion, A/D Accuracy and Resolution.
Text book 2:- Ch 10: 10.5 to 10.9. Ch 12: 12.1 to 12.10
Course outcomes: After Studying this course, students will be able to
 Explain the operation of JFETs and MOSFETs , Operational Amplifier circuits and their application
 Explain Combinational Logic, Simplification Techniques using Karnaugh Maps, Quine McClusky
technique.
 Demonstrate Operation of Decoders, Encoders, Multiplexers, Adders and Subtractors, working of Latches,
Flip-Flops, Designing Registers, Counters, A/D and D/A Converters
 Design of Counters, Registers and A/D & D/A converters
Question paper pattern:
The question paper will have ten questions.
There will be 2 questions from each module.
Each question will have questions covering all the topics under a module.
The students will have to answer 5 full questions, selecting one full question from each module.
Text Books:
1. Anil K Maini, Varsha Agarwal: Electronic Devices and Circuits, Wiley, 2012.
2. Donald P Leach, Albert Paul Malvino & Goutam Saha: Digital Principles and Applications, 8th
Edition, Tata McGraw Hill, 2015
Reference Books:
1. Stephen Brown, Zvonko Vranesic: Fundamentals of Digital Logic Design with VHDL, 2nd Edition, Tata
McGraw Hill, 2005.
2. R D Sudhaker Samuel: Illustrative Approach to Logic Design, Sanguine-Pearson, 2010.
3. M Morris Mano: Digital Logic and Computer Design, 10th Edition, Pearson, 2008.

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