Department of Electrical Engineering

Faculty Member:ARSHAD NAZIR Dated: MAY 2ND ,2023

Semester: 2ND Section:

Group No.: 7

EE-221: Digital Logic Design

Assessment Rubrics for Lab 12: Memory Elements: Latches and Flip-Flops
PLO4/CLO4 PLO4/CLO4 PLO5/CLO5 PLO8/CLO6 PLO9/CLO7
Name Reg. No Viva / Lab Analysis Modern Ethics and Individual Total
Performance of data in Tool Usage Safety and Team marks
Lab Report Work Obtained

5 Marks 5 Marks 5 Marks 5 Marks 5 Marks 25 Marks

IDREES KHAN DAWAR 412669

HASAN ANSER 422023

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Lab12: Sequential Logic: Memory Elements: Latches and Flip-Flops

This Lab experiment has been designed to familiarize the students with use of Flip-Flops

Objectives

 Learn working of SR Latch and the way it can be constructed using NOR and NAND
gates
 Modifying the SR Latch circuit to transparent latch (D-Latch)
 Design D type positive edge-triggered Flip-Flop using SR Latched

Lab Instructions

 This lab activity comprises three parts, namely Pre-lab, Lab tasks, and Post-Lab Viva
session.
 The lab report will be uploaded on LMS three days before scheduled lab date. The
students will get hard copy of lab report, complete the Pre-lab task before coming to
the lab and deposit it with teacher/lab engineer for necessary evaluation.
 The students will start lab task and demonstrate design steps separately for step-
wise evaluation (course instructor/lab engineer will sign each step after ascertaining
functional verification)
 Remember that a neat logic diagram with pins numbered coupled with nicely
patched circuit will simplify trouble-shooting process.
 After the lab, students are expected to unwire the circuit and deposit back
components before leaving.
 The students will complete lab task and submit complete report to Lab Engineer
before leaving lab.
 There are related questions at the end of this activity. Give complete answers.

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A. Pre-Lab Tasks (5 marks – Individual and team work)

1. Differentiate between the Combinational and Sequential Circuit.

ASNWER:

A Combinational Circuit is a type of circuit in which the output is independent of

time and only relies on the input present at that particular instant. A Sequential
circuit is a type of circuit where output not only relies on the current input but also
depends on the previous output.

2. Differentiate between the Synchronous Sequential logic and Asynchronous Sequential

logic
ANSWER:

A Synchronous counter is the counter in which the clock input with all the flip-flops uses
the same source and produces the output at the same time.
The counters whose output doesn’t depend on a single clock signal. There are different
clock signals provided to produce the output called Asynchronous Counters.
In the synchronous counter there are continuous clock input signals with flip-flops used
to produce the output. In Asynchronous counters there are different clock signals used to
produce the output.

3. Draw the logic diagram of SR Latch using NOR Gates. Also give its function table .

FUNCTION TABLE:

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 S R Q Q’
1 0 1 0
0 0 1 0
0 1 0 1
0 0 0 1
1 1 0 1

4. The SR Latch can also be constructed using NAND Gates. Differentiate between the two
implementations of SR Latches using Logic Diagram and function table:

LOGIC DIAGRAM:

FUNCTION TABLE:

S R Q Q’
1 0 0 1
0 1 0 1
0 1 1 1
1 1 1 0
0 0 - -

DIFFERENCE:

The complement of the input signals for the NOR latch must be used for the NAND latch. The
S'-R' latch is another name for the NAND latch because it needs a 0 signal.

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 5. What are the set and reset conditions for SR and S´R´ Latches?

ANSWER:

Two useful states exist for the latch. The latch is said to be in the Set state when output
Q=1 and Q'=0, and in the Reset state when Q=0 and Q'=1. Outputs Q and Q' are
typically complementary to one another. S'R' latch and SR latch are complementary for
set and reset circumstances.

6. What is the undefined state for the Latches and how it occurs? How can you evaluate its
behavior in this state?

ANSWER:

Your latch won't output if the state is undefinable. In essence, we don't take this output
into account. Therefore, we referred to it as undefined output.

7. How can we remove the problem of undefined state using D Latch? Give Logic Diagram
of D Latch?

ANSWER:

When using a D latch, we combine two inputs and use the complement of one input. By
making R and S always complement one another, the undefinable state is eliminated.
The "no change" state suffers because of this enhancement.

LOGIC TABLE:

8. The essential elements of Sequential Circuits are memory elements. The two basic
types of memory elements are Latches and Flip-Flops. What is the basic Difference
between them?

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 ANSWER:

The primary distinction between latches and flip flips is that the former are level
sensitive, whilst the latter are edge sensitive. Flip flops can act as either positive or
negative edge triggers.

9. Give the graphic symbols for SR, S’R’ and D Latch

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B. Lab Task ( 10 marks – Tool Usage and Analysis)

SR Latch:

10. Implement the SR Latch using a) NOR and b) NAND gates and show it to Lab
Instructor. Give Logic Diagram, Function Table, and State Table for both designs.
What is the difference between the two implementations?
PROTEUS STIMULATION

HARDWARE:

FUNCTION TABLE:

NOR IMPLEMENTATION

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 NAND IMPLEMENTATION

DIFFERENCE:

The complement of the values used for NOR latch is required for the input signals for
NAND latch. The NAND latch is sometimes referred to as the S'-R' latch because it
needs a 0 signal.

D-Latch:
11. Implement the D-Latch and show it to your Lab Instructor. Give Logic Diagram
and Function Table. What advantage does it have over SR Latch?

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Flip-Flop:

12. Implement a D-type positive edge-triggered Flip-Flop using S.R. latches. What gates
would you need for the implementation? Give Logic Diagram, Graphic Symbols and
Characteristic Table. What change would be needed to design a negative edge triggered
Flip-Flop?

PROTEUS STIMULATION:

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GATES REQUIRED:

5 2-input Nand and 1 3-input Nand gate is required for implementation.

GRAPHIC SYMBOL:

HARDWARE:

NEGATIVE EDGE TRIGGERED:

A negative edge triggering method is used when a flip flop needs to react during the transition
from HIGH to LOW. The clock input lead, a triangle, and a low-state indicator are the main
features that help identify it.

13. Add CLEAR (Direct-reset) and PRESET (Direct-set) to the Flip-Flop. What are the
function of these inputs?

PROTEUS STIMULATION:

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 14. D Flip-Flop IC is 7474. Give its PIN Configuration, Function table and internal IC circuit. Draw
its state diagram and compare working of IC to you design in 13

PIN CONFIGURATION:

INTERNAL IC CIRCUIT:

FUNCTION TABLE:

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 HARDWARE IMPLEMENTATION OF WHOLE LAB

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