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MOSFET V2

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Aidas Mik
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6 views

MOSFET V2

Uploaded by

Aidas Mik
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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The MOSFET

What is the thing that people have produced


the most in human history?
• Cars (2.8 billion)
• Clay bricks (7 trillion)
• Rice grains (50 quintillion) 5 × 10¹⁹
• The MOSFET is the most commonly produced device in history,
with an estimated total of 13 sextillion MOSFETs made between
1960 and 2020. 13 × 1021
MOSFET terminology
• 3 terminals
• Hydraulic analogy
Transistor operation (simple)
• Channel concept
• source
• drain
• material in the middle (mostly semiconductors)
• looks like a resistor
• two electrodes
• some material in the middle (mostly insulators)
Flux
▪ Current in channel

▪ Current depends on number of charges in


channel
Transistor gate
• Gate: simply a metal contact
• gate dielectric: thin insulating film (no current)
→looks like capacitor
• 𝑄𝑔𝑎𝑡𝑒 = 𝐶𝑔𝑎𝑡𝑒 (𝑉) ∗ 𝑉𝐺𝑆
𝑊
• 𝐼𝐷 = 𝜇 𝑉 𝐶 𝑉 𝑉𝐺𝑆
𝐿 𝑛 𝐷𝑆 𝑔𝑎𝑡𝑒
• Channel conductance depends on gate voltage
• Can achieve amplification
Transistor operation II
• Normal semiconductors are macroscopic
• Gate effect only modulates the surface (and does not contribute much to
overall conduction)
• Such MOSFETs rely on inversion
• n-type contacts need to be connected by n-type channel at the surface
• Rest of the p-type semiconductor does not contribute to conduction
Types of MOSFETs
• Gate makes inversion channel – “Enhancement”
• Circuit symbol looks like broken channel
Types of MOSFETs
• Gate breaks inversion channel – “Depletion”
• Circuit symbol looks like working channel
The MOS capacitor
• Our simple capacitor picture needs work
• How do charges get on the plates in a
semiconductor
Capacitor modes
• p-type plate:
• Negative voltage applied: Holes (majority carriers) accumulate
• Positive voltage applied: holes are pushed away, space charges remain
• Holes float up, electrons roll down
• 𝐹 = −𝑞 𝑑𝐸/𝑑𝑥
Semiconductor plate math
• Just like one-sided pn junction with
voltage difference 𝜙𝑆 (“surface voltage”)
• Specific conditions:
1. Apply voltage to avoid band bending
• Called “flat-band voltage”
• Ideally would be the difference in Fermi levels
between metal and semiconductor 𝜙𝑚𝑠
• May Have to consider surface potential 𝜙𝑠 due to surface charges

𝑉𝐺𝐹𝐵 = 𝜙𝑠 + 𝜙𝑚𝑠
Work function differences
• Metal/semiconductor energy difference
depends on work functions and Fermi
level shift from intrinsic position 𝜙𝑓𝑝

𝜙𝑓𝑝
Oxide energy drop
• In addition to voltage difference, charge
difference can cause a change in energy
bands
• Silicon oxide usually has dangling bonds that
introduce additional surface charges Qss
Accumulation
• Surface charge density can be much larger than
Na if 𝜙𝑠 is negative
• This is called surface accumulation (this is NOT
inversion)
• If 𝜙𝑠 is positive, the charges deplete, leaving
behind a depletion region of width

• The total depletion charge results in a voltage


difference across the capacitor of
Maximum depletion/Inversion threshold
• The lowest number of carriers is ni
• Below that depletion voltage, minority carriers
start showing up
• Surface electron concentration = bulk hole
𝜙𝑓𝑝

concentration

• Then surface band bending at threshold is


related to bulk band bending
𝜙𝑠𝑡 = 2𝜙𝑓𝑝

• Happens at threshold voltage Vt


Maximum depletion width
• Highest depletion width at inversion threshold
• after that minority carriers form and decrease the width
• Can be tracked by capacitance measurements
• At threshold VT capacitor gap is wide (low C)
• In accumulation and inversion potential stays close to 𝜙𝑆
• then, the total capacitance is limited by oxide capacitance
Inversion
• Beyond threshold voltage the p-type channel behaves like n-type
Modification of MOSFET analysis
• Our FET analysis has limited itself to a capacitor
(no voltage difference within the plates)
• To drive a transistor, VDS is needed
• VGD is VGS-VDS which is smaller than VGS
• If VGD decreases below VT there will be no
accumulation in this part of the channel (we have
a npn junction which blocks current)
• VDS exhibits saturation at
More realistic current voltage
• In non-saturating region we have to consider non-
uniform accumulation resulting in different charge
concentration

• Above VT the model doesn’t work and we just


remember
Useful insights
• For really small VDS we can get easily
extract the field-effect mobility

• For other conditions, we look at the


transconductance

saturation
Substrate bias
• We have considered B=S (substrate
grounded) but we could apply a VSB
• The substrate bias increases the
depletion region and introduces more
charges in the channel

• This will change the threshold voltage


The CMOS structure
• The flowing current in a pair of n
and p FETs is almost 0
• Sum of 𝐼𝐷𝐷 = 𝑅𝑜𝑛 + 𝑅𝑜𝑓𝑓 ≈ 𝑅𝑜𝑓𝑓
Issues with our model
• Below VT ID is not really zero because there are
still intrinsic minority carriers
• This is called subthreshold current
• Looks linear in semilog plot, so must be exponential

• Subthreshold swing is fundamentally limited by kT


Scaling
Problems with scaling
• Gate dielectric thickness controls • Making channels smaller affects
charge concentration their threshold voltage due to
• Increasing gate capacitance effect of drain potential
relies on thinner oxides which • Drain induced barrier lowering
leak more (DIBL)

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