G. VIJAY KUMAR, Asst.

Prof COMPUTER ARCHITECTURE AND

ORGANIZATION

UNIT 2

CENTRAL PROCESSING UNIT

MACHINE INSTRUCTION CHARACTERISTICS

The operation of the processor is determined by the instructions it executes, referred to as

machine instructions or computer instructions. The collection of different instructions that the
processor can execute is referred to as the processor’s instruction set.

Elements of a Machine Instruction:

Each instruction must contain the information required by the processor for execution.

Operation code: Specifies the operation to be performed (e.g., ADD, I/O).The operation is
specified by a binary code, known as the operation code,or opcode.
Source operand reference: The operation may involve one or more source operands, that is,
operands that are inputs for the operation.
Result operand reference: The operation may produce a result.
Next instruction reference: This tells the processor where to fetch the next instruction after the
execution of this instruction is complete.

FIGURE 1: A SIMPLE INSTRUCTION FORMAT

TYPES OF OPERANDS

Machine instructions operate on data. The most important general categories of data are

• Addresses
• Numbers
• Characters
• Logical data

ADDRESSES
In many cases, some calculation must be performed on the operand reference in an instruction to
determine the main or virtual memory address. In this context, addresses can be considered to be
unsigned integers.

NUMBERS
All machine languages include numeric data types. Three types of numerical data are there in
computers.

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• Binary integer or binary fixed point

• Binary floating point
• Decimal

CHARACTERS
A common form of data is text or character strings. American Standard Code for Information
Interchange (ASCII) representation is used. Each character in this code is represented by a
unique 7-bit pattern; thus, 128 different characters can be represented.

LOGICAL DATA
Normally, each word or other addressable unit (byte, halfword, and so on) is treated as a single
unit of data. It is sometimes useful, however, to consider an n-bit unit as consisting of n 1-bit
items of data, each item having the value 0 or 1.When data are viewed this way, they are
considered to be logical data.

TYPES OF OPERATIONS

• Data transfer
• Arithmetic
• Logical
• Conversion
• Input/Output
• System control
• Transfer of control

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ADDRESSING MODES
1. Immediate Mode
2. Direct Mode
3. Indirect Mode
4. Indexed Mode
5. Relative Mode
6. Auto Increment Mode
7. Auto Decrement Mode

Immediate Mode:
According to this addressing mode, the value of the operand is (immediately) available in the
instruction itself.
Consider, for example, the case of loading the decimal value 1000 into a register Ri. This
operation can be performed using an instruction such as the following:

LOAD #1000, Ri.

In this instruction, the operation to be performed is to load a value into a register.

Direct (Absolute) Mode:

According to this addressing mode, the address of the memory location that holds the operand is
included in the instruction. Consider, for example, the case of loading the value of the operand
stored in memory location 1000 into register Ri. This operation can be performed using an
instruction such as

LOAD 1000, Ri.

The content in the address location 1000 will be loaded in the register Ri
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Indirect Mode:
In the indirect mode, what is included in the instruction is not the address of the operand, but
rather a name of a register or a memory location that holds the (effective) address of the operand.
In order to indicate the use of indirection in the instruction, it is customary to include the name of
the register or the memory location in parentheses.

LOAD (1000), Ri.

The meaning of this instruction is to load register Ri with the contents of the memory location
whose address is stored at memory address 1000.

Indexed Mode:
In this addressing mode, the address of the operand is obtained by adding a constant to the
content of a register, called the index register.

LOAD X(Rind), Ri.

This instruction loads register Ri with the contents of the memory location whose address is the
sum of the contents of register Rind and the value X.

Relative Mode:
Relative addressing is the same as indexed addressing except that the program counter (PC)
replaces the index register.

LOAD X(PC),Ri

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loads register Ri with the contents of the memory location whose address is the sum of the
contents of the program counter (PC) and the value X.

Auto Increment Mode:

In this mode, the content of the autoincrement register is automatically incremented after
accessing the operand.

LOAD (Rauto)+, Ri.

This instruction loads register Ri with the operand whose address is the content of register Rauto.
After loading the operand into register Ri, the content of register Rauto is incremented, pointing
for example to the next item in a list of items.

Auto Decrement Mode:

Similar to the autoincrement, the autodecrement mode uses a register to hold the address of the
operand. However, in this case the content of the autodecrement register is first decremented and
the new content is used as the effective address of the operand.

LOAD -(Rauto), Ri.

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This instruction decrements the content of the register Rauto and then uses the new content as the
effective address of the operand that is to be loaded into register Ri.

INSTRUCTION TYPES
Based on number of operands:

1. Three address instruction

2. Two address instruction
3. One address instruction
4. Zero address instruction

Three address instruction:

ADD A,B,C.
The instruction adds the contents of memory location A to the contents of memory location B
and stores the result in memory location C.

Two address instruction:

ADD A,B.
This instruction adds the contents of memory location A to the content of memory location B and
stores the results in B. The original contents of B are lost due to this operation.

One address instruction:

A one-address instruction takes the form ADD R1. In this case the instruction implicitly refers to
a register, called the Accumulator Racc, such that the contents of the accumulator is added to the
contents of the register R1 and the results are stored back into the accumulator Racc.

Zero address instruction:

These are the instructions that use stack operation. A stack is a data organization mechanism in
which the last data item stored is the first data item retrieved. Two specific operations can be
performed on a stack. These are the push and the pop operations.

ASSEMBLY LANGUAGE

Machine language is the native language of a given processor. Since assembly language is the
symbolic form of machine language, each different type of processor has its own unique
assembly language.

Consider the simple BASIC statement

N=I+J+K
Suppose we wished to program this statement in machine language and to initialize I, J, and K to
2, 3, and 4, respectively.. The program starts in location 101 (hexadecimal). Memory is reserved
for the four variables starting at location 201.The program consists of four instructions:
1. Load the contents of location 201 into the AC.
2. Add the contents of location 202 to the AC.
3. Add the contents of location 203 to the AC.
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4. Store the contents of the AC in location 204.

PROCESSOR ORGANIZATION

Fetch instruction: The processor reads an instruction from memory (register, cache, main
memory).
Decode instruction: The instruction is decoded to determine what action is required.
Process data: The execution of an instruction may require performing some arithmetic or logical
operation on data.
Write data: The results of an execution may require writing data to memory or an I/O module.

The CPU with system bus

The major components of the processor are an arithmetic and logic unit (ALU) and a control unit
(CU).The ALU does the actual computation or processing of data. The control unit controls the
movement of data and instructions into and out of the processor and controls the operation of the
ALU. In addition, the figure shows a minimal internal memory, consisting of a set of storage
locations, called registers.

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Internal structure of the CPU

REGISTER ORGANIZATION
The registers in the processor perform two roles:

User-visible registers: Enable the machine- or assembly language programmer to minimize

main memory references by optimizing use of registers.

Control and status registers: Used by the control unit to control the operation of the processor
and by privileged, operating system programs to control the execution of programs.

User-Visible Registers
A user-visible register is one that may be referenced by means of the machine language that the
processor executes. We can characterize these in the following categories:
• General purpose
• Data
• Address
• Condition codes

General-purpose registers can be assigned to a variety of functions by the programmer.

Sometimes their use within the instruction set is orthogonal to the operation.

Data registers may be used only to hold data and cannot be employed in the calculation of an
operand address.
Address registers may themselves be somewhat general purpose, or they may be devoted to a
particular addressing mode.
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Condition codes (also referred to as flags). Condition codes are bits set by the processor
hardware as the result of operations.

Control and Status Registers

There are a variety of processor registers that are employed to control the operation of the
processor.

Sign: Contains the sign bit of the result of the last arithmetic operation.
Zero: Set when the result is 0.
Carry: Set if an operation resulted in a carry (addition) into or borrow (subtraction) out of a
high-order bit. Used for multiword arithmetic operations.
Equal: Set if a logical compare result is equality.
Overflow: Used to indicate arithmetic overflow.
Interrupt Enable/Disable: Used to enable or disable interrupts.
Supervisor: Indicates whether the processor is executing in supervisor or user mode. Certain
privileged instructions can be executed only in supervisor mode, and certain areas of memory
can be accessed only in supervisor mode.

INSTRUCTION CYCLE:

Instruction cycle

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Instruction cycle state diagram

Fetch: Read the next instruction from memory into the processor.
Execute: Interpret the opcode and perform the indicated operation.
Interrupt: If interrupts are enabled and an interrupt has occurred, save the current process state
and service the interrupt.

INSTRUCTION PIPELINE

Pipelining is the use of the processor to work on different phases of multiple instructions in
parallel

Fetch instruction (FI): Read the next expected instruction into a buffer.
Decode instruction (DI): Determine the opcode and the operand specifiers.
Calculate operands (CO): Calculate the effective address of each source operand. This may
involve displacement, register indirect, indirect, or other forms of address calculation.
Fetch operands (FO): Fetch each operand from memory. Operands in registers need not be
fetched.
Execute instruction (EI): Perform the indicated operation and store the result, if any, in the
specified destination operand location.
Write operand (WO): Store the result in memory.

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Timing diagram for instruction pipeline

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Six stage instruction pipeline

Pipeline Performance:

The cycle time of an instruction pipeline is the time needed to advance a set of instructions one
stage through the pipeline.

Total time required for a pipeline with k stages to execute n instructions and t is the time delay.

The speedup factor for the instruction pipeline compared to execution without the pipeline is
defined as

Pipeline Hazards:

A pipeline hazard occurs when the pipeline, or some portion of the pipeline, must stall because
conditions do not permit continued execution.
There are three types of hazards: resource (structural), data, and control.

Resource Hazard:
A resource hazard occurs when two (or more) instructions that are already in the pipeline need
the same resource. The result is that the instructions must be executed in serial rather than
parallel for a portion of the pipeline. A resource hazard is sometime referred to as a structural
hazard.

Data Hazard:
A data hazard occurs when there is a conflict in the access of an operand location.

Control Hazard:
A control hazard, also known as a branch hazard, occurs when the pipeline makes the wrong
decision on a branch prediction and therefore brings instructions into the pipeline that must
subsequently be discarded

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