EE2255 Microelectronic Circuits

Final Exam 01/12/2016

1. Determine the small-signal gain (vout/vin) of the following circuits. (20/100)

(a) IC= 5 mA, RC= 2 k, and VA= 20 V (b) Ibias= 1 mA, RD= 1 k, W/L= 100,
nCox= 200 A/V2

VCC RD
vout
IC RC

vout 
vin Q1 vin

Ibias

(c) Vbias= 0.9 V, IS= 10-17 A, RL= 20 ohm (d) I1= 2 mA, I2= 0.5 mA, VOV(M1)=
VOV(M2)= 0.2 V, RL= 500 

I1

vin Q1
 M2
vout vin M1 
vout
Vbias Q2 RL I2 RL

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2. A common-emitter amplifier is shown below.
(a) What are the two purposes of using Q2 in this circuit? Name two advantages of using
this topology for amplifier. (5/100)
(b) Determine Rin, Rout, vx/vin, and vout/vin. Assume Ibias= 1 mA, VCC= 3.5 V, Rsig= 500
ohm, Q2= Q3, and = 100 and VA= 50 V for all the transistors. (10/100)
(c) Plot the loadline based on the I-V characteristics of Q1 and Q2, and estimate the
maximum allowed output swing of Vout to keep both transistors in the active region.
(5/100)

VCC

Q3 Q2

vout
vx
Ibias Q1
Rsig Rout
vin 
Rin

3. A two-stage amplifier (CS + source follower) is designed with a power budget of 8

mW, where VDD= 2V, nCox= 200 A/V2, VTH= 0.8 V, Rsig= 200 ohm, RG= 10 kohm,
R1= 300 ohm, and R2= 150 ohm. Assume the currents flowing in the first stage and
second stage are identical.
(a) What are the purposes of C1, C2, and R1 in the circuit? Briefly explain. (5/100)
(b) Determine the maximum allowed RD to keep M1 in saturation. Under this
condition, find the (W/L) ratio of M1 and the midband gain |vout/vin| of the amplifier.
(10/100)
(c) Based on the results in (b), plot the small-signal model of the amplifier and
determine the high-frequency 3-dB bandwidth (express your answer by MHz) using
Miller theorem and OCTC. Assume Cgs= 2 pF and Cgd= 1 pF for both M1 and M2.
(10/100)

2
 VDD

RD
RG

 M2
M1 vout
Rsig C1
R1  C2 R2
vin 

4. A MOS differential amplifier is biased by a BJT cascode current mirror as shown

below. Assume all the BJTs are in the active mode and all the MOSFETs are in the
saturation region.
(a) Provide one advantage and one disadvantage of using the cascode topology for
current source. (5/100)
(b) Assuming Q1= Q2= 0.5Q3= 0.5Q4 (emitter area) and VBE,on= 0.8 V, determine
Ibias. Also, if = 100, VA= 50 V for all the BJTs, determine Rout. (5/100)
(c) Determine the small-signal gain vout/vin of the differential pair, assuming RS= 200
ohm, (W/L)1= (W/L)2= 100, nCox= 350 A/V2, and VTH= 0.5 V. (5/100)
(d) Determine the range (both maximum and minimum) of input common-mode DC
level for the differential pair to keep the circuit function properly. (5/100)

VDD= 5 V

RL RL= 1 k
+ -
vout

RREF= 3.4 k vin vin

 M1 M2 
2 RS 2

Ibias Rout

Q1 Q3

Q2 Q4

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5. (a) What is the small-signal output impedance of an ideal voltage source? What is that
for an ideal current source? Briefly explain your answers. (5/100)
(b) Provide one advantage and one disadvantage of using more advanced MOS
technology (scaled gate length) for amplifier design. Briefly explain your answers.
(5/100)
(c) Determine Ix using the constant-voltage model (VD,on= 0.8 V) if R1= 120 ohm.
Estimate Ix using the small-signal analysis if Vx is increased by 10 mV. (5/100)

Ix

R1
Vx= 2 V +‐
D1

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 EE2255 Microelectronic Circuits

Final Exam 01/10/2017

1. If the small-signal vin is 1 mV, determine the small-signal output voltage vout in the
following circuits. Assuming all the MOSFETs are in the saturation region and BJTs
are in the active mode (VT= 26 mV, VBE,on= 0.8 V). (20/100)
(a) (b)
VCC
VDD
5 mA
vin
RD= 5 k

vout VB2

vin W/L= 100 vout

+  nCox= 200 A/V2
VGS= 1 V VTH= 0.6 V VB1 VA_NPN= 50 V
-
VA_PNP= 30 V

(c) (d)
VDD 3.5 V

W/L= 100 10 k

vout vin = 50
vin vout
W/L= 400
500 

2. A two-stage BJT amplifier is designed as follows, where Ibias is 10 mA, RE is 200 ohm,
and the voltage drop on RE is 0.5 V. Assuming all the transistors are biased in the active
mode.
(a) Briefly explain the circuit function of each block (I, II, and III). (5/100)
(b) Determine Rin_1, Rin_2, and Rout. (5/100)
(c) Determine vx/vin, vout/vx, and the overall small-signal gain vout/vin. (10/100)
(d) Assuming C of Q2 dominates the high frequency pole of the amplifier
(neglect all other capacitances), determine f3dB of this amplifier. (5/100)

1
 VCC= 3.3 V
III
VB
Q3

vin Q1
vout Transistor parameters:
vx NPN: VA= 50 V, = 50
I Q2
PNP: VA= 30 V, = 30
Rout
Rin_1 II C = 0.8 pF (Q2 only).

Ibias
Rin_2 RE

3. A cascode amplifier is shown below, biased by an ideal current source.

(a) Determine the small-signal gain vout/vin, where RS= 100 , and RL= 500 . (5/100)
(b) Determine the time constants associated with node X, Y, and Z using OCTC, and
determine the 3-dB bandwidth of the circuit. (10/100)
(c) If the ideal current source is replaced by a cascode current mirror as shown below,
where M3= M4= M5= M6 with (W/L) = 100. Determine the minimum and maximum
allowed voltage at Z (neglect the channel-length modulation effect). (5/100)

VDD VDD= 3.5 V

1 mA

Z vout M5 M4  nCox=  pCox = 400 A/V2
VTHN= VTHP = 0.6 V
VB M2  N=  P= 0.025 V-1
Rout RL M1: (W/L)= 100,
RS Y M6 M3 CGS1= 0.5 pF, CGD1= 0.3 pF
M1 M2: (W/L)= 200,
X CGS2= 1 pF, CGD2= 0.6 pF
vin Z

1 mA

2
4. A differential MOSFET amplifier is biased by a BJT current mirror as shown below,
(a) Briefly explain the purpose of Q3 in the current mirror. If the base current of Q1 and
Q2 are both 0.1 mA, estimate the error between Iref and IC1. (5/100)
(b) Assuming Q1= Q2, VBE,on= 0.8 V, and Rref = 2 k, R1 = 100 , determine Ibias (neglect
base current). (5/100)
(c) Assuming the calculated Ibias= 0.3 mA, determine the low-frequency small-signal gain
vo/vi. (5/100) gain = -gm*Rout
(d) If the load M3 and M4 are replaced by R1 and R2 each of 5 k (Ibias = 0.3 mA), and the
output voltage is taken differentially. What is the gain of the differential-mode signal?
And what is that for the common-mode signal? (5/100)
gain of common-mode = 0
VDD= 5 V

M3 M4 R1 R2
Iref +
vout
-
vo
Rref
vi vi vi vi
 M1 M2   
2 2 M1 M2
2 2
Q3

IC1 Ibias Ibias

Q1 Q2
= 100
(W/L)1= (W/L)2= 50, (W/L)3= (W/L)4= 100
R1
nCox= 100 A/V2, pCox= 50 A/V2
Vtn= |Vtp|= 0.7 V, VA(BJT)= 50 V
n= p= 0.05 V-1

Iref=(2*104/(B+1))+Ic1
5. (a) Plot the frequency response from low to high frequencies for a typical amplifier.
Provide brief explanations about the reason of low and high 3-dB frequencies.
(5/100)
(b) What types of capacitances exist under a forward-biased PN junction? How about a
reverse-biased PN junction? (5/100)
(c) Name two advantages of differential pair, compared with the single-ended
amplifier. Also, why the differential topology is not suitable for board level
circuits? (5/100)

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 EE2255 Microelectronic Circuits

Final Exam 01/11/2022

1. Determine the small-signal gain (vout/vin) of the following circuits. Assuming all the
transistors are biased in the active mode (BJT) or saturation region (MOS) (VT = 26
mV, VBE,on = 0.8 V). (20/100)
(a) (b)

VDD VCC

Ibias= 5 mA
vout vin Q1 
vin M1
Ibias= 1 mA
RL

mnCox= 200 mA/V2, W/L= 50, =0.05 V-1 RL= 50 , = 100, and VA= 

(c) (d)

VDD VCC
VB1
vin IC = 0.5 mA
M1
 Q1 
VG M2 vin vout
 vout Q2

Ibias= 2 mA RL VB2
PNP: VA= 30 V, NPN: VA= 60 V

(W/L)1= (W/L)2= 200,

VOV_M1=VOV_M2= 0.2 V,
RL= 1 k, and = 0.

1
2. A two-stage amplifier is designed for radio frequency communications.
(a) Identify the configurations of stage I (include amplifier topology and bias) and stage
II (amplifier topology only). Briefly explain the reason for each design. (5/100)
(b) Assume RG is very large. If RS is designed as 500 ohm, design RD to have ID of 1
mA. (5/100)
(c) Assume the RD obtained in (b) is 3.5 kohm, and RE is designed as 400 ohm.
Determine Rin1, Rin2, and the small-signal gain of vx/vin, vout/vx, and vout/vin. Assume the
antenna can be equivalent to a signal source with a 50 ohm internal resistance. (10/100)
(d) If the input DC block capacitor C1 (Assume C1 = 0.1 mF) has to be considered for
the frequency response, find the corresponding zero and pole frequencies of stage I.
(5/100)

VDD
VDD= 5 V
RD ID (W/L)1= 100
RG mnCox= 200 mA/V2
vx VTH= 0.5 V.
Q2
 = 30, VBE_on= 0.8V
C2
vin  M1 Ibias vout
C1

RE RL = 100 
RS

Rin1 Rin2

Stage I Stage II

3. A two-stage amplifier using current mirror bias is shown below.

(a) Determine the drain current of Q1 and Q2. (5/100)
(b) Determine the small-signal gain (vout/vin). (5/100)
(c) If Cgs = 0.5 pF, Cgd = 0.3 pF for Q2, and CL = 1 pF, determine the high-frequency
f3dB. Neglect all other capacitances. (5/100)
(d) Sketch the Bode plot of the 2nd-stage vout/vx for both magnitude (dB) and phase
(degree). Show the important values in the plots. Assume the initial phase of vx is
-180 (5/100)

2
 VDD= 3.5 V

Q3 mnCox= 200 mA/V2, mPCox= 100 mA/V2

Q4 Q5 (W/L)1= (W/L)4= 20, (W/L)3= 10
vout (W/L)2= (W/L)5= 40
vin Q1 Q2 Vtn= |Vtp|= 0.7 V
vx CL
VAn= 20 V, VAp= 40 V
Ibias= 1 mA
RS = 100 ohm

4. Assume Q1 = Q2 and Q3 = Q4 = Q5. Neglect the base current.

(a) What are the advantages of using differential pair for IC design? Name two of them.
(5/100)
(b) Determine RREF to have IREF= 2 mA. Assume VCC = 5 V and VBE,on= 0.8 V. (5/100)
(c) Determine the differential small-signal gain. Assume RC= 1 kohm. (5/100)
(d) Determine the minimum and maximum allowed DC voltage level of the input
common-mode signal. (5/100)

VCC

Q5 RC RC
- +
vout
RREF vi Q1 Q2 vi
+ −
IREF 2 2

Q4 Q3

3
5. (a) What are the two major carrier transport mechanisms in a semiconductor? What is
the mechanism in a diode? What is that in a BJT? And what is that in a MOSFET?
(5/100)
(b) When using transistors (BJT or MOS) as current sources, why does the output
current increase with the voltage across the current source? How do we model it in the
small-signal model? (5/100)
(c) If a common-source amplifier is biased with VDD of 5 V and ID of 2.5 mA.
Determine RL and plot the loadline (overlap with I-V curve) to allow a maximum
output swing of the amplifier (neglect the effect of knee voltage). Also, determine the
Q-point, intersection points to the X and Y axes and the slope of the loadline. (5/100)

VDD = 5 V

ID (mA)
ID = 2.5 mA RL

vout
+
vin VDS
-

VDS (V)

4
 EE2255 Microelectronic Circuits

Final Exam 01/10/2023

1. Determine the operating point (V and I) of the following circuits. Assuming Von of
both the diode and BJT is 0.8 V. (20/100)

(a) VG= 1.2 V, RD= 200  (b) VCC= 5 V, RB= 10 k, RC= 100 ,
= 50
VCC
+ V -
RC
I RB I
VG RD
+
V
-

(c) VDD= 2.5 V, RG= 20 k, RD= 200 , (d) M1= M2, VDD= 3.5 V, RD= 1.5 k,
VTH= 0.5 V, W/L= 200, mnCox= 100 mA/V 2 ISS= 2 mA, VSS= 0.5 V

VDD VDD
I RD
RG RD I RD

+
+ V
V -
- M1 M2
+
VSS ISS
-

2. Answer the following questions based on amplifier I and amplifier II as shown below.
(a) What type of circuit topology is for each circuit? Name one advantage and one
disadvantage of Amp. II compared with Amp. I. (5/100)
(b) Determine the small-signal gain of each amplifier. Assuming all the MOSFETs are
biased with DC current of 5 mA with an overdrive voltage of 0.1 V. Also, RD = 2
kohm and  of the transistor is 0.1 V-1. (5/100)
(c) Assuming Cgs= 0.5 pF and Cgd= 0.3 pF for all the MOSFETs, determine the
equivalent input capacitance Cin1 and Cin2 of the amplifiers, respectively. (10/100)

1
 Amp. I Amp. II
VDD VDD

RD
RD RD vbias
vout vout
vin M2
M1 M2
vin M1
Cin1
Cin2

3. The circuit shown below is similar to the gain stage (2nd stage) of the OP741 (Ibias= 1
mA and assuming all transistors have the same emitter area with VBE, on= 0.8 V;
neglect Early effect and base current for dc current calculation):
(a) Determine Rin1, Rin2, and Rout. (10/100)
(b) Determine the low-frequency small-signal gain vx/vin, vout/vx, and vout/vin. (10/100)
(c) Assuming C = 0.5 pF of Q2 dominate the high frequency pole of the amplifier
(neglect all other capacitances). Determine f-3dB of this amplifier. (5/100)

VCC= 5 V
Q4 Q3
Circuit parameters:
vout NPN: VA= 50 V, = 50
vin Q1
Ibias PNP: VA= 30 V, = 30
vx RE1= 2 k, RE2=200 
Q2
Rin1 Rout
RE1
RE2
Rin2

4. A differential pair with current mirror bias is shown below. Assume mnCox= 200
mA/V2, VTH= 0.5 V, (W/L)1= 200, (W/L)2= 400, = 0.1V-1, = 100, and RC= 1 kohm.

2
 (a) What are the advantages of using the differential topology compared with the
single-ended amplifier? Name two of these. Also, what is the limitation of using
the differential amplifier in practical circuit design? (5/100)
(b) What is the AC signal level of node P? What is the specific term that we use to
describe this node? Briefly explain. (5/100)
(c) If IREF = 0.5 mA, determine Ibias under the cases with and without considering
channel-length modulation. Assume that the drain voltage of M2 is 1 V. (5/100)
(d) Without considering channel-length modulation of the current mirror, determine
the differential small-signal gain of the amplifier. (5/100)

VCC

RC RC
- +
vout
IREF
vi Q1 Q2 vi
+ −
2 2
P
Ibias
M1 M2

5. (a) What are the main functions of the transistors in analog circuit design? Name two
of these. (5/100)
(b) Two BJTs (Q1 and Q2) have the same process parameters. The collector bias
current of Q2 is three times of Q1. Determine the ratio of the intrinsic gain (G2/G1) of
the two transistors. (5/100)
(c) Determine DC current Ix using the exponential model (IS = 10-17A) by iteration if
R1 = 100 ohm. Based on the calculated Ix, how does VD1 change if Vx is increased by 5
mV? (5/100)

3
 Ix

R1
Vx= 2.5 V +-
+
D1 VD1
-