(Established under the Presidency University Act, 2013 of the Karnataka Act 41 of

2013)
[2024-25 ODD SEMESTER]
COURSE HAND OUT [Revision 2 - JAN 2023]
SCHOOL: SOCSE DEPT: CSE DATE OF ISSUE: 15-07-2024

NAME OF THE PROGRAM: B. Tech.

P.R.C. APPROVAL REF.: PU/AC-16/CSE/2020-2024/2021

SEMESTER/YEAR: III semester/II year

COURSE TITLE & CODE: Computer Organization and Architecture-CSE2009

COURSE CREDIT STRUCTURE: 3-0-0-3

CONTACT HOURS: (45 classes) 3 periods per week

COURSE IC(S): Dr. G. Vennira Selvi, Ms. Monisha Gupta

COURSE INSTRUCTOR(S): Dr. G. Vennira Selvi, Ms. Monisha Gupta, Dr. Pamela, Ms.
Sreelatha, Dr. Kuppala Saritha, Dr. Madhusudhan M V, Mr.
Sakthi S, Ms. Kalpana Harish
COURSE URL:
https://presidencyuniversity.linways.com/

PROGRAM OUTCOMES:

PO1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering

fundamentals, and an engineering specialization to the solution of complex engineering

problems. [H]

PO2. Problem analysis: Identify, formulate, review research literature, and analyze complex

engineering problems reaching substantiated conclusions using first principles of mathematics,

natural sciences, and engineering sciences. [M]

PO3. Design/development of solutions: Design solutions for complex engineering problems and

design system components or processes that meet the specified needs with appropriate
consideration for the public health and safety, and the cultural, societal, and environmental

considerations. [L]

PO4. Conduct investigations of complex problems: Use research-based knowledge and research

methods including design of experiments, analysis and interpretation of data, and synthesis of the

information to provide valid conclusions.

PO5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern

engineering and IT tools including prediction and modeling to complex engineering activities with an

understanding of the limitations.

PO6. The engineer and society: Apply reasoning informed by the contextual knowledge to assess

societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to the

professional engineering practice.

PO7. Environment and sustainability: Understand the impact of the professional engineering solutions

in societal and environmental contexts, and demonstrate the knowledge of, and need for sustainable

development.

PO8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and

norms of the engineering practice.

PO9. Individual and team work: Function effectively as an individual, and as a member or

leader in diverse teams, and in multidisciplinary settings.[L]

PO10. Communication: Communicate effectively on complex engineering activities with the

engineering community and with society at large, such as, being able to comprehend and write

effective reports and design documentation, make effective presentations, and give and receive

clear instructions.[L]

PO11. Project management and finance: Demonstrate knowledge and understanding of the

engineering and management principles and apply these to one’s own work, as a member and leader

in a team, to manage projects and in multidisciplinary environments.

PO12. Life-long learning: Recognize the need for, and have the preparation and ability to engage in

independent and life-long learning in the broadest context of technological change.

PROGRAM SPECIFIC OUTCOMES:

PSO1: [Problem Analysis]: Identify, formulate, research literature, and analyze complex

engineering problems related to Software Engineering principles and practices, Programming

and Computing technologies reaching substantiated conclusions using first principles of

mathematics, natural sciences, and engineering sciences.[M]

PSO2: [ Design/development of Solutions]: Design solutions for complex engineering problems

related to Software Engineering principles and practices, Programming and Computing

technologies and design system components or processes that meet the specified needs with

appropriate consideration for the public health and safety, and the cultural, societal, and

environmental considerations.[L]

PS03: [Modern Tool usage] : Create, select, and apply appropriate techniques, resources, and modern

engineering and IT tools including prediction and modelling to complex engineering activities related

to Software Engineering principles and practices, Programming and Computing technologies with an

understanding of the limitations.

COURSE PREREQUISITES:

CSE 2015 Digital Design

COURSE DESCRIPTION:

This course introduces the core principles of computer architecture and organization from basics to

intermediate level. This theory-based course emphasizes on understanding the interaction between

computer hardware and software. It equips the students with the intuition behind assembly-level
instruction set architectures. It helps the students to interpret the operational concepts of computer

technology as well as performance enhancement.

COURSE OBJECTIVE:

The objective of the course is to familiarize the learners with the concepts of Computer Organization
and Architecture and attain Skill Development through Participative Learning techniques.

COURSE OUTCOMES: On successful completion of the course the students shall be able to:
TABLE 1: COURSE
OUTCOMES
CO CO Expected
Number BLOOMS
LEVEL
CO1 Discuss the basic components of a computer, their interconnections, and Remember
instruction set architecture
CO2 Apply appropriate techniques to carry out selected arithmetic operations Apply

CO3 Explain the organization of memory and processor sub-system Understand

MAPPING OF C.O. WITH P.O. [H-HIGH , M- MODERATE, L-LOW]

TABLE 2a: CO PO Mapping ARTICULATION

MATRIX
CO.
No PO PO PO PO4 PO5 PO6 PO7 PO8 PO PO1 PO11 PO12
1 2 3 9 0
CO1 H M L L
CO2 H H M L L
CO3 H H L L L

MAPPING OF C.O. WITH PSO. [H-HIGH , M- MODERATE, L-LOW]

TABLE 2b: CO PSO Mapping ARTICULATION

MATRIX
CO. PSO PSO PSO
No 1 2 3
CO1 M
CO2 M L
CO3 M L
COURSE CONTENT (SYLLABUS):
Module 1: Basic Structure of Computers
[12 Hrs] [Blooms Level selected: Remember]
Basic Structures of Computers: Computer Types, Functional Units, Basic Operational concepts,
Bus Structures, Computer systems RISC & CISC, Performance, Arithmetic Operations on Signed
numbers. Instructions and Instruction Sequencing, Instruction formats, Memory Instructions.

Module 2: Instruction Set Architecture and Memory Unit

[12 Hrs] [Blooms Level selected: Understand]
Instruction Set Architecture: Addressing Modes, Stacks and Subroutines.
Memory System: Memory Location and Addresses, Memory Operations, Semiconductor RAM
Memories, Internal Organization of Memory chips, Cache memory mapping Techniques.

Module 3: Arithmetic and Input/Output Units

[10 Hrs] [Blooms level selected: Apply]
Arithmetic: Carry lookahead Adder, Signed-Operand Multiplication, Integer Division, and Floating point
operations.
Input/output Design: Accessing I/O Devices, I/O communication, Interrupt Hardware, Direct Memory
Access, Buses, Interface Circuits.

Module 4: Basic Processing Unit and Pipelining

[11 Hrs] [Blooms level selected: Understand]
Basic Processing Unit: Fundamental Concepts, Single Bus organization, Control sequence, Execution of a
Complete Instruction, Multiple Bus Organization.
Pipelining: Parallel Processing, Pipelining, Arithmetic Pipeline, Instruction Pipeline, Hazards.

DELIVERY PROCEDURE (PEDAGOGY):

TABLE 3: SPECIAL DELIVERY METHOD/ PEDAGOGY PLANNED WITH
TOPICS
Pedagogy title/ ** At end of
S. No Lectur Subtopic as per short explanation semester
e lesson Plan of adopted please update
Numb pedagogy whether
er activity was
done
Generation of
1 2 self-learning topics /
Computers, Secondary
Activity
Storage, Case studies.
Read only Memories,
2 8, 21 Overflow in Flipped Classroom
Arithmetic
Blended Learning
3 38 Pipelining Hazards using Videos
Text Book:
T1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer Organization”, Fifth Edition,
McGraw-Hill Higher Education, 2016 reprint.(TB1)

Reference Book(s):
R1. William Stallings, “Computer Organization & Architecture – Designing for performance”, 11th
Edition, Pearson Education Inc., 2019. (RB1)
R2. David A. Patterson, John L. Hennessy, “Computer Organization and design MIPS Edition- The
Hardware/Software Interface”, 6th Edition, Morgan Kaufmann, Elsevier Publications, November
2020. (RB2)
ONLINE RESOURCES:

W1. NPTEL Course on “Computer architecture and organization” IIT Kharagpur By Prof. Indranil
Sengupta, Prof. Kamalika Datta. https://nptel.ac.in/courses/106105163
W2. NPTEL Course on “Computer Organization”, IIT Madras By Prof. S. Raman.
https://nptel.ac.in/courses/106106092

COURSE SCHEDULE:
TABLE 4: COURSE BROAD
SCHEDULE
Sl. ACTIVITY PLANNED PLANNED TOTAL NUMBER OF
No. STARTING CONCLUDING PERIODS
DATE DATE
01 Over View of the course 19/08/2024 1
02 Module : 01 20/08/2024 15/09/2024 12
03 Surprise Test 1 - - NA
04 Module: 02 17/09/2024 14/10/2024 11
05 Surprise Test 2 - - NA
06 Assignment 1 15/10/2024 23/10/2024 --
07 Midterm As per schedule by COE
08 Module:03 15/10/2024 18/11/2024 11
09 Surprise Test 3 - - NA
10 Module:04 19/11/2024 13/12/2024 10
11 Assignment 2 19/11/2024 27/11/2024 --
DETAILED SCHEDULE OF INSTRUCTION:
Main pedagogy: PPT + Chalk Board and Lecture

LOL HOL Course Reference

Topics & Learning Objectives (Lower (Higher Outco (Ch No.,
Session No. Lesson Title Order Order me Pg:x-y)
LO: Student shall be able Learning) Learning
to: )

Details of the course,

1 Objectives, CO
Program Integration 1
Computer Types,
Functional Units LO1:
Define the functional
Units of computer. L1 T1
2 LO2: Defend the importance - CO Chap. 1
of functional Units for proper 1 (Pg. 2)
working L2
of the system.
Connections between the
processor and memory LO1:
List the registers used in a - T1
3 processor L1 CO1 Chap. 1
LO2: Explain the working (Pg. 7)
Module of the registers to store data L2
1- Basic to memory
Structu Connections between the
res of processor and memory LO1:
Comput List the registers used in a T1
ers L1
4 processor CO1 Chap. 1
LO2: Explain the steps (Pg. 7)
followed in the processor L2 -
to load data from memory to
register.
Single bus structure,
processor clock T1
5 LO1: Define the types of L1 CO Chap. 1
buses used in a computer. - 1 (Pg. 9)
LO2: Explain the use of L2
buffer registers in devices.
Clock Rate,
L1 T1
6 Basic Performance equation - CO Chap. 1
LO1: Describe the Basic 1 (Pg. 15)
Performance equation. L3
LO2: Calculate the time
required to execute a
program, when the number
of instructions and clock rate
is given.
7 Introduction to Number
Representation
LO1: State different
methods of representing a L1 T1
number. C Chap. 2
LO2: Compare and - O (Pg. 27)
summarize the different 1
ways of number L2
representation
8 Addition and Subtraction
of signed numbers and T1
overflow L1 - C Chap. 2
LO1: Define overflow. LO2: O (Pg. 29)
Perform the arithmetic L3 1
operations.
9 Byte Addressability, Big-
endian and Little-endian
Assignments T1
LO1: Recognize the types of - C Chap. 2
byte addressing. L1 O (Pg. 34)
LO2: Illustrate the types of 1
byte addressing with L3
example.
10 Byte Addressability, Big-
endian and Little-endian
Assignments T1
LO1: Describe the types of L1 - C Chap. 2
Byte Addressing. O (Pg. 34)
LO2: Problems on byte 1
addressing L3
11 Memory Operations,
Register Transfer Notation, -
Assembly T1
CO
Chap. 2
L1 1
(Pg. 36)
L2
Language Notation LO1:
Describe the basic
memory operations. -
LO2: Explain the given
instructions.
12 Three, Two and One
Address Instruction formats - T1
LO1: Explain the different C Chap. 2
types of Instruction formats. L1 O1 (Pg. 39
13 Surprise Test I

Module 1 Integration

14 Instructions Register,
Module 2 : Absolute, Immediate,
Instructio Indirect Addressing
n Set modes
Architectu LO1: Explain the Absolute, T1
re and Immediate and Direct L1 - CO 1 Chap. 2
Memory Addressing with an (Pg. 48)
Unit example.
LO2: Interpret the type of
addressing mode used in the L3
given instructions.
15 Indirect Addressing
modes,
Index Mode and Relative --
Addressing
LO1: Explain the Indirect, T1
Index and relative L1 CO Chap. 2
Addressing with an 1 (Pg. 50)
example.
LO2: Interpret the type of
addressing mode used in the L3
given instructions.
16
Auto increment and Auto
decrement mode
LO1: Explain the Auto T1
increment and Auto L1 - CO Chap. 2
decrement instructions with 1 (Pg. 57)
an example.
LO2: Calculate the effective L3
address of the operands.
17 Processor stack and stack
operations
LO1: Describe the T1
operations used in a stack L1 CO Chap. 2
LO2: Explain the operations - 1 (Pg. 68)
performed to solve an L2
equation using stack.
18 Subroutine, Subroutine
Nesting
LO1: Explain the Push and
Pop subroutine. L1 - T1
LO2: Demonstrate the CO Chap. 2
operations to point the PC 1 (Pg. 72)
register to a subroutine using
stack. L3
19 Internal Organization of -
Memory Chips
LO1: Describe Static T1
memory. L1 CO Chap. 5
LO2: Explain the memory 3 (Pg 295)
organization of 16 X8 chip. L2

20 Internal Organization of
Memory Chips
LO1: Describe Dynamic L1 T1
memory. CO Chap. 5
LO2: Explain the read and L2 -- 3 (Pg 295)
write operations of dynamic
memory.
21 Read-Only memories,
Speed, Size and Cost,
Memory Hierarchy T1
LO1: Explain the types of CO Chap. 5
primary memory. L1 -- 3 (Pg.309)
LO2: Compare the Speed,
size and cost of memory L2
devices.
22 Introduction to Cache
Memory
LO1: Define the operations -- T1
performed in cache L1 CO Chap. 5
memory. 3 (Pg.314)
LO2: Illustrate the benefit L3
of using cache memory
23 Different Mapping
Technique’s LO1: Explain
the different techniques of T1
Mapping functions with L1 -- CO Chap. 5
example. LO2: Solve the 3 (Pg.316)
given problem using
different caching L3
techniques.
24 Surprise Test I
Module 2 Integration
25 4 bit carry look ahead
adder
LO1: Explain the concept T1
C
 of Look ahead adder LO2: Chap. 6
Describe the design of L1 -- O (Pg.372)
Look Ahead Adder circuit 2
L2
26 Introduction and problem
on Booth Algorithm LO1:
Write the Booth Algorithm L1 -- T1
LO2: Solve the given C Chap. 6
problem using Booth O (Pg.380)
Algorithm L3 2
27 Problem on Booth
Algorithm
LO1: Explain the key T1
features of Booth L1 C Chap. 6
Module 3: Algorithm. -- O (Pg.382)
Arithmeti LO2: Solve the given 2
c and problem using Booth L3
Input/Out Algorithm
28 put Units Introduction to Restoring
Division
LO1: Write the Restoring -- T1
Algorithm L1 C Chap. 6
LO2: Solve the given O (Pg.390)
problem using Restoring 2
Algorithm L3
29 Problems on Restoring
Division
LO1: Explain the key T1
features of Restoring L1 C Chap. 6
Division Algorithm. LO2: -- O (Pg.391)
Solve the given problem 2
using Restoring L3
Division Algorithm
30 IEEE Standards For
Floating- Point Numbers
(Single Precision) LO1: T1
Explain the pertinent L1 -- C Chap. 6
concepts of IEEE standards. O (Pg.394)
LO2: Interpret the given 2
numbers in IEEE format. L3
31 IEEE Standards For
Floating- Point Numbers T1
(Single Precision) L1 -- C Chap. 6
LO1:Explain the IEEE O (Pg.394)
Formats. L2 2
LO2: Find the smallest and
largest number possible in a
given IEEE format.
32 Accessing I/O devices,
LO1:Explain the two
schemes to connect I/O T1
L1
 devices to CPU LO2:Write Chap. 4
a program to check the -- C (Pg.204)
status of register and read or O
L3 1
display data.
33 Interrupts, Enabling and
Disabling
LO1: Describe an interrupt T1
LO2: Explain the different L1 C Chap. 4
ways of enabling and O (Pg.208)
disabling interrupts L2 1
34 Types of interrupts
LO1: Explain the concept T1
of ISR L1
C Chap. 4
LO2: Describe different -- O (Pg.213)
ways of handling interrupts 1
L2
35 DMA operation LO1:
Define DMA operation
LO2: Distinguish the two L1 T1
modes of memory access C Chap. 4
by DMA controller -- O (Pg.234)
L2 1
36 Surprise Test 3
Module 3 Integration
37 Fundamental Concepts,
LO1: Define ISP L1 T1
LO2: Describe the steps in -- C Chap. 7
the execution of instructions. L2 O (Pg.412)
3
38 Module 4: Single Bus Organization,
Basic Control sequence
Processing LO1: Explain the registers T1
L1 -- C
Unit and used in the execution. Chap. 7
Pipelining LO2: Illustrate the execution O (Pg.413)
of an instruction in single bus 3
L3
organization
39 Control Sequence for CO3 Chap. 7
execution of complete (Pg.421)
instruction L1
LO1: List the actions --
perfomed in execution of
instruction L2
LO2: Explain the control
sequence for execution of a
given instruction
40 Three Bus Organization,
Control sequence
LO1: Explain the working L1
of registers in execution of T1
instruction. -- CO Chap. 7
 LO2: Illustrate the execution (Pg.423)
of an instruction in multiple L3 3
bus organization
41 Control Sequence for
execution of complete
instruction for 3-bus LO1:
List the actions performed L1 T1
in execution of instruction CO Chap. 7
LO2: Explain the control -- 3 (Pg.424)
sequence for execution of
a given instruction in L2
multiple bus organization
42 An Overview of
Pipelining
LO1: Describe the T1
different stages of L1 -- CO Chap. 8
pipelining 3 (Pg.454)
LO2: Describe the
execution of instructions in L2
stages.
43 Types of Pipeline
Dependencies T1
LO1:List the dependencies in L1 -- CO Chap. 8
pipeline 3 (Pg.458)
LO2: Explain the
dependencies in pipeline L2
44 Structural, Data and
Control hazards LO1:
Outline the T1
requirements to overcome L1 -- CO Chap. 8
hazards 3 (Pg.461)
LO2:Illustrate the hazards
in pipelining L3
45 Surprise Test 4
 SPECIFIC GUIDELINES TO STUDENTS:

1. Students are required to strictly adhere to assignment deadlines.

2. Students are required to actively participate in classroom discussions and other activities
which is planned in and out of the classroom.

ASSESSMENT SCHEDULE:

TABLE 6 ASSESSMENT
SCHEDULE
Course
Sl. Assessment Duratio DATE
Content outcom Marks Weightag
No. type s n In e &
e
Numbe Hours TIME
r
Surprise 10
1 Module 1 CO 1 --- 5%
Test 1 Mark
s
Surprise 10
2 Module 2 CO 2 --- 5%
Test 2 Mark
s
Assignment Questions from Module 1 CO 1 & 10
3 --- 5%
1 / Activity & 2 CO2 Mark
s
 Module 1: Basic
Midterm Structure of Computers
2 Examinati  Module 2: Instruction Set CO 1, 2 hours 50 25%
on Architecture and Memory CO 2 Mark
Unit s
Surprise 10
3 CO 2, --- 5%
Test 3 Module 3 Mark
CO3
s
Assignmen Problems from Module 3 CO 2 10
t2/ & --- Mark 5%
Activity CO3 s
 Module 1: Basic Will be
announced
Structure of Computers by COE
 Module 2: Instruction Set
Architecture and Memory
CO1,
Unit
CO 100
6 End Term  Module 3: Arithmetic 3 hours 50%
2, Marks
and Input/Output Units
CO 3
 Module 4: Basic
Processing Unit and
Pipelining
COURSE CLEARANCE CRITERIA:
AS PER ACADEMIC REGULATIONS OF THE UNIVERSITY

MAKEUP EXAM POLICY:

AS PER ACADEMIC REGULATIONS OF THE UNIVERSITY

CONTACT TIMINGS IN THE CHAMBER FOR ANY DISCUSSIONS: (Here mention the fixed
slots on any of the week days for students to come and interact with you)
SAMPLE THOUGHT PROVOKING QUESTIONS:

TABLE 7: SAMPLE THOUGHT PROVOKING

QUESTIONS
SL QUESTION MARKS COURSE BLOOM’S
N OUTCO LEVEL
O ME NO.
1 Describe the steps needed to execute the 8 CO1 Understand
machine instruction Add LOCA, RO
In terms of transfers between the
components
2 Consider a computer that has byte 8 CO2 Understand
addressable memory organized in 32 bit
words according to the big endian scheme.
Show how the contents of two memory
word at locations 1000 and 1004
after the name Vishnu is entered
3 Write the sequence of control steps required 8 CO3 Apply
for the instruction
Add the content of memory location NUM to
register R1
4 Given A=18 and B=3 Apply Restoring 10 CO3 Apply
Division and perform A/B

TARGET SET FOR COURSE OUTCOME ATTAINMENT:

TABLE 8: TARGET SET FOR ATTAINMENT OF EACH CO and ATTAINMENT
ANALYSIS AFTER RESULTS
Sl.no C.O. Course Outcomes Threshold Target Actual Remarks on
No. Set for the set for C.O. attainment
CO attainme Attainment &Measures
nt in In to enhance
percenta Percentage the
ge * attainment
*
01 CO1 Discuss the basic 60% 70
components of a %
computer, their
interconnections, and
Instruction set
architecture
 02 CO2 Apply appropriate 60% 65
techniques to carry out %
selected arithmetic
operations
03 CO3 Explain the 60% 65
organization of memory %
and processor sub-
system

Signature of the course Instructor In-Charge (s)

APPROVAL:
This course has been duly verified Approved by the D.A.C.

Signature of the Chairperson D.A.C.

Name and signature of the Instructor In-Charge (s) AFTER completing entries in Table number 3 and 8 at
end of semester:

Name and signature of the DAC Chairperson AFTER completing entries in Table number 3 and 8 at end of
semester:

BLOOM'S TAXONOMY SAMPLE VERBS

TABLE 9: REFERENCE SAMPLES OF BLOOMS TAXONOMY VERBS

Cognitive Level Illustrative Verbs Definitions

arrange, define, describe, duplicate, identify, label, list,
Knowledge match, memorize, name, order, outline, recognize, relate, remembering previously learned information
recall, repeat, reproduce, select, state
classify, convert, defend, discuss, distinguish, estimate,
explain, express, extend, generalize, give example(s),
Comprehension identify, indicate, infer, locate, paraphrase, predict, grasping the meaning of information
recognize, rewrite, report, restate, review, select,
summarize, translate
apply, change, choose, compute, demonstrate, discover,
dramatize, employ, illustrate, interpret, manipulate,
Application applying knowledge to actual situations
modify, operate, practice, predict, prepare, produce, relate
schedule, show, sketch, solve, use write
 analyze, appraise, breakdown, calculate, categorize,
classify, compare, contrast, criticize, derive, diagram,
breaking down objects or ideas into simpler
differentiate, discriminate, distinguish, examine,
Analysis parts and seeing how the parts relate and are
experiment, identify, illustrate, infer, interpret, model,
organized
outline, point out, question, relate, select, separate,
subdivide, test
arrange, assemble, categorize, collect, combine, comply,
compose, construct, create, design, develop, devise,
rearranging component ideas into a new
Synthesis explain, formulate, generate, plan, prepare, propose,
whole
rearrange, reconstruct, relate, reorganize, revise, rewrite,
set up, summarize, synthesize, tell, write
appraise, argue, assess, attach, choose, compare, conclude,
contrast, defend, describe, discriminate, estimate, making judgments based on internal evidence
Evaluation
evaluate, explain, judge, justify, interpret, relate, predict, or external criteria
rate, select, summarize, support, value