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Module 5_Presentation

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Module 5_Presentation

Uploaded by

mangatha935
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Module 5

Op-amp Application
1. DAC
a. Weighted Resistor
b. R-2R ladder

2. ADC by Successive Approximation Type

3. Small Signal Half Wave Rectifier

4. Active Filters
a) First and Second order low Pass Butterworth Filter
b) First and Second order High Pass Butterworth Filter
c) Band Pass Filter
d) Band Reject Filter

5. 555 Timer and its application


a) Monostable Multivibrator
b) Astable Multivibrator
DAC: Digital To Analog Converter
DAC is used when binary output from a digital system must be
converted to some equivalent analog voltage or current.
A D/A converter in its simplest form uses an opamp and either binary-
weighted resistor or R-2R resistor
8-11-1(a) D/A converter with binary-weighted resistor
 Opamp is connected in inverting mode, it operates as current-to-
voltage converter.
 Number of binary inputs=4 it is called 4-bit converter.
 Because there are 24=16 combinations of binary inputs for b0 to
b3, an analog output should have 16 possible corresponding
values.
Referring to figure 8-18:
Four switches (b0-b3) are used to simulate the binary inputs ( else 4-bit
counter may be used)
 When switch b0 is closed the voltage across R is 5V because
V2=V1=0V. The current through R =5/10K= 0.5mA. WKT that
input current is zero for an opamp, thus feedback resistor Rf
carries same current 0.5mA, which in turn produces output voltage
Vo= (-1K ) (0.5mA).= -0.5V.

 When b1 is closed and b0 is opened. This action connects R/2 to


the positive supply of +5V, causing as much as current (1mA) to
flow through Rf, which in turn doubles the output voltage. The
output Voltage V0= (-1K)(1mA)= -1 V

 When both b0 and b1 are closed the current through Rf will be


1.5mA, which will be converted to an output voltage of
V0=(-1K)(1.5mA)=-1.5 V
Thus depending on whether switches b0 to b3 are open or closed, the
binary-weighted currents will be set up in input resistor. The sum of
these currents is equal to the current through Rf, which in turn is
converted to a proportional output voltage.
 When all the switches are closed , obviously the output will be
maximum. The output voltage equation is given by

Figure 8-18(b) shows analog outputs versus possible combination of


inputs. The output is negative-going staircase waveform with 15 steps of
-0.5V each.
 The problem with the D/A converter of Figure8-18 is that it
requires binary-weighted resistor, which may not be readily
available, especially if the number of inputs is more than four.
 An alternate to it is to use R-2R resistor
D/A Converter with R and 2R
Figure 8-19(a) shows a D/A converter with R and 2R resistor
 Binary inputs are simulated by switches b0 through b3 and
output is proportional to the binary inputs.
 Binary inputs can be either the high or low state
Assume b3 (MSB) is connected to +5 and other switches re grounded
 Thevenizing the circuit to the left of the switch b3 .

Thevenin says that if your circuit contains linear elements like voltage sources,
current sources and resistors, that you can cut your circuit at any point and replace
everything on one side of the cut with a voltage source and a single series resistor.
The voltage source is the open-circuit voltage at the cut point, and the series resistor
is the equivalent open circuit resistance with all voltage sources shorted.
Figure 2 below shows the locations of the “cut lines” we’ll use to simplify this
circuit to calculate its output impedance. For this analysis, the digital inputs
will all be considered shorted to ground.

The two 2R resistors to the left of the first cut line in Figure 2 appear in
parallel (when the digital bit b0 is grounded), and can be replaced with a
single resistor R as shown in Figure 3. The series combination of the two R
resistors on the left of Figure 3 combine to a single resistor of value 2R,
which is in parallel with the 2R resistor to b1.
You may notice that this process repeats itself each time we work from left to
right, successively replacing combinations of resistors with their equivalents.
As you can see in Figure 4, the circuit ultimately simplifies to a single resistor
R.

 Thevenin’s equivalent resistance Rth is


 The resultant circuit is shown in figure 8-19(b). In this
figure the (-) input is at virtual ground(V2=0V); therefore,
the current through Rth =(2R) is zero
 The current through 2R connected to +5V = 5/20K =
0.25mA
 Thus same flows through Rf and in turn produces the
output voltage= -(-20K)(0.25mA)= -5V
Using the same analysis, the output voltage corresponding to all possible
combinations of binary inputs can be calculated as shown in Figure8-
19(c).
 The output voltage equation can be written as

Where each of the inputs b3, b2, b1 and b0 may be either


high(+5V) or low(0V).
 The great advantage of the D/A using R-2R is that is requires only
two sets of precision resistance values but disadvantages is it
requires more resistor and also more difficult analyze.
Analog to Digital Converter
A/D converters convert an analog voltage to digital output
that best represents the input. There are many types of A/D
converters
1. Single-Ramp integrating
2. Dual- Ramp integrating
3. Single Counter
4. Tracking
5. Successive Approximation

Successive Approximation Type:


It basically consist of
1. Comparator
2. Successive-approximation register
3. Output latches
4. D/A Converter
Comparator is inverting:
O/p is High , when Va<Vin;(Vin<Vref)
O/P is Low , When Va>Vin; (Vin> Vref)
 SAR output is applied to an 8-bit D/A Converter
 Analog O/P (Va) of D/A converter is compared to an analog i/p Vin by
the comparator
 The o/p of the comparator is a serial data input to the SAR.
 The SAR then adjusts its digital o/p(8-bit) until it is equivalent to analog
i/p
 The 8-bit latch at the end of conversion holds onto the resultant digital
data output.

Working of Circuit:
 At the start of the conversion cycle, the SAR is reset by holding the
start (S) signal high.

 On the first clock pulse low-to-high, the most significant o/p bit Q7
of the SAR is set

 The D/A converter then generates an analog equivalent to the Q7


bit, which is compared with the analog input Vin

 If the Comparator o/p is low, D/A o/p>Vin and the SAR will clear its
MSB Q7

 If the Comparator o/p is HIGH, D/A o/p< Vin and SAR will keep
the MSB Q7 Set

 On the next clock pulse low-to-high, the SAR will set the next MSB
Q6. Depending on the o/p of the comparator , the SAR will then
either keep or reset the bit Q6

 This process is continued until the SAR tries all the bits.
 As soon as the LSB Qo is tried, the SAR forces the conversion
compete (CC) signal High to indicate parallel o/p lines contain valid
data.

 The CC signal in turn enables the latch, and the digital data
appear at the o/p of the latch.

 Digital data are also available serially as the SAR


determines each bit.

 To cycle the converter continuously, the CC signal may be


connected to start conversion i/p.

 The advantage of successive-approximation A/D converter


is its high speed and excellent resolution.

 In this example, 8-bit successive-approximation A/D


converter requires only eight clock pulse.
Xc=1/f
Fh=1KHz
C= const
R=5.34Kohm
Xc=1/2*pi*f*C
C--- open switch F—low
C---closed switch F--high
V1- Voltage at non-inverting terminal
V1= RVin/Xc+R
Xc= 1/j2*pi*f*C
V1= RVin/[(1/ j2*pi*f*C )+R]
V1=j2*pi*f*C*R*Vin/1+R j2*pi*f*C

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