KARPAGAM INSTITUTE OF TECHNOLOGY

COIMBATORE – 641105
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
ACADEMIC YEAR: 2023-2024 (ODD)
QUESTION BANK

Year / Sem / Branch: III /V/ ECE A Course Code : EC3352

Name of the Faculty: R.Kiruthikaa, AP/ECE Course Name : VLSI &Chip Design
UNIT I - INTRODUCTION TO MOS TRANSISTOR
PARTA
S.No. Questions and Answers Knowledge
Level
1. What are the advantages of CMOS process? K1
i. Low power Dissipation
1 ii. High Packing density
iii. Bi directional capability
iv. Low Input Impedance
v. Low delay Sensitivity to load.

2. Draw the IV characteristics of MOS transistor. K1

2
2

3. What is pull down device? K1

A device connected so as to pull the output voltage to the lower supply voltage
3 usually 0V is called pull down device.
4. What is pull up device? K1
A device connected so as to pull the output voltage to the upper supply voltage
4 usually VDD is called pull up device.
5. Why NMOS technology is preferred more than PMOS technology? K1
5 N- Channel transistors have greater switching speed when compared to PMOS
5 transistors.

1
 Draw the energy band diagrams of the components that make up the MOS K1
system.

6.

Outline the different operating regions for an MOS transistor. K2

7. i. Cutoff region
ii. Non- Saturated Region
7 iii. Saturated Region
8. Interpret the term Latch – up. K2
Latch up is a condition in which the parasitic components give rise to the
8 establishment of low resistance conducting paths between VDD and VSS with
disastrous results. Careful control during fabrication is necessary to avoid this
problem.
9. Draw the equivalent circuit structure of level 1 MOSFET model in spice. K1

10.What is the influence of voltage scaling on power and delay? K1

10Constant voltage scaling shrinks the devices but not the power supply.
10 Historically, feature sizes were shrunk from 6 pm to 1 pm while maintaining a 5
V supply voltage. This constant voltage scaling offered quadratic delay
improvement as well as cost reduction. It also maintained continuity in voltage
standards. Constant voltage scaling increased the electric fields devices.
11.What are the uses of Stick diagram? K1
i. It can be drawn much easier and faster than a complex layout.
2
11 ii. These are especially important tools for layout built from large
cells.
12.Illustrate the various color coding used in stick diagram. K2
i. Green - n-diffusion
12 ii. Red- polysilicon
iii. Blue -metal
iv. Yellow- implant
v. Black-contact areas.
What are two components of Power dissipation? K1
There are two components that establish the amount of power dissipated in a
CMOS circuit. They are:
13. i. Static dissipation due to leakage current or other currents drawn
continuously from the power supply.
13
ii. Dynamic dissipation due to switching transient current and charging and
discharging of load capacitances.

14.What is the objective of layout rules? K1

i. To build reliably functional circuits in as small an area as possible.
14 ii. To provide a necessary communication link circuit designer and process
engineer during manufacturing.
iii. To obtain a circuit with optimum yield in smallest possible area.
Interpret the term device modeling. K2
Semiconductor device modeling creates models for the behavior of the
15.electrical devices based on fundamental physics, such as the doping files of the
devices. It may also include the creation of compact models (such as the well
15 known SPICE transistor models), which try to capture the electrical behavior of
such devices but do not generally derive them from the underlying physics.
Normally it starts from the output of a semiconductor process simulation.
16.What is the fundamental goal in Device modeling? K1
To obtain the functional relationship among the terminal electrical 0' variables
16 of the device that is to be modeled.
17.Why does the interconnect increases the circuit delay? K1
Interconnect increases circuit delay for two reasons. First, the wire capacitance
adds loading to each gate. Second, long wires have significant resistance that
17 contributes distributed RC delay or flight time.
18.What is meant by design margin? K1
The collective effects of process and environmental variation can be lumped
18 into their effect on transistors: typical, fast, or slow. In CMOS, there are two
types of transistors with somewhat independent characteristics, so the speed of
each can be characterized. Moreover, interconnect speed may vary
independently of devices. When these processing variations are combined with
the environmental variations, we define design or process corners.

19.What do you mean by VLSI? K1

VLSI means Very Large Scale Integration. It is the process of creating an
Integrated circuit by combining thousands of transistors into a single chip.
19
20.Why do we need integration? K1
i. To increase the number of components in a chip.
ii. To reduce the size of the device.
20 iii. To increase the speed.

3
 21.Classify the types of integration. K2
The integration of components is classified into five types.
21 i. Small scale Integration
ii. Medium scale Integration
iii. Large scale Integration
iv. Very Large scale Integration
v. Ultra Large scale Integration

22.State Moore's law. K1

Moore's law states that the number of transistors on a chip doubles every 18 to
22 24 months.

Write the advantages of VLSI. K1

i. Reduced size
ii. Less Expensive
23.
iii. Increased operating speed
23
iv. Less power consumption
v. High reliability
vi. Smaller area

What are the operating modes of MOSFET? K1

There are two modes of operation.
24 i. Enhancement Mode
ii. Depletion Mode
Compare Enhancement and Depletion MOSFET. K2
Enhancement MOSFET Depletion MOSFET
The electric field increases the The electric field reduces the
number of majority carriers in the number of majority carriers in
conducting region. the conducting region.
25 No conducting channel between Channel exists even with zero
source and drain unless a positive Vgs. A negative gate voltage is
voltage is applied. applied to control the channel.
Enhancement-mode device is Depletion-mode device is
equivalent to a normally open (off) equivalent to a
switch. normally closed (on) switch.
26 Draw the symbol of pMOS and nMOS transistor. K1

27 What do you mean by accumulation mode?

When gate source voltage V Gs is less than threshold voltage (Vt) there is no
conduction between source and drain and no channel is formed. The device is in K1
OFF condition. This mode is called accumulation.

4
28 What is depletion mode?
When VGs is increased greater than threshold voltage VT, the electrons are
attracted towards the gate and the holes are repelled away from gate. Thus K1
depletion region is formed under the gate. This is called depletion mode.

29 What is inversion mode?

When VGs is increased above VT , the electrons are attracted to the gate region.
The surface of the underlying p-type is said to be inverted to n-type. This
K1
creates a conduction path between source and drain and the device is in 'ON'
condition. This mode is called inversion mode.

30 What are the parameters affecting the magnitude of drain to source

current?
i. Distance between source and drain
ii. Channel length
iii. Threshold voltage K1
iv. Thickness of gate oxide layer
v. Dielectric constant
vi. Carrier mobility
31 What do you mean by CMOS?
CMOS (Complementary Metal OXIDE Semiconductor) have both n-MOS and
pMOS fabricated in the same IC. K1

32 Write the advantages of CMOS over NMOS.

i. Aluminum gates are replaced by silicon gates.
ii. Low power consumption K1
iii. Easily scalable than NMOS.
33 State the merits and Demerits of CMOS.
Merits
i. Low power consumption
ii. High performance
iii. Scalable threshold voltage
iv. High noise margin K1
v. Low output drive current
Demerits
i. Low resistance to process deviation and temperature
ii. Lesser switching speed at large capacitive loads.
34 Define noise margin.
Noise margin defines the maximum allowable noise voltage on the input so that
the output is not affected. There are two types of noise margin. K1
i. Low noise margin
ii. High noise margin
What are the types of fabrication of CMOS?
i. p-well process
35 ii. n-well process K1
iii. Twin tub process
iv. Silicon on Insulator
36 What do you mean by latch-up? K1
Latch-up creates a short circuit from positive supply voltage to ground. It
occurs when,
i. Parasitic components form low resistance conducting path between
5
 VDD and ground.
ii. Gain of two transistors β 1−β 2> 1
37 How tristate inverter is formed?
Tristate inverter is obtained by connecting the transmission gate in series with K1
an inverter.
38 How latch-up is prevented?
i. Reduce the gain product β 1−β 2> 1
K1
ii. Reduce the well and substrate resistances.

39 What are the types of process parameters?

i. PASS/FAIL parameters
K1
ii. Information parameters

40 Summarize the MOS transistor characteristics.

Metal Oxide Semiconductor is a three terminal device having source, drain and
gate. The resistance path between the drain and the source is controlled by
applying a voltage to the gate. The Normal conduction characteristics of an K2
MOS transistor can be categorized as cut-off region, Non saturated region and
saturated region.
41 Define propagation delay.
Propagation delay is defined as the time interval between the instant of applying
input to the gate and the instant at which stable output is obtained. K1

42 What do you mean by logical effort?

Logical effort is defined as the ratio of input capacitance of the gate to the input
capacitance of an inverter with same output current. K1

43 Why do we need scaling?

Scaling is required to
i. Reduce gate delay
K1
ii. Minimize power dissipation
iii. Improve package density

44 What is the threshold voltage of a MOS transistor? How it varies with the
body bias?
One of the parameters that characterize the switching behavior of a MOS
transistor is its threshold voltage Vt. This can be defined as the gate voltage at
which a MOS transistor begins to conduct. For enhancement mode, the n-mos
MOSFET body effect upon threshold voltage is given as K1
V tn =V t 0+ γ ¿
Where, Vtn is threshold voltage when substrate is present, Vsb is the source to
body substrate bias, 2ϕf is the source potential and Vto is the threshold voltage
for zero substrate bias

45 What is channel length modulation effect? How the voltage current K1

characteristics are affected because of this effect?
It is assumed that channel length remains constant as the drain voltage is
increased appreciably beyond the onset of saturation. As a consequence, the
drain current remains constant in the saturation region. In practice, however the
channel length shortens as the drain voltage is increased. For long channel
shortens as the drain voltage is increased. For long channel lengths, say more
6
 than 5µm, this variation of length is relatively very small compared to the total
length and is of little consequence. However, as the device sizes are scaled
down, the variation of length becomes more and more predominant and should
be taken into consideration. As a consequence, the drain current increases with
the increase in drain voltage even in the saturation region

46 What is body effect? How does it influence the threshold voltage of a MOS
transistor?
All MOS transistors are usually fabricated on a common substrate and substrate
(body) voltage of all devices is normally constant. When circuits are realized
using a number of MOS devices, several devices are connected in series. This
results in different source potentials for different devices. It may be noted that K1
the threshold voltage V, is not constant with respect to the voltage difference
between the substrate and the source of the MOS transistor. This is known as
the substrate-bias effect or body effect. Increasing the Vsb causes the channel to
be depleted of charge carries and this leads to increase in the threshold voltage.

47 What is the latch up problem that arises in bulk CMOS technology?

The latch-up is an inherent problem in both n-well as well as p well based
CMOS circuits. The phenomenon is caused by the parasitic bipolar transistors
for a in the bulk of silicon for the n-well process. Latch-up can be defined as the
formation of a low-impedance path between the power supply and ground rails
through the parasitic npn and pnp bipolar transistors. The BJTs are cross-
K1
coupled to form the structure of a silicon-controlled-rectifier (SCR) providing a
short-circuit path between the power rail and ground. Leakage current through
the parasitic resistors can cause one transistor to turn on, which in turn turns on
the other transistor due to positive feedback and leading to heavy current, flow
and consequent device failure.

48 How the latch up problem can be overcome?

There are several approaches to reduce the tendency of Latch-up. Some of the
important techniques are mentioned below:
i. Use guard ring around p- and/or n-well with frequent contacts to the
rings
ii. To reduce the gain product B1XB2 K1
iii. Moving the n-well and the n+ source/drain further apart
iv. Buried n+ layer in well to reduce gain of Q1
v. Higher substrate doping level to reduce R-sub
vi. Reduce R-well by making low resistance contact to GND

49 Outline the secondary effects of MOS transistor.

i. Threshold voltage variations
ii. Source to drain resistance
K2
iii. Variation in I-V characteristics
iv. Sub threshold conduction
v. CMOS latch up
50 In saturation region, what are the factors that affect Ids?
i. Distance between source and drain.
ii. Channel width
iii. Threshold voltage K1
iv. Thickness of oxide layer
v. Dielectric constant of gate insulator
vi. Carrier mobility.
7
51 Write the threshold voltage equation including the body effect?
V t =V fb +2 φb+
√ 2 εq N a (2 φb+V sb) K1
C ox

52 What is twin-tub process? Why it is called so?

Twin-tub process is one of the CMOS technologies. There are two wells are
available in this process. The other name of well is tub. So, because of these K1
two tubs, this process is known as twin-tub process.

53 Draw the circuit of a CMOS inverter.

K1

54 What are the advantages of CMOS inverter over the other inverter
configurations?
i. The steady state power dissipation of the CMOS inverter circuit is
negligible. K1
ii. The voltage transfer characteristic (VTC) exhibits a full output voltage
wing between 0V and VDD. This results in high noise margin.

55 What are stick diagrams?

Stick diagrams are used to convey layer information through the use of a color
code. It uses ‘Sticks’ or 'lines' to represents the devices and conductors. A stick
diagram is a cartoon of a chip layout. They are not exact models of layout. The K1
stick diagram represents the rectangles with lines which represent wires and
component symbols.

56 What are design rules?

Design rules are the communication link between the designer specifying
requirements and the fabricator who materializes them. Design rules are used to
produce workable mask layouts from which the various layers in silicon will be
formed or patterned. The design rule conform to a set of geometric constraints K1
or rule specify the minimum allowable line widths for physical objects on-chip
such as metal and poly silicon interconnects or diffusion area, minimum feature
dimensions and minimum allowable separations between two layers.

8
57 Draw the ideal characteristics of a CMOS inverter and compare it with the
actual characteristics.
The ideal and actual characteristics are given below. In the ideal characteristics,
the output voltage is Vdd for input voltage from o to Vdd/2 and 0 for input
voltage from Vdd/2 to Vdd. This is not true in case of the actual characteristics
as shown below.

K1

58 What is noise margin? Find out the noise margin from the actual
characteristics of the inverter.
An important parameter called noise margin is associated with the input-output
voltage characteristics of a gate. It is defined as the allowable noise voltage on
the input of a gate so that the output is not affected. The deviations in logic
levels from the ideal values, which are restored as the signal propagates to the
output, can be obtained from the DC characteristic curves. The logic levels at
the input and output are given by
The noise margins are: K1
NM L =|V IL−V OL|
NM H =|V OH −V IH|
Logic 0 input: 0 ≤ V I ≤ V IL
Logic 1 input: V IH ≤ V L ≤V dd
Logic 0 input: 0 ≤ V 0 ≤ V 0 L
Logic 1 input: V 0 H ≤ V 0 ≤V dd
59 Interpret the capacitance of a MOS capacitor.
The capacitance of a parallel plate capacitor is given
ε 0 ε ins A
C 0= Farads
D K2
Where A is the area of the plates and D is the thickness of the insulator between
the plates.

60 Explain the basic concepts of supply voltage scaling.

Power dissipation is proportional the square of the supply voltage. So, a factor
of two reductions in supply voltage yields a factor for decrease in energy. But,
as the supply voltage is reduced, delay increases as shown in the diagram. So, K2
the challenge is to scale down the supply voltage without compromise in
performance.
61 Compare constant field and constant voltage feature size scaling. Compare
their advantages and disadvantages.
K2
In this approach the magnitude of all the Internal electric fields within the
device are preserved, while the dimensions are scaled down by a factor of S.
9
 This requires that all potentials must be scaled down by the same factor.
Accordingly, supply as well as threshold voltages are scaled down
proportionately.
But, in constant-voltage scaling, all the device dimensions are scaled down by a
factor of S just like constant-voltage scaling, supply voltage and threshold
voltages are not scaled

62 Compare the constant field and constant voltage scaling approaches in

terms of area, delay, energy and power density parameters.

Quality Constant Field Constant Voltage

Scaling Scaling
Gate Capacitance C'g =Cg /S C'g =Cg /S K2
Drain Current I'D=ID/S I'D=ID.S
Power Dissipation P' = P/ S2 P' = P.S2
Power Density P' / Area' = (P / Area) P' / Area' = S3P / Area
Delay td = td / S td = td/S2
Energy E'=E/S3 E'=E/S
63 What is micron design rule?
Micron rules specify the layout constraints such as minimum feature sizes and
minimum allowable feature separations are stated in terms of absolute K1
dimensions in micrometers.

64 What is Lambda design rule?

Lambda rule specify the layout constraints such as minimum feature sizes and
minimum allowable feature separations are stated in terms of a single parameter K1
(λ) and thus allow linear, proportional scaling of all geometrical constraints.
65 What is DRC?
Design Rule Check program looks for design rule violations in the layout. It
checks for minimum spacing and minimum size and ensures that combinations K1
of layers from legal components.
66 Compare NMOS and PMOS.

NMOS PMOS
The majority carriers are electrons The majority carriers are holes
Positive voltage is applied at the Negative voltage is applied at the
K2
gate terminal gate terminal
NMOS conducts at logic 1 PMOS conducts at logic 0
Mobility of electron is high Mobility of electron is low
Switching speed is high Switching speed is low

24.
PART B & PART C (13 & 15 Marks)
67 Explain with a neat layout, the design rules for a CMOS inverter. 13 K2
68 Illustrate with necessary equation the operation of MOSFET and its 13 K2
current voltage characteristics.
69 Draw and explain the D.C and transfer characteristics of a CMOS 15 K2
inverter with a necessary condition for the different regions of
operation.
70 Outline the principle of constant field scaling and also write its 13 K2
effect on device characteristics.
71 Explain the small signal model of MOS transistors with neat 15 K2
10
 diagram and expression.
72 Draw the stick diagram and layout of a NMOS inverter. 13 K1
73 Derive an expression for Vin of a CMOS inverter to achieve the 15 K2
condition Vin = Vout, What should be the relation for βn = βp.
74 Explain about the scaling concept and reliability concept. 13 K2
75 Explain about the resistive and capacitive delay estimation of a CMOS 13 K2
Inverter circuit.
76 Discuss the CV characteristics of the CMOS 13 K1
77 Explain about the I-V characteristics of MOS transistor 13 K2
Illustrate the non ideal I-V characteristics of MOS transistor with 15 K2
78 necessary equations.
Explain briefly about the impact of RC Delay model and Elmore delay 13 K2
79 model in CMOS design.

11
 UNIT II COMBINATIONAL MOS LOGIC CIRCUITS
PARTA

S.No. Questions and Answers Knowledge

Level
Define Elmore delay model. K1
1 It is an analytical method used to estimate the RC delay in a network. Elmore
delay model estimates the delay of a RC ladder as the sum over each node in the
ladder of the resistance Rn-1 between that node and a supply multiplied by the
capacitor on the nodes.
N N i
t pd=∑ R n−1 C i=∑ Ci ∑ R j
i i=1 j=1
2 What are the general properties of Elmore delay model? K1
General property of Elmore delay model network has
i. Single input node
ii. All the capacitors are between a node and ground
iii. Network does not contain any resistive loop
3 What are the types of power dissipation? K1
i. Static power dissipation (due to leakage current when the circuit is idle).
ii. Dynamic power dissipation(when the circuit is switching) and
iii. Short –circuit power dissipation during switching of transistors.

4 What is static power dissipation? K1

Power dissipation due to leakage current when the circuit is idle is called as the
static power dissipation. Static power arises due to
i. Sub – threshold conduction through OFF transistors
ii. Tunneling current through gate oxide
iii. Leakage through reverse biased diodes
iv. Contention current in radioed circuits.

5 What is Dynamic power dissipation? K1

Power dissipation is due to circuit switching to charge and discharge the output
load capacitance at a particular node at operating frequency is called Dynamic
power dissipation.
The Dynamic power dissipation at a particular output node is given by
Pd = CL Vdd^2 Fclk. a
Where, CL = load capacitance; a = activity factor; Vdd =power supply;
Fclk= operating frequency
6 What are the methods to reduce dynamic power dissipation? K1
i. Reduce the product of capacitance and its switching frequency.
ii. Eliminate logic switching that is not necessary for computation.
iii. Reduce activity factor
iv. Reduce supply voltage
7 Outline the methods to reduce static power dissipation. K2
i. By selecting multi threshold voltages on circuit paths with low-Vt
transistors while leakage on other paths with high-Vt transistors.
ii. By using two operating modes, active and standby for each function
blocks.
iii. By adjusting the body bias (i.e) adjusting FBB (Forward Body Bias) in
active mode to increase performance and RBB (Reverse Body Bias) in
standby mode to reduce leakage.
12
 iv. By using sleep transistors to isolate the supply from the block to achieve
significant leakage power savings.

8 What is short circuit power dissipation? K1

During switching, both NMOS and PMOS transistors will conduct
simultaneously and provide a direct path between Vdd and the ground rail
resulting in short circuit power dissipation.
9 Define design margin. K1
The additional performance capability above required standard basic system
parameters that may be specified by a system designer to compensate for
uncertainties is called design margin. Design margin required as there are three
sources of variation- two environmental and one manufacturing.
10 Write the applications of transmission gate. K1
i. Multiplexing element of path selector
ii. A latch element An unlock switch
iii. Act as a voltage controlled resistor connecting the input and output.

11 What is pass transistor? K1

It is a MOS transistor, in which gate is driven by a control signal the source
(out), the drain of the transistor is called constant or variable voltage potential
(in) when the control signal is high, input is passed to the output and when the
control signal is low, the output is floating topology such topology circuits is
called pass transistor.
12 List the advantages of pass transistor. K1
i. Pass transistor logic (PTL) circuits are often superior to standard CMOS
circuits in terms of layout density, circuit delay and power consumption.
ii. They do not have path VDD to GND and do not dissipate standby
power (static power dissipation).

13 Interpret the term transmission gate. K2

The circuit constructed with the parallel connection of PMOS and NMOS with
shorted drain and source terminals. The gate terminal uses two select signals s
and s bar, when s is high than the transmission gates passes the signal on the
input. The main advantage of transmission gate is that it eliminates the
threshold voltage drop.
14 Why low power has become an important issue in the present day VLSI K1
circuit realization?
In deep submicron technology the power has become as one of the most
important issue because of:
i. Increasing transistor count; the number of transistor is getting doubled in
every 18 months based on Moore’s law.
ii. Higher speed of operation; the power dissipation is proportional to clock
frequency.
iii. Greater device leakage current; in nanometer technology the leakage
component become a significant percentage of the total power and the
leakage current increases at a faster rate than dynamic power in
technology generations.

15 What are the various ways to reduce the delay time of a CMOS inverter? K1
i. the width of the MOS transistor can be increased to reduce delay. This is
known as gate sizing.
ii. the load capacitance can be reduced to reduce delay. This is achieved by
using transistor of smaller and smaller dimension by feature generation
13
 technology.
iii. delay can also be reduced by increasing the supply voltage Vdd and/or
reducing the threshold voltage Vt of the MOS transistors

16 Outline the basic operation of a 2- phase dynamic circuit. K2

The operation of the circuit can be explained using precharge logic in which the
output is precharged to HIGH level during Φ2 clock and the output is evaluated
during Φ1 clock.
17 What makes dynamic CMOS circuits faster than static CMOS circuits? K1
As MOS dynamic circuits require lesser number of transistors and capacitance
is to be driven by it. This makes MOS dynamic circuits faster.
18 What is glitching power dissipation? K1
Because of finite delay of the gates used to realize boolean functions,different
signals cannot reach the inputs of a gate simultaneously.this leads to spurious
transition at the output before it settles down to its final value.the spurious
transitions leads to charging and discharging of the outputs causing glitching
power dissipation. It can be minimized by having balanced realization having
same delay at the inputs.

19 List various sources of leakage currents. K1

Various source of leakage currents are listed below:
I1=Reverse-bias p-n junction diode leakage current.
I2=band-to-band tunneling current
I3=Subthreshold leakage current
I4=Gate oxide tunneling current
I5=Gate current due to hot carrier junction
I6=Channel punch through
I7=Gate induced drain leakage current

20 Compare clock gating and power gating approaches. K2

Clock gating minimizes dynamic power by stopping unnecessary transitions,
but power gating minimizes leakage power by inserting a high Vt transistor in
series with low Vt logic blocks.
21 What are the advantages of using a pseudo n-MOS gate instead of a full K1
CMOS gate?
i. Neither high-value resistors nor depletion mode transistors are readily
available as static loads in most CMOS processes.
ii. The static load is built from a single pMOS transistor that has its gate
grounded so it is always ON.
iii. The DC transfer characteristics are derived by finding Vout for which
Ids= Idsp I for a given Vin.
iv. The beta ratio affects the shape of the transfer characteristics and the
VoL of the inverter.
22 Draw a pseudo NMOS inverter. K1

14
23 Classify the CMOS family. K2
i. Static CMOS
ii. Dynamic CMOS
iii. Ratioed circuits
iv. Pass transistor
24 Write a note on CMOS transmission gate logic. K1
A single nMOS or pMOS pass transistor suffers from a threshold drop. If used
alone, additional circuitry may be needed to pull the output to the rail.
Transmission gates solve this problem but require two transistors in parallel.
The resistance of a unit-sized transmission gate can be estimated as R for the
purpose of delay estimation. Current flows through the parallel combination of
the nMOS and pMOS transistors. One of the transistors is passing the value
well and the other is passing it poorly; for example, a logic 1 is passed well
through the pMOS but poorly through n MOS.
25 Given the choice between NOR or NAND logic, which one would you K2
prefer for implementation in pseudo-NMOS. Why?
NOR logic would be more sensible to implement in pseudo-NMOS logic since
you will have a pull-down network of parallel transistors as opposed to a chain
of transistors in series. A design in NOR logic would therefore most likely be
faster than the NAND logic.
26 What is meant by logical effort? K1
Logical effort of each input is the ratio of the input capacitance of input to the
input capacitance of the inverter.
27 What is parasitic delay? K1
Parasitic delay is estimated from the total diffusion capacitance on output node
by summing the sizes of the transistors attached to the output. Parasitic delay is
defined as the ratio of the parasitic capacitance to the input capacitance of the
inverter.
28 Define effort delay. K1
The delay that depends on the load and on properties of the logic gate driving
the load.
f = gh
where g — logical effort of gate, h — electrical effort of load.
29 What is path logical effort? K1
The path logical effort is the product of the logical efforts of all the logic gates
along the path.
G = π gi
30 Illustrate the following expression in a full static CMOS logic fashion using K2
no more than 10 transistors:
Y = (A.B) + (A.C.E) + (D.E) + (D.C.B)

15
31 What are glitches? K1
The finite propagation delay from one logic block to the next causes spurious
transitions. These transitions are called as glitches or dynamic hazards. A node
can exhibit multiple transitions in a single clock cycle before settling to the
correct logic level.
32 What is electrical effort? K1
Electrical effort is the ratio of the input capacitance of the load to that of the
gate. Logical effort does not take the load into account and hence we have the
term “electrical effort” which takes the load into account.
33 What is a bleeder transistor? K1
In order to cope up with leakage currents, we include a bleeder transistor to the
circuit. This transistor helps to compensate the sub threshold current of the cut-
off transistor with its current.
34 Define ratioed logic. K1
It is used to reduce the number of transistors required to implement a given
logic function. Pull up network pulls Vout to Vdd & pull down network pulls
Vout to Vss in case of Vin=1. This output is called “ratioed logic or non zero
output”.
35 Define activity factor. K1
The node transition activity factor is a statistical parameter and is data
rate dependent and defines the probability of the gate's output to make logic
transition during one clock cycle.
36 How sub threshold current occurs? K1
It is due to carrier diffusion between the source and drain region when transistor
is in inversion. Sub threshold current becomes significant when Vgsd>Vt. At
this point sub threshold current occurs.
37 What are static circuits? K1
In static circuits, at every point of time, each gate output is connected to either
VDD or Vss via a low-resistance path. The outputs of the gates assume at all
times the value of the Boolean function implemented by the circuit.
38 What is branching effort? K1
Branching effort b of a logical gate on a given path is
C on path +C off path
b=
C on path
where Con-path is the load capacitance of the gate along the path we analyze
and Coff path is the capacitance of the connections that lead off the path.
39 What are the properties of Domino Logic? K1
i. Since each dynamic gate has a static inverter, only non-inverting logic
can be implemented.
ii. Very high speeds can be achieved.
40 What are the properties of dynamic logic gates? K1
i. The logic function is implemented by the NMOS pull-down network.
ii. The number of transistors is lower than that in static case: N+2 versus
2N
iii. It is non-ratioed
iv. The logic gates have faster switching speeds.
41 What are the static properties of complementary CMOS gates? K1
They exhibit rail-to-rail swing with V0H=VDD and V0L=GND
The circuits have no static power dissipation, since the circuits are designed
such that the pull-down and pull-up networks are mutually exclusive.
The analysis of the DC voltage transfer characteristics and the noise margin is
more complicated than for the inverter, as these parameters depends upon the
16
 data input patterns applied to the gate.
42 What do you mean by combinational circuits? K1
Combination logic circuits operate on multiple input variables and produces
outputs as Boolean function of the input. The output of the combinations circuit
depends on the combination of the input values.
43 Compare static and dynamic CMOS. K2

Dynamic CMOS
Static CMOS
The output of gate depends on the The output of gate depends on temporary
Boolean function implemented by storage of signal values on the
the circuit. capacitance of nodes.
44 Define degree of skewing. K1
The degree of skewing is defined as the ratio of effective resistance for the fast
transition relative to the slow transition.
45 What is unskewed gate? K1
βp V
If =1, the inverter threshold voltage is DD .This gate is said to be
βn 2
unskewed gate. It increases the noise margins and the capacitance load charges
and discharges in equal times.

46 What is skewed gate? K1

βp
Gates with different beta ratios are called skewed gates.
βn
βp
If >1, gate is HI skewed.
βn
βp
If <1, gate is LO skewed.
βn

47 Why do we require multiple threshold? K1

i. To reduce leakage current
ii. To reduce path delay
iii. To increase switching speed.
iv. To isolate logic gates.
48 What are the main levels that effect critical path of a system? K1
i. Architectural level
ii. Logical level
iii. Circuit level
iv. Layout level
49 Define critical path. K1
Critical path is defined as the longest path in the circuit which decides the most
critical function and timing details are considered important.
50 What is intrinsic delay? K1
Intrinsic delay is defined by the product of resistance and capacitance.
τ = RC
51 Define absolute delay. K1
Absolute delay as defined as the product of a unit delay of the gate and the
delay unit that characterize a given process.
dabs = dτ

52 How reliability of a VLSI circuit is related to its power dissipation? K1

It has been observed that every 10°C rise in temperature roughly doubles the
17
 failure rate because various failure mechanism such as silicon interconnect
fatigue, electro migration diffusion, junction diffusion and thermal runaway
starts occurring as temperature increases.
53 Why leakage power dissipation has become an important issue in deep K1
submicron technology?
In deep submicron technology the leakage component becomes a significant
percentage of the total power and the leakage current increases at a faster rate
than dynamic power. in new technology generations. That is why the leakage
power has become an important issue.

54 Interpret the expression of delay time of a CMOS inverter. K2

The delay time td is given by the expression

[
t d=
Ln
+
Lp
] CL

( )
2
K nW n K pW p Vt
V dd 1−
V dd
Where C is the load capacitance, Vdd is the supply voltage and Vt is the
threshold voltages of the MOS transistors.
55 For a complex/compound CMOS logic gate, how do you realize the pull-up K2
and the pull-down networks?
A CMOS logic gate consists of a nMOS pull-down network and a pMOS pull-
up network. The nMOS network is connected between the output and the
ground, whereas the pull-up network is connected between the output and the
power supply. The nMOS network corresponds to the complement of the
function either in sum-of-product or product-of-sum forms and the pMOS
network is dual of the nMOS network .
56 Give the two possible topologies AND-OR-INVERT (A0I) and OR-AND- K2
INVERT (OAI) to realize CMOS logic gate. Explain with an example.
The AND-OR-INVERT network corresponds to the realization of the nMOS
network in sum-of-product form. Whereas the OR-AND-INVERT network
corresponds to the realization of the nMOS network in product-of-sum form. In
both the cases, the pMOS network is dual of the nMOS network.
57 How do you realize pseudo nMOS logic circuits. Compare its advantage K2
and disadvantages with respect to standard static CMOS circuits.
In the pseudo-nMOS realization, the pMOS network of the static CMOS
realization is replaced by a single pMOS transistor with its gate connected to
GND. An n-input pseudo nMOS requires n+1 transistors compared to 2n
transistors of the corresponding static CMOS gates. This leads to substantial
reduction in area and delay in pseudo nMOS realization. As the pMOS
transistor is always ON, it leads to static power dissipation when the output is
LOW.
58 In what way relay logic circuits differ from pass transistor logic circuits? K2
Why the output of a pass transistor circuit is not used as a control signal
for the next stage?
Logic functions can be realized using pass transistors in a manner similar to
relay contact networks. However, there are some basic differences as mentioned
below:
i. In relay logic, output is considered to be '1' when there is some voltage
passing through the relay logic. Absence of voltage is considered to be
'0'. On the other hand, in case of pass transistor logic it is essential to
provide both charging and discharging path for the output load
capacitance.
ii. There is no voltage drop in the relay logic, but there is some voltage

18
 drop across the pass transistor network.
iii. Pass transistor logic is faster than relay logic.
59 Outline the advantages and limitations of pass transistor logic circuits. K2
How the limitations are overcome?
Pass transistor realization is ratioless, i.e. there is no need to have L:W ration in
the realization. All the transistors can be of minimum dimension. Lower area
due to smaller number of transistors in pass transistor realization compared to
static CMOS realization. Pass transistor realization also has lesser power
dissipation because there is no static power and short-circuit power dissipation
in pass transistor circuits.
The limitations are
i. Higher delay in long chain of pass transistors
ii. Multi-threshold Voltage drop ( Vout = Vdd – Vtn)
iii. Complementary control signals
iv. Possibility of sneak path because of the presence of path to Vdd and
GND.

60 What are the key characteristics of MOS dynamic circuits? K1

The advantage of low power of static CMOS circuits and smaller chip area of
nMOS circuits are combined in dynamic circuits leading to circuits of smaller
area and lower power dissipation. Smaller area due to lesser number of
transistors (n+2) compared to static CMOS realization requiring 2n transistors
to realize a n-variable function. Dynamic CMOS circuits have Lower static
power dissipation because of smaller capacitance. There is no short circuit
power dissipation and no glitching power dissipation. No contention during
switching. Dynamic CMOS circuits are also faster because the capacitance is
about half that of the static CMOS circuits.
61 What makes dynamic CMOS circuits faster than static CMOS circuits? K1
As MOS dynamic circuits require lesser number of transistors and lesser
capacitance is to be driven by it. This makes MOS dynamic circuits faster.
62 Compare the sources of power dissipation between static CMOS and K2
dynamic CMOS circuits.
In both the cases there is switching power and leakage power dissipations.
However, the short circuit and glitching power dissipations, which are present
in static CMOS circuits, are not present in dynamic CMOS circuits.
63 What is charge leakage problem of dynamic CMOS circuits? How is it K1
overcome?
The source-drain diffusions form parasitic diodes with the substrate. There is
reverse bias leakage current .The current is in the range 0.1 nA to 0.5nA per
device at room temperature and the current doubles for every 10°C increase in
temperature. This leads to slow but steady discharge of the charge on the
capacitor, which represent information. This needs to be compensated by
refreshing the charge at regular interval.
64 Explain the clock skew problem of dynamic CMOS circuits. K2
Clock skew problem arises because of delay due to resistance and parasitic
capacitances associated with the wire that carry the clock pulse and this delay is
approximately proportional to the square of the length of the wire. When the
clock signal reaches a later stage before its preceding stage, the precharge phase
of the preceding stage overlaps with the evaluation phase of the later stage,
which may lead to premature discharge of the load capacitor and incorrect
output during evaluation phase.
65 How clock skew problem is overcome in in domino CMOS circuits? K1
In domino CMOS circuits the problem is overcome by adding an inverter as
19
 shown in the diagram. It consists of two distinct components: The first
component is a conventional dynamic CMOS gate and the second component is
a static inverting CMOS buffer. During precharge phase, the output of the
dynamic gate is high, but the output of the inverter is LOW. As a consequence
it cannot drive an nMOS transistor ON. So, the clock skew problem is
overcome.
66 How clock skew problem is overcome in in NORA CMOS circuits? K1
The problem can be overcome using NORA logic, nMOS and pMOS transistor
networks are alternatively used. The output of an nMOS block is HIGH during
precharge, which cannot turn a pMOS transistor ON. Similarly, the output of an
pMOS block is LOW during precharge, which cannot turn a nMOS transistor
ON.

67 Justify the statement; "there is no short circuit power dissipation in a static K2

CMOS circuit if Vdd < (Vtn + |V tp|).
When Vdd < (Vtn + |V tp|), only one transistor can turn on at a time. Since both
the transistors cannot turn on simultaneously, there is no short circuit power
dissipation.

68 What is band-to-band tunneling? K1

When both n regions and p regions are heavily doped, a high electric field
across a reverse biased p-n junction causes significant current to flow through
the junction due to tunneling of electrons from the valence bond of the p-region
to the conduction band of n-region. This is known as band-to-band tunneling.
69 What is body effect? K1
As a negative voltage is applied to the substrate with respect to the source, the
well-to-source junction the device is reverse biased and bulk depletion region is
widened. This leads to increase the threshold voltage. This effect is known as
body effect.
70 What is subthreshold leakage current? List the various mechanisms K1
responsible for this leakage current.
The subthreshold leakage current in CMOS circuits is due to carrier diffusion
between the source and the drain regions of the transistor in weak inversion,
when the gate voltage is below Vt. The behavior of an MOS transistor in the
subthreshold operating region is similar to a bipolar device, and the
subthreshold current exhibits an exponential dependence on the gate voltage.
The amount of the subthreshold current may become significant when the gate-
to-source voltage is smaller than, but very close to the threshold voltage of the
device.
71 Explain how parallelism can be used to achieve low power instead of high K2
performance in realizing digital circuits.
Traditionally, parallelism is used to improve performance at the expense of
larger power dissipation. But, instead of trying to improve performance, the
power dissipation can be reduced by scaling down the supply voltage such that
the performance remains unaltered.
72 Explain how multicore architecture provides, low power compared to the K2
single core architecture of the same performance.
The idea behind the parallelism for low-power can be extended to multi-core
architecture. The clock frequency can be reduced with commensurate scaling of
the supply voltage as the number of cores is increased from one to more than
one while maintaining the same throughput.
73 How clock frequency, speed up, throughput and power dissipation changes K1
for a pipelined implementation with k stages with respect to non-pipelined
20
 implementation?
Clock frequency=kf
nk
Speed up=Sk =
k + ( n−1 )
where n is the number of tasks executed using k-stage pipeline, and power
dissipation = 1/k2.
74 How can you combine sizing and supply voltage scaling to realize low K1
power circuits?
It can be done in three steps
i. Upsize gates on the critical path to reduce delay of the circuit
ii. Scale down the supply voltage to equalize with the original delay
iii. Upsize gates on non-critical paths selectively without exceeding the
critical path delay.
75 Explain the basic concept of multi level voltage scaling. K2
This is an extension of SVS where two or few fixed voltage domains are used in
different parts of a circuit,. As we know, high Vdd gates have less delay, but
higher dynamic and static power dissipation and low Vdd gates have larger
delay but lesser power dissipation. Voltage islands can be generated at different
levels of granularity, such as macro level and standard cell level. The slack of
the off-critical path can be utilized for allocation of macro modules of low-Vdd
to offcritical-path macro modules. Total power dissipation can be reduced
without degrading the overall circuit performance.
76 Outline the important issues in the context of multiple supply voltage K1
scaling.
Important issues in the context of MVS are listed below:
i. Voltage Scaling Interfaces
ii. Converter Placement
iii. Floor planning, Routing and Placement
iv. Multiple Supply Voltages
v. Static Timing Analysis
vi. Power up and Power down Sequencing
vii. Clock distribution
77 What problem arises when a signal passes from low voltage domain to high K1
voltage domain? How this problem is overcome?
A high-level output from the low-Vdd domain has output VddL, which may
turn on both nMOS and pMOS transistors of the high-Vdd domain inverter
resulting in short circuit between VddH to GND. A level converter needs to be
inserted to avoid this static power consumption
78 Explain the basic concept of clock gating to reduce power dissipation in a K2
digital circuit.
It has been observed that a major component of processor power is the clock
power (50% of the total power). So, there is scope for large reduction of power
dissipation by using suitable technique to remove a large number of
unnecessary transitions. Such transitions can be suppressed without affecting
functionality. One of the most successful and commonly used low power
technique is clock gating.
79 Interpret the important issues related to clock gating in the clock tree. K2
Clock tree amounts to a significant portion of the total dynamic power
consumption. It leads to a tradeoff between the physical capacitance that is
prevented from switching and the number of unnecessary transitions. Disabling
at higher up in the tree prevents larger capacitance from switching, but the
gating condition is satisfied fewer times. Having multiple gating points along a
path may be beneficial.
21
80 What are the three levels of clock gating granularity? Compare their pros K2
and cons.
There are three levels of granularity:
i. Module-level clock gating: Large reduction in power but there is limited
opportunity.
ii. Register-level clock gating: There is more opportunity compared to
module level clock gating, but lesser reduction of power.
iii. Cell-level clock gating: Provides many more opportunities and it lends
itself
to automated insertion and can result in massively clock gated designs.
81 What are the potential logic styles for the realization of low power high K1
performance CMOS circuits?
Potential Logic Styles are
i. Static CMOS Logic
ii. Dynamic CMOS Logic
iii. Pass-Transistor Logic (PTL)

Static CMOS Logic

Advantages
i. Ease of fabrication
ii. Good noise margin
iii. Robust
iv. Lower switching activity
v. Good input/output decoupling
vi. No charge sharing problem
vii. Availability of matured logic synthesis tools and techniques

Disadvantages
i. Larger number of transistors (larger chip area and delay)
ii. Spurious transitions (glitch) due to finite propagation delays leading to
extra power dissipation and incorrect operation
iii. Short circuit power dissipation Weak output driving capability
iv. Large number of standard cells requiring substantial engineering effort
for technology mapping

Dynamic CMOS Logic

Advantages
i. Combines the advantages of low power of static CMOS and low chip
area of pseudo-nMOS
ii. Reduced number of transistors compared to static CMOS (n+2 versus
2n)
iii. Faster than static CMOS logic
iv. No short circuit power dissipation
v. No spurious transition and glitching power dissipation

Disadvantages
i. Higher switching activity
ii. Not as robust as static CMOS logic
iii. Clock skew problem in cascaded realization
iv. Suffers from charge sharing problem
v. Mature synthesis tool not available

Pass-Transistor Logic

22
 Advantages
i. Lower area due to smaller number of transistors and smaller input loads
ii. Ratio-less PTL allows minimum dimension transistors and hence makes
area efficient circuit realization
iii. No short circuit current leading to lower power dissipation

Disadvantages
i. Increased delay due to long chain pf pass-transistors
ii. Multi-threshold voltage drop
iii. Dual-rail logic to provide all signals in complementary form
iv. There is possibility of sneak path
82 Compare standby and runtime leakage power. Why runtime leakage K2
power is becoming important in the present day context?
Standby leakage power dissipation takes place when the circuit is not in use, i.e.
inputs do not change and clock is not applied. On the other hand, runtime
leakage power dissipation takes place when the circuit is being used.
83 How supply voltage scaling leads to run time leakage power reduction? K1
Supply voltage reduction not only leads to the reduction of dynamic power, it
also leads to the reduction of leakage power. The subthreshold leakage due to
GIDL and DIBL decreases as supply voltage is scaled down. It has also been
demonstrated that the supply voltage scaling impacts in the orders of V3 and V4
on subthreshold leakage and gate leakage, respectively.
84 Compare VTCMOS and MTCMOS for leakage power reduction. K2
In case of VTCMOS, basic principle is to adjust threshold voltage by changing
substrate bias. Transistors initially have low Vth during normal operation and
substrate bias is altered using substrate bias control circuit. The threshold is
increased by using reverse body bias when the circuit is not in use. Effective in
reducing leakage power dissipation in standby mode and it involved additional
area and higher circuit complexity. So, it is a post-silicon approach.
On the other hand, in case of MTCMOS approach MOS transistors of multiple
threshold voltages are fabricated in which a power gating transistor is inserted
in the stack between the logic transistors and either power or ground, thus
creating a virtual supply rail or a virtual ground rail, respectively. The logic
block contains all low-Vth transistors for fastest switching speeds while the
switch transistors, header and footer, are built using high-Vth transistors to
minimize the leakage power dissipation. So, it is a pre-silicon approach.
85 Outline the concept of dual Vt assignment for the reduction of leakage K2
power.
This is based on the observation that all gates are not on the critical path when
the circuit is represented with the help of a directed acyclic graph (DAG). So.
gates on the critical path can be realized using Low-Vth transistors for high
performance and the gates on the noncritical path are realized using high-Vth
transistors to reduce leakage power. This is the basic concept of dual Vt
assignment.
86 Infer how the threshold voltage can be dynamically adjusted to reduce K2
leakage power dissipation.
Just like dynamic the Vdd scaling scheme, a dynamic Vth scheme (DVTS) can
be used to reduce runtime leakage power in sub-100-nm generations, where
leakage power is significant portion of the total power at runtime. When the
workload is less than the maximum, the processor is operated at lower clock
frequency. Instead of reducing the supply voltage, the DVTS hardware raises
the threshold voltage using reverse body biasing to reduce runtime leakage
power. Just enough throughput is delivered for the current workload by

23
 dynamically adjusting the Vth in an optimal manner to maximize leakage power
reduction. A simpler scheme is called Vth-hopping which dynamically switches
between only two threshold voltages; Low-Vt and High-Vt as the frequency
controller generates either FCLK or FCLK/2, respectively.
87 How parameter variations impact on yield of present day VLSI circuits? K1
Fluctuations are attributed to the manufacturing process (e.g., drifts in Leff,
Tox, Vt, or Ncheff), which affect circuit yield. For example, with in die
variation in Leff can be as high as 50%. 30% delay variation and 20X leakage
variation between fast and slow dies have been reported for 0.18µ CMOS
process. Low leakage chips with too low frequency must be discarded and high
frequency chips with too high leakage must also be discarded. This results to
reduction in yield.
88 What is bubble pushing? K1
Here two bubbles are pushed in the input side. This is known as bubble pushing.
89 What is Domino Logic? K1
The dynamic static pair is known as domino gate. The monotonicity problem
can be solved by connecting a static CMOS inverter between the dynamic gates.
It is used to convert monotonically falling output into a monotonically rising
signal suitable for the next gate.
90 Define Pass transistors (or) Explain steering logic. What are the K2
Advantages of pass transistor logic? What is n MOS Pass transistor?
These are single MOSFET which passes the signal between the drain and
source terminals instead of a fixed power supply value.
Advantages:
i. These are not 'ratio' devices.
ii. They do not have a path from + supply to ground. So, they don't
dissipate standby power.

n-MOS pass transistor

91 Summarize Bubble pushing with neat diagram. K2

Using De-Morgan’s laws, a . b=a+ b .In the logical OR gate, 2 bubbles are
pushed in the input side. This concept is known as bubble pushing. It is shown
in figure.

24
92 How to overcome charge sharing? K1
By using Keeper circuit, charge sharing can be avoided

93 What is the need of MODL? K1

If one function is a sub function of another sub function, then, multiple output
domino logic (MODL) is needed. It saves area by combining all the functions
into a multiple output gate.
94 Compare the CMOS circuit families. K2
i. Static CMOS logic is best for CMOS circuits. It is fast.
ii. Pseudo-nMOS, dynamic NOR gates are suitable for implementing high
fan-in functions. Because logical effort is independent of the width. E.g.
PLA, ROM
iii. Domino logic is suitable for high speed applications.
PART B & PART C (13 & 15 Marks)
95 Explain about the ratioed circuit and dynamic circuit CMOS logic 13 K2
configurations.
96 Outline the basic principle of operation of dynamic CMOS, domino and 15 K2
NP domino Logic with neat diagrams.
97 Explain the static and dynamic power dissipation in CMOS circuits with 15 K2
necessary diagrams and expressions.
98 Interpret the design techniques to reduce switching activity in a static 13 K2
and dynamic CMOS circuits.
99 Classify the circuit families and compare them. 13 K2
100 Size the transistors of CMOS three input NAND gate for logic ratio of 13 K2
3/1.
101 Illustrate Y= (A+B)(C+D) using the standard CMOS logic. 15 K2
102 Illustrate a 2-bit non-inverting dynamic shift register using pass 15 K2
transistor logic.
103 Discuss in detail the characteristics of CMOS transmission gate 13 K2
104 Draw a CMOS logic, design the Boolean function Z=A(D+E)+BC 13 K1
105 Describe how dynamic voltage scaling can reduce dynamic power 13 K2
25
 dissipation.
106 Explain the following static CMOS logic. K2
(i) Bubble pushing. (4)
(ii) Compound gates. (4)
(iii) Skewed gates. (5)
107 Illustrate the following circuits in detail. K2
(i) Pseudo-nMOS, (8)
(ii) Ganged CMOS. (5)
108 (i) Write short notes on Cascode voltage switch logic. (8) K1
(ii) Describe the modes of operation in dynamic circuits. (5)
109 Draw the 2-input multiplexers using the following circuit K1
techniques.
(i) static CMOS. (3)
(ii) Pseudo-nMOS. (3)
(iii) CVSL. (3)
(iv) Dual-rail Domino. (4)
110 Illustrate the design of Differential Cascode Voltage Switch (13) K2
with Pass Gate (DCVSPG).
111 Describe in detail about the following. K1
(i) Keepers. (5)
(ii) Multiple-Output Domino Logic (MODL). (4)
(iii) NP and Zipper Domino. (4)

26
 UNIT III
SEQUENTIAL CIRCUIT DESIGN

PARTA

S.No. Questions and Answers Knowl

edge
Level
What is called static and dynamic sequencing element? K1
1 A sequencing element with static storage employs some sort of feedback to retain its
output value indefinitely. A sequencing element with dynamic storage generally
maintains its value as charge on a capacitor that will leak away if not refreshed for a
long period of time.
2 What is clock skew? K1
In reality clocks have some uncertainty in their arrival times that can cut into the time
available for useful computation is called clock skew.
3 What are the disadvantages of dynamic CMOS technology? K1
i. A fundamental difficulty with dynamic circuits is a loss of noise immunity
and a serious timing restriction on the inputs of the gate.
ii. Violate monotonicity during evaluation phase.
4 What are synchronizers? K1
A synchronizer is a circuit that accepts an arbitrarily changing input and produces
an output aligned to the synchronizer's clock. If the input changes during
synchronizer's aperture, the synchronizer has a non-zero probability of producing
metastable output. Synchronizers are used to reduce metastability. The synchronizers
ensure synchronization between asynchronous input and synchronous system.
5 Differentiate Melay and Moore state machines. K2
In the Melay state machine we can calculate the next state and output both from the
input and state. But in the Moore state machine we can calculate only next state but
not output from the input and the state and the output is issued according to next state.
6 Define propagation delay and contamination delay. K1
Propagation delay(tpd):
The amount of time needed for a change in a logic input to result in a permanent
change at an output, that is the combinational logic will not show any further output
changes in response to an input change alter time for units.
Contamination delay(tcd):
The amount of time needed for a change in a logic input to result in an initial change
at an output, that is the combinational logic is guaranteed not to show any output
change in response to an input change before fed time units have passed.
7 Define Setup time and Hold time. K1
Setup time (t setup):
The amount of time before the clock edge that data input D must be stable the rising
clock edge arrives.
Holdtime (t hold):
This indicates the amount of time after the clock edge arrives the data input D must
be held stable in order for FF to latch the correct value. Hold time is always measured
from the rising clock edge to a point after the clock edge.
8 Compare latches and Flip-Flop. K2
Latch Flip - Flop
A latch is level sensitive A Flip Flop is edge triggered

27
 A latch stores when the clock level is A Flip Flop stores when the clock
low and transparent when the level is rises and is mostly never
high. transparent.
9 Interpret the term Pipelining. K2
A pipeline is a set of data processing elements connected in series, so that the output
of one element is the input of the next one. In most of the cases we create a pipeline
by dividing a complex operation into simpler operations. Pipelining is a popular
design technique often used to accelerate the operation of the data path in digital
processors. The major advantages of pipelinig are to reduce glitching in complex
logic networks and getting lower energy due to operand isolation.
10 How the limitations of a ROM-based realization are overcome in a PLA-based K1
realization?
In a ROM, the encoder part is only programmable and use of ROMs to realize
Boolean functions is wasteful in many situations because there is no cross-connect for
a significant part. This wastage can be overcome by using Programmable Logic Array
(PLA), which requires much lesser chip area.
11 In what way the DRAMs differ from SRAMs? K2
Both SRAMs and DRAMs are volatile in nature, ie. Information is lost if power line
is removed. However SRAMs provide high switching speed, good noise margin but
require large chip area than DRAMs.
12 Explain the read and write operations for a one-transistor DRAM cell. K2
A significant improvement in the DRAM evolution was to realize 1-T DRAM cell.
One additional capacitor is explicitly fabricated for storage purpose. To store 'I', it is
charged to store '0' it is discharged to '0' volt. Read operation is destructive. Sense
amplifier is needed for reading. Read operation is followed by restoration operation.
13 What is MTBF? K1
T =T setup
T ie i
1 τi
MTB F= =
P (failure ) N T0
14 Outline Max delay constraint and Min delay constraint. K2
Min delay constraint:
The path begins with the rising edge of the clock triggering F1. The data may begin to
change at Q1 after a clk-to-Q contamination delay. However, it must not reach D2
until at least the hold after the clock edge, lest it corrupt the contents of F2. Hence, we
solve for minimum logic contamination delay :
tcd>= thold – tccq
Max delay constraint :
The path begins with the rising edge of the clock triggering F1. The data must
propagate to the output of the flipflop Q1 and through the combinational logic to D2,
setting up at F2 before the next rising clock edge. Under ideal conditions, the worst
case propagation delays determine the minimum clock period for this sequential
circuitry
Tc>= tpcq + tpd + tsetup

15 Classify the types of sequential circuits. K2

The sequential circuits are classified on the basis of timing of their signals into two
types. They are,
i. Synchronous sequential circuit.
ii. Asynchronous sequential circuit.
16 Define sequential circuit. K1
The circuits in which the output depends on the current inputs as well as previous
inputs are called sequential circuits. The output is fedback to the input and these
circuits are also known as regenerative circuits.
28
17 Compare combinational circuits and sequential circuits. K2
Combinational circuits Sequential circuits
The output depends on the current The output depends on the current
input values. input and previous output values.

Memory unit is not required Memory unity is required

Non-Regenerative circuits Regenerative circuits

Example: Parallel adder Example: Serial adder

18 Define synchronous sequential circuit. K1
In synchronous sequential circuits, signals can affect the memory elements only at
discrete instant of time.
19 Define Asynchronous sequential circuit. K1
In asynchronous sequential circuits change in input signals can affect memory
element at any instant of time.
20 Differentiate static and dynamic memory. K2
Dynamic Memory
Static Memory
The state is preserved as long as Stores state for a short period of time.
power is ON
The register is not updated for periods The capacitor should be refreshed
of time. periodically.
Used in multivibrators Used in data path circuits
21 Compare Synchronous & Asynchronous sequential circuits. K2
Asynchronous sequential circuits
Synchronous sequential circuits
Memory elements are locked Memory elements are either unlocked
flip-flops flip-flops or time delay elements.
22 What is called sequencing element? K1
Flip-flop or latches are memory elements that hold data called tokens. These memory
elements are called sequencing elements and are used to sequence data i.e. data
appear in a predetermined sequence in bits.
23 What is static sequencing element? K1
A sequencing element with static storage is called static sequencing element. It uses
feedback to retain its output indefinitely.
24 What is dynamic sequencing element? K1
A sequencing element with dynamic storage is called dynamic sequencing element. It
stores the values depending on the charge on a capacitor. The capacitor should be
refreshed in periodic interval.
25 What are the types of sequencing static circuits? K1
i. Flip-flops
ii. 2-phase transparent latches
iii. Pulsed latches
26 What is meant by pulsed latch? K1
The latch which has short clock-to-Q delay and a long hold time is called pulsed latch
or single-phase level triggered latch.
27 What is race around condition? K1
In the JK latch, the output is feedback to the input, and therefore changes in the
output results to change in the input. Due to this in the positive half of the clock pulse
if J and K are both high then output toggles continuously. This condition is known as
29
 race around condition.
28 What is clock jitter? K1
Clock jitter refers to the temporal variation of the clock period at a given point (i.e.)
the clock period can reduce or expand on a cycle by cycle basis.

29 Define sequencing overhead. K1

If the tokens arrive too early, then sequencing elements delay the tokens so that it will
not coincide with the previous tokens. This will further add delay to the critical tokens
and reduce the performance of the system. This extra delay is called sequencing
overhead.
30 What is Max-delay failure (or) setup time failure? How to overcome it? K1
If the combinational logic delay is too high, then the receiving element can miss its
setup time. So, it samples the wrong value. It is known as setup time failure (or) max-
delay failure. To overcome this failure, the logic can be redesigned or the clock
period can be increased.
31 What is two phase timing? K1
In two phase timing, the signal can belong to phase 1 or phase 2. In each phase, three
different clocks are there. These are stable, valid, qualified clock.
32 Define time borrowing or cycle stealing. K1
Certain paths take longer time if other paths take less time. The ability of slow logic
to use time nominally allocated in one half-cycle to faster logic in another half-cycle
is called time borrowing.
33 Define Word line and Bit line. K1
The horizontal select line which is used to select the single row of cell is known as
word line. The wire which connects the cell in a single column to the input/output
circuit is known as bit line.
34 What is Block address? K1
The memory is divided into various small blocks. The address which is used to select
one of the small blocks to be read or written is known as block address.
35 What is meant by keeper circuit? K1
If a dynamic node is precharged high and left floating, the voltage on the dynamic
node will drift over time due to sub threshold and junction leakage. Charge-keeper
circuit is used for retaining the charge till next precharge condition.
36 Abbreviate the terms: VTC, C2MOS, TSPCR. K1
VTC - Voltage Transfer Characteristic
C2MOS - Clocked CMOS
TSPCR - True Single Phase Clocked Register.
37 Write the advantages and disadvantage of TSPCR. K1
Advantages:
Single clock phase is used.
Logic functions can be embedded into the latch.
Disadvantage:
Number of transistors is increased.
38 Write advantages of C2MOS Dual Edge Triggered Register. K1
It means input is sampled on both edges (Rising edge and falling edge).
Advantages
Power is saved in clock distribution network.
30
 Frequency clock is low.
39 Compare latches and registers. K2

Registers
Latches
Latches are level sensitive and the Registers on the other hand are edge
input is transferred to the output triggered i.e. they transfer input to the
during the clock transition. output at clock's edges.

Positive latches let the input to A register of a master-slave topology

propagate to the output as long as the is created by placing a negative latch
clock( enable) is high and hold their after a positive latch.
previous state when clock is low (and
vice versa for negative latches).

The latches are divided into Positive The registers are classified as Positive
latch and Negative latch edge triggered and Negative edge
triggered
40 Contrast Latches and Flipflop. K2
Flipflop
Latches
A latch is level-sensitive A flip-flop is edge triggered

Stores when the clock level is low Stores when the clock rises and is
and is transparent when the level is mostly never transparent. Since flip-
high flops only change value in response
to a change in the clock value, timing
parameters can be specified in
relation to the rising (for positive
edge-triggered) or falling (for
negative-edge triggered) clock edge.
41 Explain ROM. K2
A read only memory (ROM) is a device that includes both the decoder and the OR
gates within a single IC package. It consists of n input lines and m output lines. Each
bit combination of the input variables is called as an address. Each bit combination
that comes out of the output lines is called as a word. The number of distinct
addresses possible with n input variables is 2n.
42 What are the types of ROM? K1
i. PROM
ii. EPROM
iii. EEPROM
43 Explain PROM. K2
PROM (Programmable Read Only Memory) allows user to store data or program.
PROMs use the fuses with material like nichrome and polycrystalline. The user can
blow these fuses by passing around 20 to 50mA of current for the period 5 to 20s.The
blowing of fuses is called programming of ROM. The PROMs are one time
programmable. Once programmed, the information is stored permanently.
44 Explain EPROM. K2
EPROM (Erasable Programmable Read Only Memory) use MOS circuitry. They
store 1's and 0's as a packet of charge in a buried layer of the IC chip. We can erase
the stored data in the EPROMs by exposing the chip to ultraviolet light via its quartz
window for 15 to 20 minutes. It is not possible to erase selective information. The
chip can be reprogrammed.
31
45 Explain EEPROM. K2
EEPROM (Electrically Erasable Programmable Read Only Memory) also use MOS
circuitry. Data is stored as charge or no charge on an insulated layer or an insulated
floating gate in the device. EPROM allows selective erasing at the register level
rather than erasing all the information since the information can be changed by using
electrical signals.
46 What is FLASH memory? K1
FLASH is Electrically Erasable Programmable ROM. It is a combination of density
of EPROM and versatility of EEPROM.
47 Define address and word. K1
In a ROM, each bit combination of the input variable is called as address. Each bit
combination that comes out of the output lines is called a word.
48 What is programmable logic array? How it differs from ROM? K1
In some cases the number of don't care conditions is excessive, it is more economical
to use a second type of LSI component called a PLA. A PLA is similar to a ROM in
concept; however it does not provide full decoding of the variables and does not
generates all the min terms as in the ROM.
49 How the limitations of a ROM-based realization is overcome in a PLA-based K1
realization?
In a ROM, the encoder part is only programmable and use of ROMs to realize
Boolean functions is wasteful in many situations because there is no cross-connect for
a significant part. This wastage can be overcome by using Programmable Logic array
(PLA), which requires much lesser chip area.
50 Define RAM. K1
RAM is Random Access Memory. It is a random access read/write memory. The data
can be read or written into or from any selected address in any sequence.
51 Define Static RAM and dynamic RAM. K1
Static RAM uses flip flops as storage elements and therefore store data indefinitely as
long as dc power is applied. Dynamic RAMs use capacitors as storage elements and
cannot retain data for a long time without capacitors being recharged by a process
called refreshing.
52 List the two types of SRAM. K1
i. Asynchronous SRAMs
ii. Synchronous Burst SRAMs
53 List the basic types of DRAMs. K1
i. Fast Page Mode DRAM
ii. Extended Data Out DRAM (EDC DRAM)
iii. Burst EDO DRAM
iv. Synchronous DRAM
54 Explain the read and write operations for a one transistor DRAM cell. K2
A significant improvement in the DRAM evolution was to realize 1-T DRAM cell.
One additional capacitor is explicitly fabricated for storage purpose. To store ‘1’, it is
charged to Vdd-Vt and to store ‘0’, it is discharged to 0V. Read operation is
destructive. Sense amplifier is needed for reading. Read operation is followed by
restoration operation.
55 Define a bus. K1
A bus is a set of conductive paths that serve to interconnect two or more functional
components of a system or several diverse systems.
56 What are the Properties of 3T dynamic memory? K1
i. There is no constraint on device ratio. Device reliability depends on the device
size.
ii. Reading the cell is nondestructive. Data stored in cell is not affected by a read.
iii. Storage capacitance is not more than the gate capacitance of the readout
32
 device.
iv. The threshold loss reduces the current flowing through M2 during read
operation. So read access time is increased. Some bootstrap is needed to avoid
this.
57 Sketch the schematic diagram of a SRAM memory cell along with sense K1
amplifier and data write circuitry.

58 Outline the design procedures in a logic circuit. K2

i. State the problem.
ii. Determine the number of available input variables and required output
variables.
iii. Assign letter symbols for input and output variables.
iv. Derive the truth table defining the required relationships between inputs and
outputs.
v. Obtain the simplified Boolean function for each output.
vi. Draw the logic diagram.
59 Draw the circuit diagram of 6-transistor SRAM cell. K1

33
60 Draw the circuit diagram of 3-transistor DRAM cell. K1

61 Write the characteristic of 1T cells. K1

i. 1T cell consists of one transistor
ii. 1T DRAM needs the presence of sense amplifier for each bit line. Sense
amplifier is needed to speed up the readout process. DRAM cells are single
ended.
iii. The amount of charge stored in the cell is modified during read operation.
After reading, the original value must be restored.
iv. 1T cell needs the extra capacitance which is added in the design.
v. If logic 1 is to be written then the threshold voltage is lost. So, the charge is
reduced.
62 Draw the architecture of memory organization. K1

34
63 Draw the circuit diagram of 1-transistor DRAM cell. K1

64 What are the advantages of memory division approach? K1

i. Access time is fast.
ii. Power saving is good, because the blocks which are not activated by the block
address will be in power saving mode.
65 Draw the circuit diagram of NAND- based ROM. K1

66 What is floating gate transistor? K1

It is mostly used in all the reprogrammable memories. In floating gate transistor, extra
polysilicon strip is there between the gate and the channel. It is known as floating
gate. It is used to double the gate oxide thickness. So device transconductance is
reduced and threshold voltage is increased.
67 What is FAMOS? What are its advantages and disadvantages? K1
The floating gate transistor is known as floating gate avalanche injection MOS or
FAMOS.
Advantages
i. Simple
ii. Large memories are fabricated with low cost.
Disadvantages
i. Number of erase/program cycle is limited to maximum of 1000.
35
 ii. Reliability is not good.
iii. Threshold voltage of the device may be varied with repeated program.
68 What is arbiter? K1
An arbiter is a circuit for determining which of several signals arrive first. Arbiters
are used in asynchronous circuits to order the computational activities for shared
resources to prevent concurrent incorrect operations.
69 What is metastability? K1
Flip-flop is a device susceptible to metastable state. If the flip-flop switches between
two states 0 and 1 for more than a clock cycle, then this condition is known as
metastability.
70 What is resettable latch? K1
The control input called reset signal is applied to resettable latch so that initial state is
entered on startup.
71 What are the types of reset? K1
The two types of reset are
i. Synchronous Reset
ii. Asynchronous Reset
72 What is meant by synchronous and asynchronous design? K1
Synchronous design:
A synchronous signal is one that has the exact same frequency, and a known fixed
phase offset with respect to the local clock. The signal is synchronized with the clock,
and the data can be sampled directly without any uncertainty. In digital logic design,
synchronous systems are the most straight forward type of interconnect, where the
flow of data in a circuit proceeds in lockstep with the system clock.
Asynchronous design:
Asynchronous circuits are an inherently larger class of circuits, since there are many
sequencing options other than global periodic clock signals.
PART B & PART C (13 & 15 Marks)
73 Write a brief note on sequencing dynamic circuits. 13 K1
74 Explain in detail about the principle concepts used in sequential circuits. 13 K2
75 How do you achieve low power in memory circuits? Explain in detail. 13 K1
76 Discuss in detail about dynamic RAM. 13 K1
77 Illustrate the principles of synchronizer and arbiter. 13 K2
78 Discuss in detail about various Pipelining techniques and explain in detail. 13 K2
79 Draw and explain the operation of conventional CMOS, Pulsed and resettable 15 K2
latches
80 Compare the sequencing in traditional domino and skew tolerant domino 15 K2
circuits with neat diagrams
81 Explain the problem of metastability with neat diagrams and expressions 13 K2
82 State Bistability principle and explain in detail about the two different 13 K1
approaches used in this.
83 Discuss in detail about K2
(i) Master-Slave Edge-Triggered Register. 8
(ii) Timing properties of Multiplexer-Based Master-Slave registers. 7
84 Write short notes on: K1
(i) Multiplexer-Based Latches. 7
(ii) Low-Voltage Static Latches. 6
85 Explain the working of C2MOS Register with CLK-CLK clocking approach. 15 K2
86 Draw and explain about True Single-Phase Clocked Register (TSPCR) and 13 K2
TSPC Edge-Triggered register.
87 Illustrate the following Alternative Register styles. K2
(i) Pulse Registers. 7
(ii) Sense-Amplifier-Based Registers. 6
36
88 Explain the concept of clock-distribution techniques dealing with clock skew 15 K2
and jitter.
89 Illustrate the following. K2
(i) Latch versus Register based pipeline. 6
(ii) NORA-CMOS logic style for pipelined structures. 7
90 (i) Write about Schmitt trigger and its properties. K1
4
(ii) Describe Schmitt trigger and its CMOS implementation with neat diagram. 9
91 Illustrate about Monostable Sequential circuits and Astable circuits with 13 K2
example.

37
 UNITIV

DESIGN OF ARITHMETIC BUILDING BLOCKS AND SUBSYSTEM

PARTA
S.No. Questions and Answers Knowledge
Level
How path can be implemented in VLSI system? K1
1 A data path is best implemented in a bit –sliced fashion. A single layout is used
respectively for every bit in the data word. This regular approach eases the
design effort and results in fast and dense layouts.

2 Interpret the performance of ripple carry adder. K2

A ripple carry adder has a performance that is linearly proportional to the
number of bits. Circuit optimizations concentrate on reducing the delay of the
carry path. A number of circuit topologies exist providing that careful
optimization of the circuit topology and the transistor sizes helps to reduce the
capacitance on the carry bit.
3 What is the logic of adder for increasing its performance? K1
Other adder structures use logic optimizations to increase the performance
(carry bypass, carry select, carry lookahead). Performance increase comes at the
cost area.
4 What is multiplier circuit? K1
A multiplier is nothing more than a collection of cascaded adders. Critical path
is far more complex and optimizations are different compared to adders.

5 Which factors dominate the performance of programmable shifter? K1

The performance and the area of a programmable shifter are dominated by
the wiring
6 What is meant by data path? K1
The data path is the core of the processor in which all computations are
performed. A typical data path consists of an interconnection of the basic
combinational functions such as arithmetic operators (addition, multiplication,
comparison and shift) or logic (AND, OR and XOR). A datapath is a functional
unit, such as arithmetic logic units or multipliers that perform data processing
operations, registers and buses. Along with the control unit it composes the
central processing unit.
7 Write down the expression for worst-case delay for RCA. K1
t = (n-1)tc+ts

8 Write down the expression to obtain delay for N-bit carry bypass adder. K1
tadder = tsetup +Mtcarry +(N/M-1)tbypass +(M-1)tcarry + tsum
9 Define Braun multiplier. K1
The simplest multiplier is the Braun multiplier. All the partial products are
computed in parallel, and then collected through a cascade of Carry Save
Adders. The completion time is limited by the depth of the carry save array, and
by the carry propagation in the adder. This multiplier is suitable for positive
operands.
10 Why do we go for Booth’s algorithm? K1
Booth algorithm is a method that will reduce the number of multiplicand
multiples. For a given number of ranges to be represented, a higher
representation radix leads to fewer digits.

38
11 List the different types of shifter. K1
Shifters are used to shift the numbers from one bit position to other. The various
types of shifters are as follows:
i. Array shifter
ii. Barrel shifter
iii. Logarithm shifter
12 Draw the truth table for Modified booth’s algorithm. K1
X2n+1 X2n X2n-1 f(2n) f(2n)Y
0 0 0 0 0
0 0 1 1 Y
0 1 0 1 Y
0 1 1 2 2Y
1 0 0 -2 -2Y
1 0 1 -1 -Y
1 1 0 -1 -Y
1 1 1 0 0
13 Draw the block diagram of full adder. K1

14 What are the two major types of carry lookahead adders? K1

i. Monolithic lookahead adders
ii. Logarithmic lookahead adders
15 What is clock-delayed domino? K1
During the precharge phase, a short-circuit current exists in all gates -without a
foot switch until their inputs get precharged. To avoid the short circuit current,
the clock at each stage Clkk is delayed from the previous stage. This approach
is called clock-delayed domino.
16 What are the drawbacks of static adder circuits? K1
i. Consumes large area
ii. Slow in operation
iii. Tall PMOS transistor stacks are present in both carry and sum
generation circuits.
17 Outline the multiplication operation using two-input adders. K2
For inputs that are M and N bits wide, the multiplication takes M cycles, using
an N-bit adder. This shift-and-add algorithm for multiplication adds together M
partial products. Each partial product is generated by multiplying the
multiplicand with a bit of the multiplier-which is an AND operation - and by
shifting the result on the basis of the multiplier bit's position.
18 What are the basic building blocks of a 4-bit divider? K1
i. Adder (ADD4) to add two 4-bit binary number
ii. 4-bit binary up counter (CB4CE)
iii. 4 set 2:1 MUX and D flip-flops.
19 Summarize the properties of barrel shifter. K2
i. Number of rows = Number of data word length
ii. Control wire routed diagonally
iii. Signal goes through only one transmission gate (theoretically delay is
constant for shift value and shifter size)
39
 iv. Reality - delay depends on shift widths due to parasitic capacitance
v. Layout and area dominated by wiring and not active elements
vi. Need decoder to interpret shift data to route signal to appropriate wire
20 What is equality detector? K1
It is a circuit which is used to compare 2 numbers of n-bit words. If inputs are
equal, then outputs =1, otherwise, output =0.
21 What is priority encoder? K1
The circuit which is used to examine the input bits and produces an output
which indicates the position of the highest priority logic 1 bit is known as
priority encoder.
22 In shift register, how the rotation is specified? K1
In shift register, n-bit rotation is specified by using the control word Ro, and
L/R bit defines a left or right shifting.
23 Summarize the steps for computation in Wallace tree algorithm. K2
The Wallace tree has 3 steps.
i. Multiply each bit of one of the arguments by each bit of the other
yielding n 2 results.
ii. Reduce the number of partial products to two using layers of full and
half adders.
iii. Group the wires in two numbers and add them with a conventional adder
23 What are the advantages and disadvantages of Wallace tree multiplier? K1
Advantages
i. Substantial Hardware Savings
ii. Higher Speeds
Disadvantages
i. Propagation delay 0(log31 2N)
ii. Irregular; inefficient for layout
24 How do you calculate critical path of array multiplier? K1
t mult =[ ( M −1 ) + ( N−2 ) ] t carry + ( N −1 ) t ∑ ¿+ t ¿
¿

25 How can power consumption of a circuit be reduced? K1

Power consumption can be reduced by the proper choice of circuit, logical or
architectural structure. This might come at the expense of area, but area might
not be critical in the submicron devices.
26 How do you determine the circuit size? K1
Circuit size is determined by the number and size of the transistors, and also by
other factors such as wiring and the number of vias and contacts. These factors
become even more important with shrinking dimensions or when extreme
performance is a goal.
27 Define ripple carry adder. K1
The carry bit of first adder is connected as input to the second one and is
continued till Nth adder.

An N-bit adder can be constructed by cascading N full-adder (FA) circuits in

series, connecting Co,k-1 to Ci,k for k=1 to N-1, and the first carry-in Ci,o to 0.
40
 This configuration is called a ripple-carry adder, since the carry bit "ripples"
from one stage to the other.
28. What is Manchester carry chain adder? K1
The Manchester carry chain is a variation of the carry-lookahead adder that uses
shared logic to lower the transistor count. The logic for generating each carry
contains all of the logic used to generate the previous carries. A Manchester
carry chain generates the intermediate carries by tapping off nodes in the gate
that calculates the most significant carry value.
29 Draw the diagram of Manchester cell for adder. K1

30 Draw the transistor level implementation of 4-bit carry generation. K1

31 List the advantages and disadvantages of dual rail domino adder. K1

Advantages:
i. Very fast
ii. Used in fast multipliers
Disadvantages:
i. Occupies larger area
ii. More power consumption
32 What is Kogge-Stone adder? K1
The Kogge-Stone adder is a parallel prefix form carry look-ahead adder. The
Kogge-Stone adder takes more area to implement, but has a lower fan-out at
each stage, which increases performance for typical CMOS process nodes.
However, wiring congestion is often a problem for KoggeStone adders.
33 What are the advantages of CPL adder? K1
i. The complementary Pass- Transistor Logic (CPL) can also be used to
implement full adder.
ii. CPL is twice as fast as 40- transistor static CMOS full adder.
41
 iii. 30% low power and slightly smaller.
34 What is carry lookahead adder? K1
A carry-lookahead adder (CLA) or fast adder is a type of adder used in digital
logic. A carry-lookahead adder improves speed by reducing the amount of time
required to determine carry bits. It is used to overcome the latency which is
introduced by the rippling effect of carry bits.
35 What are the types of dividers? K1
i. Serial Divider
ii. Parallel Divider
36 Name a few high performance adders. K1
i. Carry-bypass adder
ii. Carry select adders
iii. Carry increment adder
iv. Carry lookahead adder
v. Variable length increment adder
37 How subtraction is performed? K1
A subtractor can be implemented using adder; a subtractor is performed using
2's complement addition.
A-B = A + (2's Complement of B)
= A + ( B + 1)
38 Draw the circuit diagram of 1-bit CMOS Full adder. K1

39 What is meant by accumulator? K1

Accumulator basically consists of register and adder. Register hold the output of
previous clock from adder. Holding outputs in accumulation register can reduce
additional add instruction.
40 Write the steps required in designing 4-bit accumulator. K1
The steps required for designing a 4-bit accumulator is as follows.
i. Design a 1-bit edge triggered DFF.
ii. Cascade four 1-bit full-adders to form a 4-bit ripple adder.
iii. Use the 4-bit ripple adder and register to design and 4-bit accumulator.
41 Draw the circuit diagram of transmission gate Full adder. K1

42
42 Define dot diagram. K1
Each dot represents a placeholder for single bit either 0 or 1. Partial products
are represented by a horizontal boxed row of dots, shifted depending on their
weight.

43 What is Booth's recoding? K1

It is a classical method which cuts down the number of partial products in an
addition tree by a factor of 2 or 3 at the expense of a more complex generation
of partial products. Booth recoding improves both the cost and the speed of
multipliers by a constant factor of 1/4.
44 What are the advantages of Booth’s multiplication? K1
i. The number of partial products is reduced to half and hence for the
number of additions is also reduced.
ii. For every consecutive bit, atmost one bit will be 1 or —1.
iii. For a given range of numbers to be represented, a higher representation
radix leads to fewer digits.
43
 iv. The speed is increased and it also leads to reduction in area.
45 Draw the bit sliced datapath organization. K1

46 Define logical shifter. K1

Logical shifter is used to shift the number to the left or right and empty spots
are filled with 0's.
47 What is funnel shifter? K1
A funnel shifter can perform all three shifting operation — Logical, arithmetic
and barrel shifting. The funnel shifter can support all types of shifts and rotates
by choosing suitable inputs Z.
48 Define barrel shifter. K1
Barrel shifter rotates the numbers in a circle such that empty spots are filled
with bits shifted at other end.
Example:

49 Draw the four bit carry select adder topology. K1

50 Give the expression for the propagation time of a carry bypass adder. K1

[( ) ]
t p=t setup + Mt carry +
N
M
−1 t bypass + [ M −1 ] t carry +t ∑ ¿ ¿

Where,
t setup :The fixed overhead time to create the generate and propagate signals.
44
 t carry :The propagation delay through a single bit. The worst-case carry-
propagation delay through a single stage of M bits is approximately M times
larger.
t bypass : The propagation delay through the bypass multiplexer of a single stage
t ∑ ¿ :¿ The time to generate the sum of the final stage.

51 What are the disadvantages of standard cell design? K1

i. Regular layout has delay for each bit.
ii. Interconnect should be built into each cell.
52 Outline the steps involved in divider. K2
i. Each bit of divisor is complemented and then given as input to the adder
ii. Dividend is initially loaded in a register with 4 D flip-flops if LOAD =
which is common select input of all the MUX and to CLR input of
counter.
iii. The counter is reset to zero.
iv. The output of D flip-flops is fed to another set of inputs of adder.
v. The final carry output of the adder block is fed to the clock enable input
(CE) of the counter and to OR gate.
53 Write the metrics required in design of VLSI chip. K1
Area: size of the die, which relates to cost and profit
Speed /delay: how fast the transistors can switch
Power: how much energy it takes to do the work
54 What are the types of power in calculating power matrix? K1
The standard power is measured which affects the performance. There are two
types of power.
i. Static power- DC current that does not depends on signal activity.
ii. Dynamic- AC current proportional to signal transitions.
PART B & PART C (13 & 15 Marks)
55 Explain the structure of booth multiplier and list its advantages. 13 K2
56 Construct a 3 bit barrel shifter 15 K2
57 What is 4*4 carry save multiplier. Calculate its critical path delay 13 K2
58 Explain with neat diagram Baugh-Wooley multiplier 13 K2
59 Explain ripple carry adder. 13 K2
60 Describe about carry look-ahead adder and its carry generation and 13 K1
propagation.
61 Draw the circuit diagram and stick diagram of a 4*4 barrel shifter and 13 K2
explain its operation
62 Explain the structure of a booth multiplier and list its advantages. 13 K2
63 Give the general arrangement of a 4-bit arithmetic processor and design 15 K3
a 4-bit adder unit for ALU sub system
64 Describe the working of ripple carry adder and derive the expression for 13 K1
worst case delay.
65 Discuss the operation of SRAM memory cell and give a short K1
note on
(i) Read operation. 7
(ii) Write operation. 6
66 Explain the working of bitline conditioning circuitry with necessary 13 K1
circuit diagram.
67 Build a multiplier for 5 bit by 3 bit. Explain its operation and summarize 15 K3
the number of adders. Discuss it over Wallace multiplier.
68 Draw and explain the architecture of large memory array with subarray 13 K2
memory circuitry.

45
69 Discuss in detail about linear carry select adder with neat diagram. 13 K1
70 Develop the operation of booth multiplication with suitable example. 15 K3
Justify how booth algorithms speed up the multiplication process.
71 Construct 4 X 4 array type multiplier and find its critical path delay. 13 K3
72 Explain about the DRAM sub array and open bitlines architecture. 13 K2

46
 UNIT V

IMPLEMENTATION STRATEGIES AND TESTING

PARTA

S.No. Questions and Answers Knowledge

Level
1 What are the different levels of design abstraction at physical design? K1
i. Architectural or functional unit
ii. Register Transfer-level (RTL)
iii. Logic level
iv. Circuit level
2 What are programmable Interconnects? K1
In a PAL, the device is programmed by changing the characteristics if the
switching element. An alternative would be to program the routing.
3 Differentiate channeled and channel less gate array. K2
Channeled gate array Channel less gate array
Only the interconnect is customized Only the top few mask layers are
customized
The interconnect uses predefined No predefined areas are set aside for
spaces between rows of base cells routing between cells.
Routing is done using spaces Routing is done using the area of
transistors unused
Logic density is less Logic density is higher
4 What are macros? K1
Gate array library is provided by ASIC Company. The designer can choose the
predesigned logic cells from a Gate Array Library. These logic cells are known
as Macros. The logic cells in a gate-array library are often called macros.
5 Outline the different types of ASIC. K2
i. Full custom ASICs
ii. Semicustom ASICs
a) Standard cell based ASICs
b) Gate-array based ASICs
iii. Programmable ASICs
a) Programmable Logic Device (PLD)
b) Field Programmable Gate Array (FPGA).
6 Classify the types of programmable devices. K2
Types of programmable devices are
i. Programmable logic structure
ii. Programmable Interconnect
iii. Reprogrammable Gate Array
7 What are the features of standard celled ASICs? K1
i. All mask layers are customized-transistors and interconnect.
ii. Custom blocks can be embedded
Manufacturing lead time is about eight weeks.
8 Summarize the characteristics of FPGA. K2
i. None of the mask layers are customized
ii. A method of programming the basic logic cells and the interconnect.
iii. The core is a array of programmable basic logic cells that can implement
combinational as well as sequential logic (flipflops).
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 iv. A matrix of programmable interconnect surrounds the basic logic cells.
v. Design turnaround is a few hours.
9 What is programmable logic array? K1
A programmable logic array (PLA) is a programmable device used to
implement combinational logic circuits. The PLA has a set of programmable
AND planes, which link to a programmable OR planes, which can then be
conditionally complemented to produce an output. This layout allows for a large
number of logic functions to be synthesized in the sum of products (sometimes
product of sums) canonical forms.
10 What is meant by programmable logic plane? K1
The programmable logic plane is programmable read only memory (PROM)
array that allows the signals present on the devices pins to be routed to an
output logic macro cell.
11 What is the full custom ASIC design? K1
In a Full custom ASIC, an engineer designs some or all of the logic cells,
circuits or layout specifically for one ASIC. It makes sense to take this approach
only if there are no suitable existing cell libraries available that can be used for
the entire design.
12 What is standard cell-based ASIC design? K1
A cell-based ASIC (CBIC) uses predefined logic cells known as STANDARD
CELLS. The standard cell areas are also called flexible block in a CBIC are
built of rows of standard cells. The ASIC designer defines only the placement
of standard cells and the interconnect in a CBIC. All the mask layers of a CBIC
are customized and are unique to a particular customer.
13 Interpret the term FPGA. K2
A Field Programmable Gate Array (FPGA) is a programmable logic device that
supports implementation of relatively large logic circuits. FPGA can be used to
implement a logic circuit with more than 20,000 gates whereas a CPLD can
implement circuits of upto about 20,000 equivalent gates.
14 What are the different methods of programming of PALs? K1
The programming of PALs in done in three ways:
i. Fusible links
ii. UV-erasable EPROM
iii. EEPROM(E2PROM) – Electrically Erasable Programmable
ROM.
15 What is an antifuse? K1
An antifuse is normally high resistance (>100MΩ). on application of
appropriate programming voltages, the antifuse is changed permanently to a
low-resistance structure(200-500Ω).
16 Outline the steps in ASIC design flow. K2
i. Design entry
ii. Logic synthesis system partitioning
iii. Prelayout simulation
iv. Floor planning
v. Placement
vi. Routing
vii. Extraction
viii. Post layout simulation
17 Why CMOS technology is most useful for analog functions? K1
The first reason is that CMOS is now by far the most widely available IC
technology. Most CMOS Asics and CMOS standard products are now being
manufactured than bipolar ICs.
The second reason is that increased levels of integration require mixing analog
and digital functions on the same IC: this has forced designers to find ways to
48
 use CMOS technology to implement analog functions.
18 Compare ASIC and FPGA. K2
ASIC FPGA
i. An ASIC is a unique type of An FPGA is a reprogrammable integrated
integrated circuit meant for a circuit.
specific application
ii. An ASIC can no longer be FPGA is alterable
altered once created
iii. An ASIC wastes very little FPGA is not efficient in terms of use of
material, recurring costs are materials. A certain number of components
low. are always wasted.
iv. Cost of ASIC is low only FGPA is better than an ASIC when
when it is produced in large building low volume production circuits.
quantity. ASICs are tested on FPGA before
v. ASICs can't be used to test implementing.
FPGAs. FPGAs are useful for research and
vi. ASICs are not suitable for development activities. Prototype
research and development fabrication using FPGA is affordable and
purposes, as they are not fast.
reconfigurable.

19 What are the characteristics of the FPGA? K1

i. None of the mask layers are customized.
ii. A method for programming the basic logic cells and the interconnect.
iii. The core is a regular array of programmable basic logic cells that can
implement combinational as well as sequential logic (flip-flops).
iv. A matrix of programmable interconnect surrounds the basic logic cells.
v. Programmable I/O cells surround the core.
vi. Design turnaround is a few hours.
20 What are the different levels of design abstraction at physical design? K1
i. Architectural or functional level
ii. Register Transfer-level (RTL)
iii. Logic level
iv. Circuit level
21 Give the general structure of FPGA. K1

22 Write a short note on detailed routing. K1

The global routing step determines the channels to be used for each
interconnect. Using this information the detailed router decides the exact
location and layers for each interconnect.

49
23 Write the goals of global routing. K1
The goal of global routing is to provide complete instructions to the detailed
router on where to route every net.
24 What type of interconnect scheme is used in ACTEL family? K1
The ACTEL FPGAs are based on an element called PLICE - Programmable
Low Impedance Circuit Element or antifuse. ACTEL deploys poly-diffusion
antifuse for interconnect. When high current density is applied, the thin
insulating dielectric between polysilicon and diffusion electrodes melts and
forms a thin, permanent and resistive silicon link.
25 Differentiate EPROM and EEPROM. K2
EPROM
EPROM is read and written electrically; before a write operation, all the storage
cells must be erased to the same initial state by exposure of the packaged chip
to ultraviolet radiation. Erasure is performed by shining an intense ultraviolet
light through a window that is designed into the memory chip.
EEPROM
EEPROM is a read- mostly memory that can be written into at any time without
erasing prior contents; only the byte or bytes addressed are updated.
26 What are the different types of CMOS testing? K1
i. Functionality tests
ii. Manufacturing tests
27 What is the aim of adhoc test techniques? K1
The adhoc test techniques are aimed at reducing the combinational explosion of
testing.
28 Compare functionality test and manufacturing test. K2
Functionality tests seek to verify that a chip as a whole is functionally
equivalent to some specification, whereas manufacturing tests are used to verify
that every gate operates as expected.
29 List any two faults that occur during manufacturing. K1
i. Stuck at fault
a) Stuck at 0 fault
b) Stuck at 1 fault
ii. SC & OC faults
a) Short circuit model fault
b) Open circuit model fault
30 What is the need for testing? K1
IC fabrication is very complex process. SO, there may be any imperfection
occur in any one of the stage. This imperfection may affect the result. So testing
is necessary to find out which IC is good and which IC is bad.
31 Write a note on functionality tests. K1
Functionality tests verify that the chip performs its intended function. These
tests assert that all the gates in the chip, acting in concert, achieve a desired
function. These tests are usually used early in the design cycle to verify the
functionality of the circuit.
32 Write a note on manufacturing tests. K1
Manufacturing tests verify that every gate and register in the chip functions
correctly. These tests are used after the chip is manufactured to verify that the
silicon is intact.
33 Mention the defects that occur in a chip. K1
i. layer-to-layer shorts
ii. discontinous wires
iii. thin-oxide shorts to substrate or well
34 Give some circuit remedies to overcome the defects. K1
i. nodes shorted to power or ground
50
 ii. nodes shorted to each other
iii. inputs floating/outputs disconnected
35 What are the tests for I/O integrity? K1
i. I/O level test
ii. Speed test
iii. IDDQ test
36 What is meant by fault model? K1
Fault model is a model for how faults occur and their impact on circuits.
37 Give some examples of fault models. K1
i. Stuck-At Faults
ii. Short-Circuit and Open-Circuit Faults
38 Interpret the levels at which testing of a chip can be done. K2
i. At the wafer level
ii. At the packaged chip level
iii. At the board level
iv. At the system level
v. In the field
39 What is stuck – at fault? K1
With this model, a faulty gate input is modeled as a “stuck at zero” or “stuck at
one”. These faults most frequently occur due to thin-oxide shorts or metal-to-
metal shorts.
40 What do you infer by the term observability? K2
The observability of a particular internal circuit node is the degree to which one
can observe that node at the outputs of an integrated circuit.
41 What is meant by controllability? K1
The controllability of an internal circuit node within a chip is a measure of the
ease of setting the node to a 1 or 0 state.
42 What is known as percentage-fault coverage? K1
The total number of nodes that, when set to 1 or 0, do result in the detection of
the fault, divided by the total number of nodes in the circuit, is called the
percentage-fault coverage.
43 What is fault grading? K1
Fault grading consists of two steps. First, the node to be faulted is selected. A
simulation is run with no faults inserted, and the results of this simulation are
saved. Each node or line to be faulted is set to 0 and then 1 and the test vector
set is applied. If and when a discrepancy is detected between the faulted circuit
response and the good circuit response, the fault is said to be detected and the
simulation is stopped.
44 Mention the ideas to increase the speed of fault simulation. K1
i. parallel simulation
ii. concurrent simulation
45 What is fault sampling? K1
An approach to fault analysis is known as fault sampling. This is used in
circuits where it is impossible to fault every node in the circuit. Nodes are
randomly selected and faulted. The resulting fault detection rate may be
statistically inferred from the number of faults that are detected in the fault set
and the size of the set. The randomly selected faults are unbiased. It will
determine whether the fault coverage exceeds a desired level.
46 What are the approaches in design for testability? K1
i. ad hoc testing
ii. scan-based approaches
iii. self-test and built-in testing
47 Mention the common techniques involved in ad hoc testing. K1
i. partitioning large sequential circuits
ii. adding test points
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 iii. adding multiplexers
iv. providing for easy state reset
48 Outline the scan-based test techniques. K2
i. Level sensitive scan design
ii. Serial scan
iii. Partial serial scan
iv. Parallel scan
49 Interpret the two principles in LSSD. K2
i. The circuit is level-sensitive.
ii. Each register may be converted to a serial shift register.
50 What are the self-test techniques? K1
i. Signature analysis and BILBO
ii. Memory self-test
iii. Iterative logic array testing
51 What is known as BILBO? K1
Signature analysis can be merged with the scan technique to create a structure
known as BILBO- for Built In Logic Block Observation.
52 What is known as IDDQ testing? K1
A popular method of testing for bridging faults is called IDDQ or current-
supply monitoring. This relies on the fact that when a complementary CMOS
logic gate is not switching, it draws no DC current. When a bridging fault
occurs, for some combination of input conditions a measurable DC IDD will
flow.
53 What are the applications of chip level test techniques? K1
i. Regular logic arrays
ii. Memories
iii. Random logic
54 What is boundary scan? K1
The increasing complexity of boards and the movement to technologies like
multichip modules and surface-mount technologies resulted in system designers
agreeing on a unified scan-based methodology for testing chips at the board.
This is called boundary scan.
What is the test access port? K1
The Test Access Port (TAP) is a definition of the interface that needs to be
included in an IC to make it capable of being included in a boundary-scan
architecture. The port has four or five single bit connections, as follows:
i. TCK(The Test Clock Input)
ii. TMS(The Test Mode Select)
iii. TDI(The Test Data Input)
iv. TDO(The Test Data Output)
It also has an optional signal
i. TRST*(The Test Reset Signal)
55 What are the contents of the test architecture? K1
The test architecture consists of:
i. The TAP interface pins
ii. A set of test-data registers
iii. An instruction register
iv. A TAP controller
56 What is the TAP controller? K1
The TAP controller is a 16-state FSM that proceeds from state to state based on
the TCK and TMS signals. It provides signals that control the test data registers,
and the instruction register. These include serial-shift clocks and update clocks.
57 What is known as test data register? K1
The test-data registers are used to set the inputs of modules to be tested, and to
collect the results of running tests.
52
58 What is known as boundary scan register? K1
The boundary scan register is a special case of a data register. It allows circuit-
board interconnections to be tested, external components tested, and the state of
chip digital I/Os to be sampled.
59 What are the different chip level test techniques? K1
i. Fault models: Stuck at faults, Stuck-open or Stuck-Shut-Fault
ii. Scan path: Full scan, Partial scan
iii. Boundary scan Check- JTAG, TAP Controller, BIST
60 Explain VLSI verification and testing. K2
VLSI verification is done before manufacturing. Before even tapeout. This is
done for verifying if the chip design is working as expected. For example if we
have a counter design in Verilog, we can simulate the verilog file and verify if
the sequence is correct. This is functionality check.
VLSI testing is done after manufacturing. After the chips are made, we will
look for any structural damages or mistakes in the chip. At this stage, we will
check if the chip passes the test. We have to put some extra special logic into
the chip before it is taped out. This is called as Design For Testing (DFT).
PART B & PART C (13 & 15 Marks)
61 Explain the general architecture of FPGA and bring about different 13 K2
programmable blocks used.
62 Explain the programmable interconnects and I/O blocks used in FPGA. 15 K2
63 Why SRAM based FPGAs are popular when compared to other types? 13 K2
Explain?
64 Explain the manufacturing test principle with an example of digital 8 K2
logic circuits.
65 Describe the various types of adhoc testing techniques with neat 13 K1
diagram.
66 Outline the need of Observability for integrated circuits. 6 K2
67 Illustrate the concepts of short circuit and open circuit fault. 13 K2
68 Explain the architecture of parallel scan testing method. 13 K2
69 Interpret the boundary scan architectures and explain how test the 13 K2
circuit board level and system level.
70 Describe briefly about the BIST block structure along its components. 13 K1
71 Give a short note on stuck-at faults model. 6 K1
72 Explain the small finite state machine of TAP architecture. 13 K2
73 Draw the block diagram of BILBO\BIST and explain each unit 13 K2
operation.
74 Illustrate the steps involved in design for manufacturability to increase 13 K2
the yield of optimized circuit.
75 Draw and explain the building blocks of FPGA with different fusing 15 K2
technologies.
76 Discuss in detail about different types of scan design method and 15 K2
explain with neat diagram.

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