1

CHAPTER 1

INTRODUCTION TO MOS TRANSISTOR

1.1 BRIEF HISTORY

Until 1950s, electronic active device technology was dominated by Vacuum Tube devices. The
situation was totally changed with the invention of Transistor by William B. Shockley, Walter H.
Brattain and John Bardeen of Bell Telephone Laboratories in 1947. The transistor invention was
followed by the development of Integrated Circuit (IC). The first IC in the form of a flip-flop was
invented by Jack Kilby in the semiconductor laboratory of Texas Instruments in 1958. This
historic invention has subsequently led to the miniaturisation of electronic components and
reduced costs. Nobel prizes in Physics were awarded to W.Shockley in 1956 and J.Kilby in 2000.
In 1965, the first MOS logic gate was introduced by Frank Wanlass of Fairchild, USA. This gate
used both nMOS and pMOS transistors. However, the manufacturing processes were complex,
which delayed the commercial usage of the technology. The first practical MOS IC was
fabricated using pMOS logic for digital calculators. In 1970, the first microprocessor 4004 was
introduced by Intel.
In 1965, Gordon Moore, co-founder of Intel, predicted that the numbers of transistors
incorporated in a chip will approximately double every two years. This prediction is generally
known as Moore’s law. The prediction and actual count of transistors per chip is shown in Figure
1.1.

Figure 1.1 Moore’s Law Illustration

Depending on the number of transistors present in a chip, ICs are classified into various
levels of integration. They are, Small Scale Integration (SSI), Medium Scale Integration (MSI),
Large Scale Integration (LSI) and Very Large Scale Integration (VLSI). Number of transistors in a
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SSI chip is less than 100. An example of SSI is the Hex inverter IC 7404. Number of transistors
integrated into a MSI chip is between 100 and 1000. IC 74161 counter is an example of MSI
chip.LSI chips like 8-bit microprocessors have up to 10000 transistors. A chip with more than
10000 transistors is generally termed as a VLSI chip. All modern microprocessors are VLSI chips.
For example, Intel’s Atom microprocessor contains 4.7 crores of transistors. Another example is a
16 GB Flash memory, which contains more than 400 crores of transistors.

1.2 nMOS AND pMOS TRANSISTORS

A metal-oxide-semiconductor (MOS) transistor is a four terminal device. It is fabricated by

superimposing layers of conducting and insulating materials. Each MOS transistor consists of a
stack of silicon wafer called as body, bulk or substrate, an insulating layer of silicon dioxide
(SiO2), and the gate. Gates of early transistors were fabricated from metal, so the stack was called
metal oxide-semiconductor, or MOS. Since the 1970s, the gate has been fabricated from
polycrystalline silicon (Polysilicon), but the same name is used. The current flow in a MOS
transistor is controlled by a voltage applied to the gate. Hence it is called as a voltage-controlled
device.
Types of MOS transistors:
1. n-type transistor (nMOS)
2. p-type transistor (pMOS)

Unlike bipolar transistor, current flow in a MOS transistor is due to majority carriers
only. In an nMOS transistor, majority carriers are electrons and the current flow is also due to
electrons. In a pMOS transistor, the majority carriers are holes. Since the MOS transistor
operation is controlled by electric fields, it is also called as Metal Oxide Semiconductor Field
Effect Transistors (MOSFETs).
Figure 1.2 shows the structure of nMOS and pMOS transistors. An nMOS device consists
of a moderately doped p-type substrate or body. Two heavily doped n+ regions (source and
drain) are diffused into the body. Between these two regions, there is a narrow region of p-type
body, which is known as the channel. The channel is covered by a thin layer of SiO2, which acts
as an insulator. Above the oxide layer, a polysilicon layer is deposited, which is the gate. Because
of the insulator layer, the gate and the channel are electrically isolated and no current flows from
the gate to channel or vice versa. Source and drain are physically equivalent and
interchangeable. The + symbol in the source and drain indicates that they are heavily doped
regions. The body is typically grounded. The gate is a control input that controls the flow of
current between the source and drain.
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A pMOS transistor is just the opposite, consisting of a p-type source and drain, and an n-
type body. In a CMOS technology which uses both types of transistors, the body could be either
n-type or p-type.

(a) nMOS transistor (b) pMOS transistor

The symbols of nMOS and pMOS are shown in Figure 1.2. with three terminals source,
gate and the drain. The fourth terminal is the body, which is generally connected to a dc supply
(GND for nMOS and VDD for pMOS). So it is sometimes not shown in symbols. The symbol for
the pMOS transistor has a bubble on the gate, which indicates that the transistor behaviour is the
opposite of nMOS.

Figure 1.2 Cross Sections and symbols for nMOS and pMOS transistors

1.2.1 Threshold voltage

The first parameter of interest in the operation of a MOS transistor is the threshold voltage (Vt).
It is defined as the gate voltage at which a MOS transistor starts to conduct. It is also defined as
the gate voltage at which strong inversion occurs. It is positive for a nMOS transistor and
negative for a pMOS transistor.
The value of threshold voltage depends on number of parameters. Some of the parameters are
given below:-
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• Gate material doping

• Gate material
• Channel doping
• thickness of silicon dioxide
• impurities at the interface of silicon-insulator
• voltage between source and substrate (body effect)

1.2.2 MOS Transistor Operation

The behaviour and operation of a MOS transistor can be understood by first examining
an isolated MOS structure with a gate and body but no source or drain. Figure 1.3 shows such a
simple MOS structure.
Top layer - polysilicon gate
Middle layer - thin insulating layer of SiO2, called the gate oxide
Bottom layer - the doped silicon body

A p-type body is used in this example that has charge carriers as holes. The body is connected to
ground. The gate is the control input. Behaviour of the MOS transistor varies with the gate
voltage.
Let Vg denote the gate voltage.
Vg < 0 : -
A negative voltage is applied to the gate. The mobile positively charged holes are attracted to the
region below the gate. This is called the accumulation mode (Figure 1.3(a)).
0< Vg < Vt :-
When a small positive voltage less than the threshold voltage (V t) is applied to the gate, holes in
the body are repelled from the region directly below the gate. This results in the formation of a
depletion region below the gate. This is called as depletion mode (Figure 1.3(b)).
Vg > Vt :-
When the gate voltage is higher than Vt, holes are repelled away from the gate and some free
electrons in the body are attracted to the region below the gate to form a conducting layer. This
conductive layer of electrons in the p-type body is called the inversion region (Figure 1.3(c)).
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Figure 1.3 MOS transistor behaviour (a) accumulation (b) depletion (c) inversion

1.2.3 MOS Transistor –Regions of operation

Depending on the values of gate-to-source voltage Vgs , and the drain to source voltage Vds , the

MOS transistor can operate in three different regions. The three regions of operation are,
• cut-off region
• linear /triode/unsaturated region
• saturation region

Cut-off region:
Initially, the gate-to-source voltage (Vgs) is less than the threshold voltage (V t). The source and
drain are electrically insulated. This is because of the absence of a conducting channel between
source and drain. Since the source is connected to ground, the p-n junctions between the body
and the source or drain are zero-biased or reverse-biased, so little or no current flows (Figure 1.5
a). This region of operation is called as cut-off region and the transistor is OFF under this
condition.
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Linear Region: -
When the gate voltage (Vg) is greater than the threshold voltage (V t), the holes in the body are
repelled away from the gate. At the same time, electrons in the body get attracted towards the
gate. Due to the accumulation of attracted electrons, the region under the gate changes from p-
type to n-type and creates a conductive path between the source and drain. This is the inversion
condition. The transistor is now ON. When a small positive voltage Vds is applied to the drain
(Figure 1.5(b & c)) under this condition, electrons present in the channel sweeps towards the
drain. Since the current increases linearly with both the drain voltage and gate voltage, this
region is also called as linear or resistive region. Other names for this region of operation are
triode or unsaturated .

Figure 1.4 MOS transistor- regions of operation

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Saturation Region:

As Vds is increased further, the shape of the channel starts to change due to the resistive drop
along the channel. The full gate voltage is effective at the source end of the channel. But, at the
drain end of the channel, only the difference between gate and drain voltage (Vgd) is effective. If
Vds becomes sufficiently large such that Vgd > Vt , the channel is no longer inverted near the
drain end (Figure 1.5(d)). This is the pinch-off condition. But, conduction still occurs by the drift
of electrons towards the drain due to the effect of positive drain voltage. That is, as electrons
reach the end of the channel, they are injected into the depletion region near the drain and
accelerated toward the drain. The drain current is now independent of the drain voltage and is
controlled only by the gate voltage. The transistor is now said to be in the saturation region.

Summary:

Voltage Region Behaviour of the transistor

Vgs < Vt Cutoff Transistor is OFF

Transistor is ON
Vgs >Vt , 0< Vds < (Vgs-Vt) Linear Acts as a resistor
current flow is proportional to Vds
Transistor is ON
Vgs > Vt , Vds > (Vgs-Vt) Saturation Acts as a current source
current flow is independent of Vds

1.2. 4 MOS transistor as a switch

Figure 1.5 MOS transistors as switches

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A MOS transistor can be viewed as a simple ON/OFF switch. When a positive voltage greater
than the threshold voltage (shown as g=1) is applied to the gate of an nMOS transistor, the
transistor is ON and there is a conducting path from source to drain. When the gate voltage falls
below the threshold voltage (g=0), the nMOS transistor is OFF, and almost zero current flows
from source to drain.
A pMOS transistor behaves just the opposite, being ON when the gate voltage is low,
and OFF when the gate voltage is high. The switch model of transistors is shown in Figure 1.5,
where g,s, and d indicate gate, source, and drain respectively.

1.2.5 CMOS Logic Gates

In general, a Complementary MOS (CMOS) logic gate has an nMOS pull-down network to connect
the output to 0 (GND) and pMOS pull-up network to connect the output to 1 (VDD). Figure 1.6
shows the general structure of a CMOS logic gate. The networks are arranged such that when
one network is ON, the other is OFF for any input pattern.

Figure 1.6 CMOS- General Structure

1.2.6 The CMOS Inverter

Figure 1.7 shows the circuit diagram and symbol for a CMOS inverter which uses one nMOS
transistor in the pull-down network and one pMOS transistor in the pull-up network. When the
input A is at logic 0, the nMOS transistor is OFF and the pMOS transistor is ON. The output Y is
pulled up to 1 through the pMOS transistor which is ON. On the other hand, when A is at logic
1, the nMOS is ON and the pMOS is OFF. Y is pulled down to logic 0 through the nMOS
transistor. This behaviour is explained in Table 1.1.
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(a) (b)

Figure 1.7 CMOS inverter a) schematic b) symbol

Table 1.1 Inverter Truth Table

A Y

0 1
1 0

1.3 PROCESS PARAMETERS FOR MOS AND CMOS

Some of the process parameters affect the transistor parameters as well as the output of digital
circuits. The fabrication process has an effect on the chip cost also. Hence an understanding of
the manufacturing process is required for digital design engineers. A brief description of the
modern IC manufacturing process is given along with steps and techniques.

1.3.1 Fabrication basics

A pMOS transistor is always created either an n-type substrate or an n-well. An NMOS transistor
is fabricated in either a p-type substrate or a p-well. Both transistors are fabricated on thin silicon
wafers known as the substrate. A substrate serves as a mechanical support and an electrical
common point. A CMOS chip fabrication needs both nMOS and pMOS transistors. Therefore,
fabrication process is explained for a CMOS inverter.

1.3.2 Fabrication of CMOS inverter

The CMOS inverter is built on a p-type substrate. This p-type substrate also acts as the body for
the nMOS transistor. Since the pMOS transistor needs an n-type body, an n-well is diffused into
the p-type substrate. The nMOS transistor has heavily doped n-type (n+) source and drain
regions. A polysilicon gate is built over a thin layer of silicon dioxide (SiO2). It is also called as
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gate oxide. The pMOS transistor is a similar structure with p-type source and drain regions.
Figure 1.8 shows the cross-section of a CMOS inverter.

Figure 1.8 Inverter cross-section

Interconnections:-

• The polysilicon gates of the two transistors are connected together to form the input A.
• The source of the nMOS transistor is connected to a metal ground line and the source of
the pMOS transistor is connected to a metal VDD line.
• The drains of the two transistors are connected with metal to form the output Y.

A thick layer of SiO2 called field oxide prevents metal from shorting to other layers except where
contacts are explicitly etched.

Steps in CMOS Inverter Fabrication

In the fabrication process, several layers of the chip are defined through a process called
photolithography. Photolithography process uses a set of masks to specify the placement of
components on the chip. A set of six masks are used in the inverter fabrication. The six masks
are,

1. n-well 4. p+ diffusion
2. polysilicon 5. Contacts
3. n+ diffusion 6. metal
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1. Creation of n-well:-

Figure 1.8 shows the processing steps involved in forming the n-well. Figure 1.8(a) shows the p-
type substrate. Steps in n-well formation are given below:-

i. SiO2 layer formation

The first step is to grow a protective layer of oxide is grown over the over the entire
substrate. This is done by oxidizing the wafer in a high temperature (900–1200 °C)
furnace. Si and O2 reacts and become SiO2 on the wafer surface. See Figure 1.9(b)).

ii. Patterning

The SiO2 is to be removed from the region where the n-well has to be fabricated. For this
purpose, the Si02 is covered with a photo-resist material (Figure 1.9(c)). The photo-resist
is then exposed through the n-well mask. The mask allows light to pass through region
where the well should be fabricated. The softened photo-resist is removed to expose the
oxide (Figure 1.9(d)). The oxide is etched with hydrofluoric acid (HF) where it is not
protected by the photo resist (Figure 1.9(e)). Then the remaining photo-resist is stripped
away using a mixture of acids (Figure 1.9(f )).

iii. Formation of n-well

The well is formed in the region where the substrate is not covered with oxide. The n-
type dopant is added through a diffusion process. In the diffusion process, the wafer is
placed in a furnace with a gas containing the dopants and heated. The dopant atoms
diffuse into the substrate (Figure 1.9(g)). Finally, the remaining oxide is stripped off to
get n-well in the required place.
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Figure 1.9 Creation of n-well

2. Gate Formation:-

The transistor gates are made of polysilicon over a thin layer of oxide. First, the thin oxide is
grown in a furnace. Then the wafer is placed in a reactor with silane gas (SiH4) and heated again
to grow the polysilicon layer through a process called chemical vapour deposition. The polysilicon is
heavily doped to form a reasonably good conductor. The resulting structure is shown in Figure
1.10(a). As before, the wafer is patterned with photo-resist and the polysilicon mask (Figure
1.10(b)) to get the polysilicon gates.
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Figure 1.10 Gate formation

3. Source and Drain regions (n-diffusion)

This process is similar to the n-well formation. A protective layer of oxide is formed (Figure
1.11(c)) and patterned with the n-diffusion mask (Figure 1.11(d)) to expose the source and drain
areas (Figure 1.37(d)). The n+ diffusion regions are now formed Figure 1.11(e). Note that the
polysilicon gate over the nMOS transistor blocks the diffusion so the source and drain are
separated by a channel under the gate. This is called a self-aligned process because the source
and drain of the transistor are automatically formed adjacent to the gate without the need to
precisely align the masks. Finally, the protective oxide is removed through stripping process
(Figure 1.11(f)).

Figure 1.11 Source and Drain Formation

The process is repeated for the p-diffusion mask to give the structure shown in Figure 1.12(a).
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4. Contacts:

The field oxide is grown to insulate the wafer from metal and patterned with the contact mask
(Figure 1.12(b)) to leave contact cuts where metal should attach to diffusion or polysilicon.
Finally, aluminium is deposited over the entire wafer, filling the contact cuts as well. The metal is
patterned with the metal mask (Figure 1.12(c)) and plasma etched to remove metal everywhere
except where wires should remain.
This completes the fabrication process for a CMOS inverter.

(a) p-diffusion

(b) Contacts

(c) Metal
Figure 1.12 Inverter Cross section after fabrication of various layers

1.3.3 Process Parameters

In general, identical transistors fabricated from the same die should have identical parameters.
But, in reality, the parameters are different even for transistors made on the same die. The
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primary reason for this deviation is the variations in the process parameters. Process parameters
vary due to non-uniform conditions during the deposition of the impurities, variation in oxide
thickness, depth of diffusion etc. Variations in the process parameters result in changes in the
values for sheet resistances and threshold voltage of transistors. The process variations may
affect the output of a digital circuit. A microprocessor designed to run at a clock frequency of
1GHZ may run at a slightly lower or higher frequency.

For example, the following transistor parameters are affected by process parameters:-

Transistor parameter Affecting process parameter

Threshold voltage Changes in oxide thickness

Substrate and poly impurity level
Surface charge
Transconductance Oxide thickness
Mobility Oxide thickness
Channel length and width Varies due to lithographic process

1.4 ELECTRICAL PROPERTIES OF CMOS CIRCUITS

The electrical properties of a MOS transistor can be understood by observing its I-V
characteristics for long-channel and short channel devices. When the channel length of a
transistor is more than 1 μm, it is known as a long channel device. Devices with channel length
below 1 μm are short channel devices. The I-V characteristics of a long-channel device is
generally known as ideal I-V characteristics or long-channel I-V characteristics.

1.4.1 Ideal I-V Characteristics

The long-channel model is known as the first- order, ideal or Shockley model. This model does
not consider many effects that are present in short-channel transistors. Hence, the long-channel
model is not sufficient for accurate calculations of currents. But this model is generally used to
understand the behaviour of transistor voltages and currents in various regions of operations.

We know that a MOS transistor has three different regions of operation:-

a. Cutoff region
b. Linear region
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c. Saturation region
Using the long-channel model, we can relate the voltages and currents in these three regions of
operation.

Cut-off Region:-

In cut-off region, the long-channel model assumes that the current through an OFF transistor is 0.

Linear Region:-

For the linear region, Vgs > Vt, but Vds is relatively small. It is called linear or resistive because
when Vds << (Vgs –Vt ) , Ids increases almost linearly with Vds, just like an ideal resistor. When
Vgs  Vt , the nMOS transistor becomes ON, and electrons accumulate below the gate to form the

conducting channel. When a positive voltage is applied to the drain such that Vds  (Vgs − Vt ) ,

these electrons drift from source to drain at a rate proportional to the electric field between these
regions.
We know that the gate along with the oxide and channel acts as a parallel plate capacitor.
The general equation for the charge on each plate of a capacitor is
Q=CV (1.1)
Thus, the charge in the channel, Qchannel is given by,

Qchannel = Cg (Vgc − Vt ) (1.2)

where
Cg - Capacitance of the gate to the channel

Vgc − Vt - The amount of voltage attracting charge to the channel beyond the minimum

required to invert from p to n.

The gate voltage is referenced to the channel, which is not grounded.

Let Vs - source voltage

Vd - drain voltage

Vs + Vd V
Average voltage , Vc = = Vs + ds
2 2 (1.3)
Therefore, the mean difference between the gate and channel potentials,
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Vds V
Vgc = Vg − Vc = Vg − Vs − = Vgs − ds
2 2 (1.4)
This is shown in Figure 1.13.

(a) Voltages between terminals

(b) Channel
Figure 1.13 nMOS Transistor showing voltages and channel

Gate Capacitance calculation:-

We can model the gate as a parallel plate capacitor with capacitance proportional to area over
thickness. If the gate has length L and width W and the oxide thickness is tox , as shown in Figure

1.6, the capacitance is

WL WL
Cg = kox 0 =  ox = CoxWL (1.5)
tox tox

where

0 = 8.85 x10–14 F/cm, permittivity of free space

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kox = 3.9  0 , permittivity of SiO2

tox - Oxide thickness

 ox
The ratio of Cox = is called gate oxide capacitance, Cox. It is the capacitance per unit area of
tox
the gate oxide. That is,

 ox
Cox =
tox (1.6)
Each carrier in the channel is accelerated to an average velocity, v, proportional to the lateral
electric field between source and drain. The constant of proportionality  is called the mobility.

v = E (1.7)

The electric field E is the voltage difference between drain and source Vds divided by the channel
length, L.
Vds
E= (1.8)
L
Channel Length L
Time required for electrons to cross the channel, tch = =
Carrier Velocity v

Therefore, the current between source and drain (I ds) is the total amount of charge in the channel
divided by the time required to cross the channel.

The linear region drain current equation is now obtained as,

Qchannel Qchannel
I ds = =
tch L
v
W  Vds2 
=  Cox  gs
(V − V )V − 
2 
t ds
L 

 V2  (1.9)
=   (Vgs − Vt )Vds − ds 
 2 
where
W (1.10)
 = Cox
L
 is known as the device trans-conductance.

Saturation region:-
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Saturation region begins when Vds = Vgs − Vt . If Vds > (Vgs – Vt) , the channel is no longer

inverted near the drain end and we say that the channel is pinched off. Once the channel is
pinched off, the drain voltage has no effect on drain current. The drain current is now called as
the saturation current.
The drain current equation for saturation region can be obtained by substituting
Vds = Vgs − Vt in Equation 1.9. So we get,

 (Vgs − Vt )2   (Vgs − Vt )2 
I ds =   (Vgs − Vt )(Vgs − Vt ) −  =  (V −
 gs t V ) 2
−  (1.11)
 2   2 
   

= (Vgs − Vt ) 2 (1.12)
2

Note that the drain current equation in the saturation region is independent of Vds .

Summary of current equations in three regions for nMOS transistor:-


0 Vgs  Vt Cutoff
 (1.13)
  V 2
I ds =   (Vgs − Vt )Vds − ds  Vgs  Vt Linear
  2 

 (Vgs − Vt ) Vgs  Vt
2
Saturation
2

Figure 1.14(a) shows the I-V characteristics for the nMOS transistor. According to the long-
channel model, the current is zero for gate voltages below Vt. For higher gate voltages, current
increases linearly with Vds for small Vds . As Vds reaches the saturation point, current becomes

independent of Vds .

The I-V characteristics of pMOS transistors can be derived in the same way, except that
the signs of all voltages and currents are reversed. The I-V characteristics of a pMOS exist in the
third quadrant, as shown in Figure 1.14(b). Since the mobility of holes is less than that of
electrons, pMOS transistors provide less current when compared to nMOS transistors of the
same size.
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(a)nMOS

(b) pMOS

Figure 1.14 I-V characteristics of ideal nMOS and pMOS transistors

Drawbacks of the Shockley model:-

• Overestimates current at high voltage because it does not account for mobility
degradation and velocity saturation caused by the high electric fields.

1.4.2 Non-ideal I-V Effects

The Shockley model described above assumes that the carrier mobility is independent of the
applied fields and temperature. Also, the threshold voltage is assumed as constant. But, this is
not true for a short channel device. Both threshold voltage and mobility change with
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temperature and affect the drain current. Due to the impact of various parameters, drain current
characteristics deviate from the ideal behaviour to generate non-ideal characteristics.

i) Velocity Saturation

The velocity (v) of electrons in a device is related to the electric field strength (E) by mobility.
v = E
This means that the carrier velocity should increase linearly with the field strength. In
other words, carrier mobility is a constant. But at high lateral field strengths, the carrier velocity
becomes nonlinear and saturates due to scattering effects or collisions between electrons. This
effect is known as velocity saturation and is shown in Figure. The velocity saturation reduces
drain current at high Vds.

Figure Velocity-saturation effect

ii) Mobility degradation

The velocity saturation effect considers the effect of horizontal field (field between drain and
source) in the current calculations. In addition to the horizontal field, a vertical electric field
exists over the channel due to gate voltage. If gate voltage is high, it attracts carriers to the edge
of the channel, causing collisions with the oxide interface. Charge carriers slow down due to
these collisions. This effect is called mobility degradation. Mobility degradation reduces the
drain current. Mobility degradation is modelled by replacing  with eff that is a function of

Vgs.

iii) Channel Length modulation

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The saturation region current equation is independent of the Vds term. So, drain current in this
region should not vary with Vds. But this is not true for short-channel devices. When Vds is
increased, depletion region at the drain end in the channel also increases. The increase in
depletion region effectively reduces the channel length. This is known as the channel length
modulation. The reduced channel length is given by,
Leff = L − Ld
(1.14)
As per the saturation current equation, shorter channel length results in higher drain
current. In other words, Ids increases with Vds when there is channel length modulation. The
drain current equation for the saturation region including the effect of channel length
modulation is given as,

I ds = (Vgs − Vt ) 2 (1 + Vds ) (1.15)
2
where  is an empirical parameter added in the equation to show the effect of channel length
modulation. Channel length modulation is very important for analog IC designers because it
reduces the gain of amplifiers.

iv) Threshold voltage Effects

So far we have considered threshold voltage as constant. But it varies with various voltages and
channel length.

a. Body effect

Ideally, voltage between body and source (VBS) is zero. If the voltage between source and body
terminals is non-zero, it increases the amount of charge required to invert the channel. Hence, it
increases the threshold voltage. This increase in threshold voltage due to the non-zero VBS is
known as the body effect. Threshold voltage including the body effect is modeled as,

Vt = Vt 0 +  ( −2F + VSB − −2F ) (1.16)

where

Vt 0 - Threshold voltage when the VSB=0

F - Fermi potential at threshold

 - Body effect coefficient, typically in the range 0.4 to 1 V

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The effect of non-zero body voltage on the threshold voltage is shown in Figure for a nMOS
transistor for −2F = 0.6V and  = 0.4V . A negative body voltage increases the threshold

from 0.45V to 0.85V.

Figure showing Body effect

b. Drain Induced Barrier Lowering

The drain voltage Vds generates a horizontal electric field that affects the threshold voltage. This
effect is known as Drain Induced Barrier Lowering (DIBL) and is more dominant in short

channel transistors. DIBL effect increases Ids with Vds in saturation region. It also increases sub-
threshold voltage. The DIBL effect is modelled as,

Vt = Vt 0 − Vds (1.17)

Where C gs = Csb = Cdb = 1 fF /  m - DIBL coefficient

c. Short Channel Effect

The threshold voltage typically increases with channel length.

v)Latch-up:-
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Latchup occurs in CMOS devices due to the structure of a CMOS process. The result of this effect
is the flow of too much current from the power supply leading to self-destruction of the chip or
system failure that can only be resolved by shutting down the system.
The origin of latchup can be understood by considering the CMOS structure shown in
Figure 1.15. nMOS transistor is fabricated in the p-substrate, and pMOS transistor is fabricated
in the n-well. Due to the construction of the CMOS transistor, two parasitic bipolar transistors
are formed. The parasitic n-p-n bipolar transistor in the p-substrate is formed by the source of the
NMOS, the p-substrate and the n-well. The parasitic p-n-p bipolar transistor in the n-well is
formed by p-substrate, the n-well and the source of the PMOS. In addition, resistance of n-well
and p-substrate forms two resistors Rpsubs and Rnwell . The equivalent circuit is shown in Fig (b).
Since both bipolar transistors are connected back to back, when any one of the two bipolar
transistors gets forward biased due to current flowing through the well or substrate, it feeds the
base of the other transistor. This positive feedback is regenerative and hence increases the
current in the other transistor, finally leading to the circuit failure.

Latchup can be prevented by designing the structure so that there is no feedback network. In
particular, latchup effect is reduced by using the following techniques:-
i. Minimize resistances Rnwell and Rpsubs
ii. Provide a substrate contact for every well. Connect every substrate contact to a
supply pad by metal directly
iii. Place well and substrate contacts, close to the source connections of the MOS
transistor connected to the supply rail. That is, VDD for p-devices and VSS for n-
device.

Figure 1.15 CMOS latchup

 25

The most probable place for latchup is in I/O structures where current flow is large or large
parasitic components are present. A set of rules are applied to design such structures to
minimize the possibility of latchup. Rules for a p-well process are given below:-
1. Physically separate p and n driver-transistors
2. Provide p guard rings around n devices connected to Vss, and n guard rings around p
devices connected to VDD. A guard ring is a doped region that is placed around the
device. Although they are effective in preventing latchup, guard rings increase the chip
area.
3. Use minimum area p-wells to minimize p-well photocurrent

Latchup is almost eliminated from modern chip through process innovations and improvement
in design.

1.4.3 C-V Characteristics

Each terminal (source, drain and gate) of a MOS transistor has capacitance to the other terminals.
These capacitances are nonlinear and voltage dependent. Figure 1.15 shows the capacitances
present in an inverter.

Figure 1.15 Capacitances in a CMOS inverter

MOS Capacitance models:

The gate of a MOS transistor is a good capacitor. The gate is viewed as a capacitor with top plate
as the polysilicon gate, bottom plate as the channel and the oxide layer as the insulator. This
capacitance is given by,
 o ins A  oxWL  ox
Gate capacitance, Cg = = = WL = CoxWL (1.18)
d tox tox
 26

where
 ox
= Cox
tox (1.19)
Since the MOS gate sits over the channel, it partially overlaps the source and drain regions.
Therefore, the gate capacitance has two components:-

1. The intrinsic gate capacitance (Co):-

This capacitance is approximated as,

C0 = CoxWL
(1.20)

This capacitance has different values depending on the region of operation of the MOS
transistor.

Cut-off:- The channel is not inverted in this region. Charge on the gate is matched with opposite
charge from the body. Thus we get Cgb , gate to body capacitance equal to C0 .

Linear Region: Channel is inverted in this region. Since the channel connects source and drain
regions, we get two capacitances:-
C0
Cgs = Cgd = (1.21)
2
Saturation:- Channel is pinched off in this region. At this point, Capacitance exists between gate
and source only. Its value is given by,
2
Cgs = C0
3 (1.22)

Table 1.1 Capacitances in CMOS inverter

Parameter Cut-off Linear Saturation

C gb  C0  C0 0 0

C gs 0 C0 / 2 2/3 C0

Cgd 0 C0 / 2 0

C0 C0 2/3 C0
 27

2. Overlap capacitances:-

In a practical MOS transistor, gate overlaps the source and drain by a small amount. This will
generate overlap capacitances. Their value is proportional to the width (W) of the transistor.
Figure 1.16 shows overlap capacitances.

Cgs (overlap ) = Cgsol W

(1.23)
Cgd (overlap) = Cgdol W
(1.24)

where Cgsol = Cgdol = 0.2 − 0.4 fF /  m

Figure 1.16 Overlap capacitances

In addition to the gate capacitance, source and drain also have capacitances. These are
parasitic capacitances. The p-n junctions formed between the source, drain and the body leads to
these capacitances. They are also known as diffusion capacitances. As diffusion has high
capacitance and high resistance, it is generally made very small in layouts. Values of these
capacitances are comparable to the gate capacitance. That is,
C gs = Csb = Cdb = 1 fF /  m (1.25)
Where
Cdb - drain to body diffusion capacitance

C sb - Source to body diffusion capacitance

The C-V characteristics for an nMOS transistor is shown in Figure1.17.

 28

Figure 1.17 C-V Characteristics of the MOS Transistor

1.4.4 DC Transfer Characteristics of CMOS Inverter

The DC input-output transfer characteristic is also called as voltage transfer

characteristics (VTC). It is simply a plot of the output voltage (Vout) as a function of the input
voltage (Vin) . For deriving the transfer characteristics of an inverter, transistor current
equations for the linear and saturation regions are used.

Figure 1.18 CMOS Inverter showing currents

Since the source of nMOS transistor is connected to GND,

Vgsn = Vin
Vdsn = Vout
Since the source of pMOS transistor is connected to VDD,
Vgsp= Vin-VDD
Vdsp= Vin-Vout

Table 1.2 gives the various regions of operations for nMOS and pMOS transistors using these
notations.
 29

TABLE 1.2 Relationships between voltages for the three regions of operation of a CMOS inverter

Cutoff Linear Saturation

nMOS Vin<Vtn Vin>Vtn Vin>Vtn

Vout< Vin-Vtn Vout>Vin-
Vtn
pMOS Vin>Vtp+VDD Vin<Vtp+VDD Vin<
Vout>Vin-Vtp Vtp+VDD
Vout <Vin-
Vtp

The operation of CMOS inverter can be divided into five regions as shown in Figure1.19 (a).

Region A:
The nMOS transistor is OFF and the pMOS is in linear region. The pMOS transistor pulls the
output to VDD.
Region B :
The pMOS transistor is in linear region while the nMOS transistor turns ON and goes to
saturation region. The output starts falling.
Region C:
Both transistors are ON and in saturation region. This condition occurs for Vin = VDD/2 .
Region C is a point in the transfer characteristics.
Region D:
The pMOS transistor is in saturation and nMOS is in linear region. Output falls further.
Region E:
The pMOS transistor is completely OFF while nMOS is in linear region. The output falls to zero.

A summary of the relation between voltages for different regions of operation is given in Table
1.3.

Table 1.3 Regions and their output

 30

The DC characteristics can be derived graphically or analytically. Figure1.19 (a) shows the drain
currents Idsn and Idsp as a function of Vdsn, Vdsp, Vgsn and Vgsp. Figure 1.19 (b) shows the
same currents as a function of Vout for various values of Vin. The operating points of the
inverter are the values of Vout where Idsn=|Idsp| for a given value of Vin. In Figure 1.19 (c)
these values are plotted to get the DC transfers characteristics.
The supply current IDD is also plotted against Vin to show the I-V characteristics of the
inverter, which is a current pulse.

(a) Transfer Characteristics

(b) I-V Characteristics

 31

Figure 1.19 Graphical Derivations of CMOS Inverter Characteristics

In a CMOS inverter, current consumption is zero when the input Vin is at logic 1 or logic 0.
When the input goes from 1 to 0 or 0 to 1, both transistors are ON for a short period of time. This
results in a short current pulse and this feature is important in low power operation.

NOISE MARGIN
Noise margin is a parameter used to calculate the permitted noise levels at the input of a gate so
that the output is not corrupted. It is a measure of sensitivity of a gate to noise. The specification
uses two parameters:-
1. The LOW noise margin, NML
2. The HIGH noise margin, NMH
NML is defined as the difference between the maximum LOW input voltage detected by the
receiving gate and the maximum LOW output voltage produced by the driving gate.

NMH is defined as the difference between the minimum HIGH output voltage of the driving gate
and the minimum HIGH input voltage of the receiving gate.

where
VIL - maximum LOW input voltage
VOL - maximum LOW output voltage
VOH - minimum HIGH output voltage
VIH - minimum HIGH input voltage
 32

Figure Definition of noise margin

Figure Noise margins for a CMOS inverter

When the input value is between VIL and VIH it is said to be in the indeterminate region with
undefined logic levels. So, it is preferred to have these two values close to each other. This
implies a sharp transition in the transfer characteristic or, a high gain in the transition region.
The definition of voltage levels VIL, VIH, VOL and VOH are shown in Figure along with the transfer
characteristic of CMOS inverter. Logic levels are defined at the unity gain point where the slope
is –1. For the inverter shown in Figure , the NML is 0.46 VDD while the NMH is 0.13 VDD. If
either NML or NMH for a gate is very small, the gate may be affected by noise on its inputs.

1.6 SCALING PRINCIPLES AND FUNDAMENTAL LIMITS

Scaling is basically shrinking the dimensions of transistors, interconnections and the spacing
between features, by adjusting the doping levels and supply voltages for increasing the packing
density in a chip. Reducing the dimensions and/or voltages affect the electrical behaviour of the
chip.

1.6.1 Types of Scaling

The most commonly used methods are,

a. Constant field scaling (Full Scaling)
b. Constant voltage scaling
c. General scaling
 33

Assumptions:-
1. All device dimensions scale by the same factor S (with S > 1 for a reduction in size). This
includes the width and length of the transistor, the oxide thickness, and the junction
depths.
2. All voltages, including the supply voltage and the threshold voltages, scale by a same
ratio U.
3. Only short-channel devices are considered

a. Constant Field Scaling (Full Scaling)

In this ideal model, all device dimensions, including L and W, are scaled by a scale factor S. The
supply voltage and threshold voltage are also scaled by S. Since both distance and voltage are
scaled equally, the electric field remains constant. Therefore many nonlinear parameters and
secondary effects are not affected.
Advantages of constant field scaling:-
• greater device density (Area)
• higher performance (Intrinsic Delay)
• reduced power consumption (P)
The effects of full scaling on the device and circuit parameters are given in the third column of
Table 1.6.

b. Constant-Voltage Scaling

Practically, full scaling is not a feasible option due to the following reasons:-
i. First of all, voltages cannot be scaled arbitrarily to avoid compatibility issues of the
new devices with the existing devices.
ii. Multiple supply voltages increases the cost of a system

In constant voltage scaling, voltages are not scaled. Historically, when feature sizes were scaled
from 6  m to 1  m , supply voltage was kept at 5V. Only with the introduction of the 0.5  m

CMOS technology, new voltage levels such as 3.3 V and 2.5 V were used. This technique
achieved quadratic delay reduction and cost reduction. Another advantage of this method is a
net reduction in on-resistance.
Disadvantages:-
 34

• Constant voltage scaling increased electric fields in devices. There is a possibility of

device breakdown due to high field.
• In a velocity-saturated device, this method has no performance advantage over the full-
scaling model. more power consumption than the constant field scaling
• Hot-carrier effect is possible

Due to these disadvantages, constant voltage scaling is less preferred.

c. General Scaling

Let us observe from Figure 1.20 that scaling the supply voltages and the technology are not
similar. For example, when the feature size is reduced from 0.5  m to 0.1  m , the maximum

reduction in supply-voltage is from 5 V to 1.5 V. The reason for the difference in scaling is,
• Material parameters such as silicon band-gap and the built-in junction potential
cannot be scaled.
• There is a limit to the scaling of threshold voltage. It is difficult to turn off very low
threshold devices.

Figure 1.20 Feature Size versus Supply Voltage

Due to these reasons, a general scaling model is used. In the general scaling model,
dimensions and voltages are scaled independently by using different scaling factors. The device
dimensions are scaled by a factor S, and voltages are reduced by another factor U. When the
voltage is held constant, (U = 1), this scaling model reduces to the constant-voltage model.
The performance of general-scaling model is similar to the full and the constant voltage
scaling. Its power dissipation lies between the two models (for S > U > 1). A comparison of all
three scaling models is shown in Table 1.6.
 35

Table 1.6 Scaling scenarios for short- channel devices

1.6.2 Impacts of scaling on Design

When a device is scaled, various design parameters are affected. Some of the impacts of scaling
on design are given below:-

1. Improved device Performance and Cost

• faster devices
• Poor performance of long interconnects. It is difficult to send a signal from one side
of a large chip to another side in a single cycle. Multiple pipeline stages are required
in such cases. To avoid such problems, more layers needs to be used for
interconnects. Another design strategy is to use different scale factors for different
layers of interconnects. Reverse-scale of interconnects to make them wider to provide
low-resistance, high speed interconnect, good clock distribution networks, and a stiff
power grid.
• Copper and low-k dielectrics were introduced to reduce resistance and capacitance.

2. Power
In constant field scaling, dynamic power density remains constant and overall chip power
increases only slowly with die size. But, in 1990s, power density increased heavily due to an
 36

increase in clock frequencies. Now the aim of designers is to have maximum performance
for a given power and not an increase in clock frequency.

3. Variability
This is a key factor in scaled devices. Wider guard bands are used by designers to ensure that
an acceptable fraction of chips meet specifications.

4. Productivity
The number of transistors on a chip is increasing faster than designer productivity. Hence
design methodologies that maximize productivity are used. One method is design reuse.
Intellectual property (IP) blocks can be purchased and used as black boxes within a system-
on-chip (SOC) to increase the productivity.

1.6.3 Limits of scaling

a. Physical Limits:

There is a physical limit for scaling. A minimum-sized transistor in a 32 nm process has an

effective channel length of less than 100 Si atoms. The gate oxide is only 4 atoms thick. The
channel contains approximately 50 dopant atoms. The physical limit of scaling is due to the
device dimensions that reach the atomic scale.

Other factors that limit the scaling are,

• Sub-threshold leakage at low VDD and Vt
• Tunnelling current through thin oxides
• Poor I-V characteristics due to DIBL and other short channel effects
• Dynamic power dissipation
• Lithography limitations
• Exponentially increasing costs of fabrication facilities and mask sets
• Electro migration
• Interconnect delay
• Variability

For devices with dimensions below 32 nm, the engineering costs are high. These high costs also
limit the performance and power benefits of geometrical scaling.
 37

1.7 PROPAGATION DELAY

The switching speed of a CMOS gate depends on the time taken to charge and discharge the load
capacitance CL. An input transition results in an output transition that charges or discharges C L.
The charging and discharging action create slopes in the switching waveforms. These slopes are
usually expressed in terms of rise time tr and fall time t f .

tr – Time for a waveform to rise from 10% to 90% of its steady state value

tf – Time for a waveform to fall from 90% to10% of its steady state value

The propagation delay ( t p ) of a gate expresses the delay experienced by a signal when

passing through a gate. This delay defines how quickly a gate it responds to a change at its
input/inputs. For a CMOS inverter, it is measured between the 50% transition points of the input
and output waveforms, as shown in Figure 1.21. Since gates have different response times for
rising or falling input waveforms, two definitions of the propagation delay are necessary.
Let
t pLH - Response time of the gate for a low-to-high output transition

t pHL - Response time of the gate for a high-to-low output transition

The propagation delay tp is defined as the average of the two, and is give as,

t pLH + t pHL
tp = (1.28)
2

Figure 1.21 Definition of Propagation Delay, rise time and fall time
 38

1.7.1 Elmore Delay

The propagation delay of a logic gate can be estimated using Elmore delay formula.

Consider the R-C network shown in Figure 1.22. This circuit is called an RCtree and has the
following properties:
• The network has a single input node (called s)
• All the capacitors are connected between a node and the ground
• The R-C network does not contain any resistive loops (which makes it a tree)

Figure 1.22 Tree structured RC network

For an RCtree, a unique resistive path exists between the source node s and any node i of
the network. The total resistance along this path is called the path resistance Rii. For example, the
path resistance between the source node s and node 4 in the example of Figure 1.22 equals

(1.29)

The definition of the path resistance can be extended to address the shared path resistance Rik,
which represents the resistance shared among the paths from the root nodes to nodes k and i:

(1.30)
Assume now that each of the N nodes of the network is initially discharged to GND, and that a
step input is applied at node s at time t = 0. The Elmore delay at node i is then given by the
following expression:

(1.31)
 39

The Elmore delay is equivalent to the first-order time constant of the network (or the first
moment of the impulse response). The designer should be aware that this time-constant
represents a simple approximation of the actual delay between source node and node i. Yet in
most cases this approximation has proven to be quite reasonable and acceptable. It offers the
designer a powerful mechanism for providing a quick estimate of the delay of a complex
network.

Example: RC delay of a tree structured network

(1.32)

1.7.2 Propagation Delay of an Inverter

The propagation delay of an inverter can be calculated from its RC model.

Resistance estimation:-

For the delay analysis, each transistor is modelled as a resistor in series with an ideal switch. The
value of the resistance depends on the power supply voltage, L and W values. A unit size (L=W)
nMOS transistor has a resistance value equal to R. An nMOS transistor of k times unit width has
a resistance R/k. A pMOS transistor has larger resistance due to less mobility, and has resistance
in the range 2R to 3R. In general, 2R value is used for pMOS transistors.

Capacitance estimation:-

Each transistor also has its gate and diffusion capacitance. Let C be the gate capacitance of a unit
transistor. A transistor of k times the unit width has capacitance kC.

Let Rp - resistance of pMOS transistor

Rn - resistance of nMOS transistor
CL - load capacitance

Figure 1.23 shows the RC switch model of a CMOS inverter. The propagation delay is derived by
analysing this first order RC network. It is assumed that the load-capacitance CL used in the RC
model is identical for both high-to-low and low-to-high transitions.
 40

Figure 1.23 RC model of CMOS inverter

RC model for low-to-high and high-to-low transition are different. The RC model for high-to-low
transition is formed by the pull-down resistance Rn and load capacitance CL. Therefore,
propagation delay for high-to-low transition is given by,
t pHL = ln(2) RnCL = 0.69 RnCL
(1.33)
Similarly, propagation delay for low-to-high transition is given by,

t pLH = ln(2) R p CL = 0.69 R p CL

(1.34)

The overall propagation delay of the inverter is defined as the average of the two values, or
t pHL + t pLH  Rn + R p 
tp = = 0.69   CL
2  2  (1.35)
Propagation delays of both rising and falling inputs can be made identical by making the on-
resistance of the nMOS and pMOS equal.

1.7.3 CMOS Inverter Scaling

The scaling of transistors and the supply voltage in a CMOS inverter affects various parameters.
Effect of scaling the transistors and supply voltage are discussed below:-
 41

1.7.2.1 Effect of transistor scaling on propagation delay

Normal inverter:
Let
Cint - intrinsic output capacitance of the inverter that consists of the diffusion and Miller
capacitances, both of which are proportional to the width of the transistors.
Req - resistance of the reference gate
The propagation delay is given by,

(1.36)

Scaled inverter:

Let S – sizing factor

Cint = SCiref. Req =Rref/S.

The propagation delay of the scaled gate is given by,

(1.37)
Conclusions:-

1. The intrinsic delay of the inverter tp0 is independent of the sizing of the gate, and is purely
decided by technology and inverter layout. When no load is present, an increase in the drive
of the gate is totally offset by the increased capacitance.
2. Making S infinitely large yields the maximum obtainable performance gain, eliminating the
impact of any external load, and reducing the delay to the intrinsic one. Yet, any sizing
factor S that is sufficiently larger than Cext/Cint produces similar results at a
substantial gain in silicon area.

1.7.2.2 Effects of Scaling the Supply Voltage

 42

The gain of the inverter in the transition region increases with a reduction of the supply voltage.
(Ref Figure 1.24 (a)). For a Vdd value of 0.5 V, the width of the transition region measures only
10% of the supply voltage (for a maximum gain of 35), whereas it widens to 17% for 2.5 V. This
shows that the voltage transfer characteristics (VTCs) are better for low supply voltages.

However, reducing the supply voltage has the following effects:-

1. The dc-characteristic becomes more sensitive to variations in the threshold voltage.

2. Scaling of VDD reduces the signal swing, which reduces the internal noise like cross talk. But, it
makes the design more sensitive to external noise sources that are not scaled.

Figure 1.24 Effects of voltage scaling a) steeper transition region b) deterioration at very low Vdd

The limits of voltage scaling are shown in Figure 1.24. The voltage transfer characteristic
of the inverter is plotted for the same threshold voltage, but different power supply voltages of
200 mV, 100 mV, and 50mV. Even for such low value supply voltages, inverter characteristic are
proper. The reason for this behaviour is the sub-threshold operation of the transistors. The sub-
threshold currents are sufficient to switch the gate between low and high levels, and provide
enough gain to produce acceptable voltage transfer characteristics.
When VDD is around 100 mV, VOL and VOH are no longer at the supply rails and the
transition-region gain approaches 1. Hence it can be concluded that, for achieving minimum
sufficient gain, the supply voltage must be at least a couple time fsT = V T (VT= the thermal
voltage =25 mV at room temperature). Below this voltage, thermal noise becomes an issue and
the circuit becomes unreliable.
 43

1.8 STICK DIAGRAMS

Stick diagram are used to convey layer information in a chip before the actual layout. Unlike
Layout diagrams, they need not to be drawn to scale. Colour codes or striped patterns are used
to represent various layers and components in a stick diagram.

Transistors:

A nMOS transistor is formed when a polysilicon stick crosses an N diffusion stick. Similarly, a
pMOS transistor is formed when a polysilicon stick crosses a P diffusion stick as shown in
Figure1.25.

Figure1.25 nMOS and pMOS transistors in stick diagram

Colour codes used in stick diagrams for layers:

Layer Colour
N diffusion Green
P diffusion Yellow/Brown
Polysilicon Red
Metal1 Blue
Contacts & Taps Black
Metal2 Magenta
 44

Figure 1.26 (a) CMOS Inverter (b) Stick diagram of CMOS Inverter using colour codes

Figure1.27 Stick diagram of CMOS inverter using striped pattern codes

Contacts are represented by small black squares.Figure1.26 and 1.27 show the stick diagram for a
CMOS inverter using color codes and patterns respectively.

1.9 LAYOUT DESIGN RULES

Layouts consist of a set of rectangles on various layers such as diffusion, polysilicon or metal.
The main objective of layout design rules is to build reliably functional circuits in a minimum
possible area. The rules are defined in terms of layer dimensions, spacings, and overlaps.
Width - the minimum width of a rectangle on a particular layer
Spacing - the minimum spacing between two rectangles on the same or different
layers
Overlap - specifies how much a rectangle must surround another on another layer

Two types of layout design rules exist for industrial and academic applications.
Industrial design rules are usually specified in microns. Universities use scalable design rules.
Mead and Conway (1980) proposed scalable design rules based on a single parameter called λ.
channel length( L )
= L= 2 λ
2
In a λ-based design, all dimensions are expressed in terms of λ. The advantage of λ based
design is that, an existing layout can be re-used for a new process by simply changing the λ
value. The value of λ is generally specified in terms of microns. It is nothing but the width of the
poly silicon layer.
 45

In CMOS fabrication, a process is generally described by its feature size, which is the
minimum transistor length (L). So, λ is half the feature size. For example, a 360 nm process has a
minimum poly silicon width (and hence transistor length) of 0.36μm. For this process, λ =
0.18μm. In a layout, pMOS transistors are generally made wider than nMOS transistors due to
the low mobility of holes. This will ensure that they deliver the same current as nMOS.

Advantages of λ-based rules:-

• scalability
• simple

1.9.1 MOSIS design rules

The MOSIS is a prototyping service that collects designs customers and combines them onto one
mask set. They have developed a set of scalable lambda-based design rules that covers a wide
range of manufacturing processes. These rules describe
• the minimum width to avoid breaks in a line
• minimum spacing to avoid shorts between lines
• minimum overlap to ensure that two layers completely overlap

MOSIS Design rules for layouts in an n-well process are described below and also shown
diagrammatically in Figure 1.28.
 46

Figure1.28 MOSIS λ-based design rules

1. Metal and diffusion have minimum width and spacing of 4λ .

2. Polysilicon uses a width of 2 λ
3. Polysilicon overlaps diffusion by 2 λ where a transistor is desired and has a spacing
of 1 λ away where no transistor is desired.
4. Contacts are 2 λ × 2 λ and must be surrounded by 1 λ on the layers above and below.
5. Polysilicon and contacts have a spacing of 3 λ from other polysilicon or contacts.
6. N-well surrounds pMOS transistors by 6 λ and avoids nMOS transistors by 6 λ.

1.9.2 Layout of CMOS inverter

Figure 1.41(a) shows a CMOS inverter and its layout. The numbers near the transistors specify
the dimensions of their Width/Length (W/L) ratio. The nMOS transistor in this example has a
W/L ratio of 4/2. This is the minimum dimension and is sometimes called as 1 unit. Such a
minimum-width contacted transistor is often called a unit transistor. In a 0.6  m process, this

corresponds to an actual width of 1.2  m and a length of 0.6  m .

 47

Figure 1.29 a)CMOS inverter (b) inverter layout (c) Layout with substrate tap

The inverter layout consists of four horizontal strips:

• metallic layer for the ground
• n-diffusion
• p-diffusion
• metallic layer for VDD.

The power and the ground lines are usually called supply rails. Polysilicon lines run
vertically to form transistor gates. The input A can be connected from the top, bottom, or left in
polysilicon. The output Y is available at the right side of the cell in a metal layer. It is required to
connect the p-substrate to ground and n-well to VDD. These connections are also shown.

Example: Layout of 3-input NAND gate:

Figure1.30 (a)3-input CMOS NAND gate (b) Layout

Figure 1.30 shows a three input NAND gate and the corresponding layout. All nMOS transistors
are connected in series while pMOS transistors are connected in parallel.