CHAPTER 4:

Combinational Logic
• Use the Boolean Algebra and the
minimization techniques to design useful
circuits
• No feedback, no memory
• Just n inputs, m outputs and an arbitrary truth
table
 Analysis Procedure
• We need to analyze digital circuits to verify
our designs (as well as understand designs
without documentation)
• Assume we have the logic diagram (and
some minimal info about the inputs)
 Steps in Analysis
• Label all the outputs of the gates that are
connected directly to the inputs with (short)
arbitrary names
• Label all the outputs of the gates that are
connected directly to the previous set
• Repeat till all gates are done.
 Symbolic Manipulation
• Substitute symbolically till all intermediate
symbols are gone
• Build the truth table
• HDL compiler packages have good tools to
speed this up
 Design
• The purpose is to translate a high level
description of the circuit to a logic diagram
or something that is directly implementable
• Normally we are expected to minimize some
cost measure
 Design Procedure
• Give short names to all inputs and outputs
• Derive truth table from the specification
• Simplify
• Draw diagram
 HDLs
• The first two steps cannot be handled by
HDLs
– but the compiler packages provide tools
– there are libraries that can be reused or modified
• The other two are handled very well by
HDLs
 Example: BCD-Exc3
• We design a converter from BCD to Excess-
3
• Excess-3 is essentially BCD+3
Truth Table
ABCD wxyz
0000 0011
0001 0100
0010 0101
0011 0110
0100 0111
0101 1000
0110 1001
0111 1010
1000 1011
1001 1100
1010 xxxx
1011 xxxx
1100 xxxx
1101 xxxx
1110 xxxx
1111 xxxx
 Handicraft...
• The boolean expressions are
– w = A + BC + BD = A + B(C + D)
– x = B’C + B’D + BC’D’=B’(C+D)+B(C+D)’
– y = CD + C’D’ = CD + (C+D)’
– z = D’
• Notice that (C+D) and its negation appear 4
times
 Half Adder
• 2 inputs, 2 outputs
• So simple that can be done without maps etc
– S = x’y + xy’
– C = xy
Half Adder Truth Table

xy CS

00 00
01 01
10 01
11 10
 Full Adder
• A bit more interesting
• Adds 3 bits (2 bits plus a carry-in)
• Produces 2 outputs
• Needs maps
Full Adder Truth Table

xyz CS

000 00
001 01
010 01
011 10
100 01
101 10
110 10
111 11
 Decoder
• A standard and quite useful MSI chip
• Has n input and 2^n outputs
• The output with number that corresponds to
the binary value of the input is high and the
rest are low
• Produces all the minterms
 Enable pin
• Decoders usually have an ENABLE pin
• Very often ENABLE pins have negative
logic (active low)
• Without the ENABLE one of the decoder
outputs is always true
 Many uses
• The main advantage of the ENABLE is that
it allows us to build big decoders out of
smaller ones.
• E.g. build a 4x16 decoder out of two 3x8 and
a 1x2.
 Combinational Logic
• Decoders produce all the minterms
• So can be used to implement functions
• Very good for hard to minimize functions
• Very good for MSI-SSI implementations
MULTIPLEXERS
Combinational Logic using MUX
• Really useful things for implementing
complex logic
• When the MSIs ruled the world, MUXes
were kings
 General Procedure
• The simplest way to design a combinational
circuit with N inputs is to use an N x (2^N)
MUX
– Connect the inputs to the control inputs
– Assign 1 to the data inputs that correspond to the
minterms, zero o/w
 Too simple...
• Too simple to be mentally satisfying
• We could use a smaller MUX and very little
other hardware (or have more inputs)
 General Procedure
• Assign the N control inputs of the MUX to
the first N inputs to the circuit we want to
design
• Separate the truth table to 2^N blocks
• Treat each block as an individual truth table
and minimize it
 Advantages
• We can implement efficiently quite large
combinational circuits
– with a 16x4 MUX we can implement a 10 input
circuit using nothing but maps.
• Can attempt to minimize further by assigning
different inputs to the control inputs of the
MUX
 Disadvantages
• It is not always a standard form (AND-OR
or OR-AND)
• The advantages are less significant if we do
not use MSI
 Combinational Circuits
Encoders
 An encoder is a digital circuit that performs the inverse
operation of a decoder.
 An encoder has 2n (or fewer) input lines and n output lines.
The output lines, as an aggregate, generate the binary code
corresponding to the input value.
 An example of an encoder is the octal-to-binary encoder
whose truth table is given in Table 4.7.
 It has eight inputs (one for each of the octal digits) and three
outputs that generate the corresponding binary number
Combinational Circuits
 Combinational Circuits
 The encoder defined in Table 4.7 has the limitation that only
one input can be active at any given time. If two inputs are
active simultaneously, the output produces an undefined
combination.
 For example, if D3 and D6 are 1 simultaneously, the output
of the encoder will be 111 because all three outputs are equal
to 1. The output 111 does not represent either binary 3 or
binary 6.
 To resolve this ambiguity, encoder circuits must establish an
input priority to ensure that only one input is encoded. If we
establish a higher priority for inputs with higher subscript
 Combinational Circuits
numbers, and if both D3 and D6 are 1 at the same time, the
output will be 110 because D6 has higher priority than D3.
 Another ambiguity in the octal-to-binary encoder is that an
output with all 0’s is generated when all the inputs are 0; but
this output is the same as when D0 is equal to 1. The
discrepancy can be resolved by providing one more output
to indicate whether at least one input is equal to 1
 Combinational Circuits
Priority Encoder
 A priority encoder is an encoder circuit that includes the
priority function.
 The operation of the priority encoder is such that if two or
more inputs are equal to 1 at the same time, the input having
the highest priority will take precedence.
 The truth table of a four-input priority encoder is given in
Table 4.8.
 Combinational Circuits

 In addition to the two outputs x and y, the circuit has a third

output designated by V; this is a valid bit indicator that is set
to 1 when one or more inputs are equal to 1.
 Combinational Circuits
 If all inputs are 0, there is no valid input and V is equal to 0.
The other two outputs are not inspected when V equals 0
and are specified as don’t-care conditions.
 According to Table 4.8, the higher the subscript number, the
higher the priority of the input.
 Input D3 has the highest priority, so, regardless of the values
of the other inputs, when this input is 1, the output for xy is
11 (binary 3). D2 has the next priority level. The output is 10
if D2 = 1, provided that D3 = 0, regardless of the values of
the other two lower priority inputs. The output for D1 is
generated only if higher priority inputs are 0, and so on down
the priority levels.
 Combinational Circuits

 The maps for simplifying outputs x and y are shown in Fig.

4.22.
 Although the table has only five rows, when
each X in a row is replaced first by 0 and then by 1, we
obtain all 16 possible input combinations.
 Combinational Circuits
 For example, the fourth row in the table, with inputs XX10,
represents the four minterms 0010, 0110, 1010, and 1110.
 HDL Models of Combinational Circuits
 Verilog allows the designer to describe a module in one of
three ways:
Gate-level (using primitive and built-in and UDPs)-
describes a circuit by specifying its gates and how they
are connected with each other.
Dataflow modeling (using keyword assign)- is used
mostly for describing the Boolean equations of
combinational logic
Behavioral modeling (using keyword always)- is
used to describe combinational and sequential circuits
at a higher level of abstraction.
 HDL Models of Combinational Circuits
1. Gate-Level Modeling
 In this type of representation, a circuit is specified by its
logic gates and their interconnections.
 Gate level modeling provides a textual description of a
schematic diagram.
 The Verilog HDL includes 12 basic gates as predefined
primitives.
 Four of these primitive gates are of the three-state type.
 The other eight are all declared with the lowercase keywords
and, nand, or, nor, xor, xnor, not, and buf.
 The Verilog language includes a functional description of
each type of gate, too.
 HDL Models of Combinational Circuits
 When the gates are simulated, the simulator assigns one
value to the output of each gate at any instant.
 We now present two examples of gate-level modeling.
They use identifiers having multiple bit widths, called
vectors.
 The syntax specifying a vector includes within square
brackets two numbers separated with a colon. The
following Verilog statements specify two vectors:
output [0: 3] D;
 Declares an output vector D with four bits, 0 through 3
wire [7: 0] SUM;
 HDL Models of Combinational Circuits
 Declares a wire vector SUM with eight bits numbered 7
through 0.
 The individual bits are specified within square brackets, so
D [2] specifies bit 2 of D. It is also possible to address parts
(contiguous bits) of vectors. For example, SUM [2: 0]
specifies the three least significant bits of vector SUM.
 Example 4.1 shows the gate-level description of a 2-4-line
decoder. It has two data inputs A and B and an enable input
E. The four outputs are specified with the vector D.
 The wire declaration is for internal connections. Three not
gates produce the complement of the inputs, and four nand
gates provide the outputs for D.
 HDL Models of Combinational Circuits

 This example describes the decoder of Fig. 4.19 below

 HDL Models of Combinational Circuits

Nested Modules
 Two or more modules can be combined to build a
hierarchical description of a design.
 A module can instantiate other modules. Instantiation
means allocation of needed hardware
HDL Models of Combinational Circuits
HDL Models of Combinational Circuits
HDL Models of Combinational Circuits
 HDL Models of Combinational Circuits
2. Dataflow Modeling
 Dataflow modeling of combinational logic uses a
number of operators that act on binary operands to
produce a binary result.
 Verilog HDL provides about 30 different operators.
 HDL Models of Combinational Circuits

 Dataflow modeling uses continuous assignments and the

keyword assign. A continuous assignment is a statement
that assigns a value to a net.
HDL Models of Combinational Circuits
HDL Models of Combinational Circuits
 HDL Models of Combinational Circuits
 The next example uses the conditional operator (? :). This
operator takes three operands:

 The condition is evaluated. If the result is logic 1, the true

expression is evaluated and used to assign a value to the
left-hand side of an assignment statement. If the result is
logic 0, the false expression is evaluated
 HDL Example 4.6 describes a two-to-one-line multiplexer
using the conditional operator. The continuous assignment
 HDL Models of Combinational Circuits

3. Behavioral Modeling
 Behavioral modeling represents digital circuits at a
functional and algorithmic level.
 It is used mostly to describe sequential circuits, but can
also be used to describe combinational circuits.
 HDL Models of Combinational Circuits
 Uses the keyword always and C-like procedural
assignments (blocking) to entities of type reg
 HDL Example 4.7 shows the behavioral description of a
two-to-one-line multiplexer.
 Since variable m_out is a target output, it must be
declared as reg data (in addition to the output
declaration).
 HDL Models of Combinational Circuits

 The procedural assignment statements inside the always

block are executed every time there is a change in any of
the variables listed after the @ symbol. (Note that there
is no semicolon (;) at the end of the always statement.)
 In this case, these variables are the input variables A, B,
and select. The statements execute if A, B, or select
 HDL Models of Combinational Circuits
changes value. Note that the keyword or, instead of the
bitwise logical OR operator “|”, is used between
variables. The conditional statement if–else provides a
decision based upon the value of the select input.
 The if statement can be written without the equality
symbol:
 HDL Models of Combinational Circuits
Writing a Simple Test Bench
 A test bench is an HDL program used for describing and
applying a stimulus to an HDL model of a circuit in order
to test it and observe its response during simulation
 In addition to employing the always statement, test
benches use the initial statement to provide a stimulus to
the circuit being tested.
 The initial statement executes only once, starting from
simulation time 0, and may continue with any operations
that are delayed by a given number of time units, as
specified by the symbol #.
 HDL Models of Combinational Circuits
For example, consider the initial block

 The block is enclosed between the keywords begin and

end. At time 0, A and B are set to 0. Ten time units
later, A is changed to 1. Twenty time units after that (at
t =30), A is changed to 0 and B to 1.
 Inputs specified by a three-bit truth table can be
generated with the initial block:
 HDL Models of Combinational Circuits

 When the simulator runs, the three-bit vector D is

initialized to 000 at time 0. The keyword repeat specifies
a looping statement: D is incremented by 1 seven times,
once every 10 time units.
 The result is a sequence of binary numbers from 000 to 111
 HDL Models of Combinational Circuits

 A test module is written like any other module, but it

typically has no inputs or outputs. The signals that are
applied as inputs to the design module for simulation are
declared in the stimulus module as local reg data type.
 HDL Models of Combinational Circuits
 The outputs of the design module that are displayed for
testing are declared in the stimulus module as local wire
data type.
 The module under test is then instantiated, using the local
identifiers in its port list.
Figure 4.34 clarifies this relationship.
HDL Models of Combinational Circuits
 HDL Models of Combinational Circuits
 The response to the stimulus generated by the initial and
always blocks will appear in text format as standard output
and as waveforms (timing diagrams) in simulators having
graphical output capability
 These are built-in system functions that are recognized by
keywords that begin with the symbol $. Some of the system
tasks that are useful for display are:
 HDL Models of Combinational Circuits
 The format specification uses the symbol % to specify the
radix of the numbers that are displayed and may have a string
enclosed in quotes ().
 The base may be binary, decimal, hexadecimal, or octal,
identified with the symbols %b, %d, %h, and %o,
respectively (%B, %D, %H, and %O are valid too). For
example, the statement
$display ("%d %b %b", C, A, B);
specifies the display of C in decimal and of A and B in
binary
Example
 HDL Models of Combinational Circuits
 An example of a stimulus module is shown in HDL
Example 4.9. The circuit to be tested is the two-to-one-line
multiplexer described in Example 4.6. The module
t_mux_2x1_df has no ports.
 The inputs for the mux are declared with a reg keyword
and the outputs with a wire keyword. The mux is
instantiated with the local variables.
 The output response is checked with the $monitor system
task. Every time a variable in its argument changes value,
the simulator displays the inputs, output, and time.
 The result of the simulation is listed under the simulation
log in the example. It shows that m_out=A when select=1
and m_out=B when select=0 verifying the operation of
the multiplexer.
HDL Models of Combinational Circuits
HDL Models of Combinational Circuits
 HDL Models of Combinational Circuits
EXAMPLE: For the circuit Fig. 4.2, write the gate-level
description of circuit and a stimulus to analyze the circuit
 HDL Models of Combinational Circuits
 The description of the circuit follows the interconnections
between the gates according to the schematic diagram of
Fig. 4.2.
 The stimulus for the circuit is listed in the second module.
The inputs for simulating the circuit are specified with a
three-bit reg vector D. D[2] is equivalent to input A, D[1]
to input B, and D[0] to input C. The outputs of the circuit
F1 and F2 are declared as wire.
 The repeat loop provides the seven binary numbers after
000 for the truth table. The result of the simulation
generates the output truth table displayed with the
example. The truth table listed shows that the circuit is
a full adder.
HDL Models of Combinational Circuits
HDL Models of Combinational Circuits
 Assignment 4
From our core reference material (Digital
Design With an Introduction to the Verilog
HDL by M. Morris Mano and Michael D.
Ciletti) attempt the following questions: 4.2,
4.4, 4.6, 4.22, 4.26, 4.27, 4.32, 4.35, 4.42,
4.43