INSTRUCTION SET OF 8088/8086

COURSE CODE: CS-430

COURSE TITLE: MICROPROCESSOR PROGRAMMING AND INTERFACING
PREPARED BY: DR. SYED AQEEL HAIDER
REVIEW OF PREVIOUS LECTURE

◼ Addressing Modes of Instructions

◼ Data Addressing Modes
◼ Program Memory Addressing Modes
◼ Stack Memory Addressing Mode
◼ Assembly to Machine Language Conversion
TO BE COVERED

◼ Introduction to Instruction Set of 8088/8086 Microprocessor

◼ Group of Instructions
◼ Data Transfer Group of Instructions
◼ Arithmetic and Logic Instructions
INSTRUCTION SET OF 8088/8086

◼ The instruction set of a microprocessor defines the basic operations that a programmer can make the
device perform.
◼ The instruction set of 8088/8086 microprocessor has 117 basic instructions.
◼ The wide range of operands and addressing modes permitted for use with these instructions
executable at the machine code level.
GROUPS OF INSTRUCTIONS

◼ The instruction set can be divided into a number of groups of functionally related
instructions.
◼ Data Transfer Group of Instructions
◼ Arithmetic and Logic Group of Instructions
◼ Transfer of Control Group of Instructions
DATA TRANSFER GROUP

◼ Data Transfer Instructions

◼ Isolated I/O Instructions
◼ Stack Operation Instructions
◼ String Data Transfer Instructions
ARITHMETIC AND LOGIC GROUP

◼ Arithmetic Instructions
◼ Logic Instructions
◼ Compare and Test Instructions
◼ Multiplication Instructions
◼ Division Instructions
◼ BCD and ASCII Arithmetic Instructions
◼ Rotate Instructions
◼ Shift Instructions
◼ Flag Control Instructions
TRANSFER OF CONTROL GROUP

◼ Jump Instructions
◼ Subroutine Handling Instructions
◼ Loop Handling Instructions
DATA TRANSFER INSTRUCTIONS

D S Examples:
• MOV AX , DI; (AX) 🡨 (DI)
REG REG
• MOV DL , CH; (DL) 🡨 (CH)
REG MEM
• MOV AX , [BX]; (AX) 🡨 (DS:[BX])
MEM REG
◼ MOV D , S • MOV [DI] , DX; (DS:[DI]) 🡨 (DX)
MEM IMM
(D) 🡨 (S) • MOV WORDPTR[BP] , 3Ch; (SS:[BP]) 🡨 003Ch
REG IMM
No Flags affected • MOV DI , 9F60h; (DI) 🡨 9F60h
ACC MEM
• MOV AX , WD2; (AX) 🡨 (DS: WD2)
MEM ACC • MOV BT2 , AL; (DS:BT2) 🡨 (AL)
SEG REG • MOV DS , DX; (DS) 🡨 (DX)
SEG MEM • MOV ES , [DI+40h]; (ES) 🡨 (DS:[DI+40h])
REG SEG • MOV DI , SS; (DI) 🡨 (SS)
MEM SEG • MOV [SI+50h] , CS; (DS:[SI+50h]) 🡨 (CS)
DATA TRANSFER INSTRUCTIONS

◼ XCHG OP1 , OP2 OP1 OP2 Examples:

(OP1) 🡨🡨 (OP2) REG8 REG8 XCHG AX , DI; (AX) 🡨🡨 (DI)
No Flags affected REG16 REG16 XCHG DL , CH; (DL) 🡨🡨 (CH)
REG MEM XCHG AX , [BX]; (AX) 🡨🡨 (DS:[BX])
MEM REG XCHG [DI] , DX; (DS:[DI]) 🡨🡨 (DX)
DATA TRANSFER INSTRUCTIONS

DS*10h + BX + 8 D6
DS*10h + BX + 7 38
DS*10h + BX + 6 15
DS*10h + BX + 5 2E
◼ XLAT
DS*10h + BX + 4 9B
(AL) 🡨 (DS:[BX+AL]) or
DS*10h + BX + 3 56
(AL) 🡨 (DS*10h+BX+AL)
DS*10h + BX + 2 D4
DS*10h + BX + 1 3C
DS*10h + BX + 0 45
:
:
DS*10h
DATA TRANSFER INSTRUCTIONS

◼ LEA REG16 , MEM

(REG16) 🡨 Offset address of MEM WD1 DW 3050h
Offset of WD1 is 7080h
Example:
LEA DX , WD1;
DS*10h+WD1+1 30
(DX) 🡨 7080h
DS*10h + WD1 50
:
DS*10h
DATA TRANSFER INSTRUCTIONS

◼ LDS REG16 , MEM D6 02

(REG16) 🡨 (MEM), (DS) 🡨 (MEM+2) 38 78
◼ LES REG16 , MEM 2E 3C
(REG16) 🡨 (MEM), (ES) 🡨 (MEM+2) DS*10h + BX + 43 4F SS*10h + BP + 23 8D
Examples: DS*10h + BX + 42 C3 SS*10h + BP + 22 92

◼ LDS AX , [BX+40h] DS*10h + BX + 41 5A SS*10h + BP + 21 5F

DS*10h + BX + 40 F2 SS*10h + BP + 20 30
(AX) 🡨 5AF2h, (DS) 🡨 4FC3h
: :
◼ LES DX , [BP+20h]
: :
(DX) 🡨 5F30h, (ES) 🡨 8D92h
DS*10h SS*10h
ISOLATED I/O INSTRUCTIONS

ACC PT
◼ IN ACC , PT
AL P8 Fixed
(ACC) 🡨 Data present at input port ‘PT’
AX P8 Address
◼ OUT PT , ACC
AL DX Variable
Data appear at output port ‘PT’ 🡨 (ACC) Address
AX DX
Examples: (Fixed Addressed Isolated I/O)
IN AL , 80h ; From input port ’80h’ a byte is read/inputted into ‘AL’
IN AX , 80h ; From input port ’80h’ a word is read/inputted into ‘AX’
OUT 60h , AL ; From ‘AL’ a byte is written/outputted at port ‘60h’
OUT 60h , AX ; From ‘AX’ a word is written/outputted at port ‘60h’
ISOLATED I/O INSTRUCTIONS

Examples: (Variable Addressed Isolated I/O)

IN AL , DX ; From input port ’DX’ a byte is read/inputted into ‘AL’
IN AX , DX ; From input port ’DX’ a word is read/inputted into ‘AX’
OUT DX , AL ; From ‘AL’ a byte is written/outputted at port ‘DX’
OUT DX , AX ; From ‘AX’ a word is written/outputted at port ‘DX’
STACK OPERATION INSTRUCTIONS

S16 / D16
REG16
◼ PUSH S16 ; (SS:[SP – 1]) 🡨 (S15-8) , (SS:[SP – 2]) 🡨 (S7-0) , (SP) 🡨 (SP) – 2.
MEM16
◼ POP D16 ; (D7-0) 🡨 (SS:[SP]) , (D15-8) 🡨 (SS:[SP+1]) , (SP) 🡨 (SP) + 2.
SEG
◼ DETAILED DISCUSSION IN LECTURE # 9.
IMM(not for POP & not
available for 8088/8086)
FLAG
ALL
STACK OPERATION INSTRUCTIONS

Examples:
◼ PUSH AX; ((SP)-1)🡨(AH), ((SP)-2)🡨(AL), (SP)🡨(SP)-2.
◼ PUSH [BX]; ((SP)-1)🡨(DS:[BX+1]), ((SP)-2)🡨(DS:[BX]), (SP)🡨(SP)-2.
◼ PUSH DS; ((SP)-1)🡨(DSH), ((SP)-2)🡨(DSL), (SP)🡨(SP)-2.
◼ PUSHF; ((SP)-1)🡨(FLH), ((SP)-2)🡨(FLL), (SP)🡨(SP)-2.
◼ POP DX; (DL)🡨((SP)), (DH)🡨((SP)+1), (SP)🡨(SP)+2.
◼ POP [BP]; (SS:[BP])🡨((SP)), (SS:[BP]+1)🡨((SP)+1), (SP)🡨(SP)+2.
◼ POPF; (FLL)🡨((SP)), (FLH)🡨((SP)+1), (SP)🡨(SP)+2.
◼ POP ES; (ESL)🡨((SP)), (ESH)🡨((SP)+1), (SP)🡨(SP)+2.
STRING DATA TRANSFER INSTRUCTIONS

◼ LODSB ; (AL) 🡨 (DS:[SI]) , (SI) 🡨 (SI)+1

◼ LODSW ; (AX) 🡨 (DS:[SI]) , (SI) 🡨 (SI)+2
◼ STOSB ; (ES:[DI]) 🡨 (AL) , (DI) 🡨 (DI)+1
◼ STOSW ; (ES:[DI]) 🡨 (AX) , (DI) 🡨 (DI)+2
◼ MOVSB ; (ES:[DI]) 🡨 (DS:[SI]) , (SI) 🡨 (SI)+1, (DI) 🡨 (DI)+1
◼ MOVSW ; (ES:[DI]) 🡨 (DS:[SI]) , (SI) 🡨 (SI)+2, (DI) 🡨 (DI)+2
◼ INSB ; (ES:[DI]) 🡨 Byte from input port ‘DX’ , (DI) 🡨 (DI)+1
◼ INSW ; (ES:[DI]) 🡨 Word from input port ‘DX’ , (DI) 🡨 (DI)+2 Available in 32-bit
◼ OUTSB ; Byte at output port ‘DX’ 🡨 (DS:[SI]) , (SI) 🡨 (SI)+1 microprocessors

◼ OUTSW ; Word at output port ‘DX’ 🡨 (DS:[SI]) , (SI) 🡨 (SI)+2

STRING DATA TRANSFER INSTRUCTIONS
:
ES*10h + DI + 3
ES*10h + DI + 2
Example: ES*10h + DI + 1
◼ MOV CX, 05h ; Count of 05h is initialized ES*10h + DI
:
◼ CLD ; (DF) 🡨 0
ES*10h
◼ MOV SI , 2000h
:
◼ MOV DI , 3000h
DS*10h + SI + 3
◼ REP MOVSB ; Repeat until [(CX)-1 ] = 0 DS*10h + SI + 2
DS*10h + SI + 1
4
2
5
CX = 3 3
1
4
1–1=2
0 DS*10h + SI
:
DS*10h
 ARITHMETIC INSTRUCTIONS

◼ ADC*/ADD OP1 , OP2

(OP1) 🡨 (OP1) + (OP2) + CF*
Examples:
All Status Flags are affected
• ADD DX , DI; (DX) 🡨 (DX)+(DI)
• ADC BL , CH; (BL) 🡨 (BL)+(CH)+CF
OP1 OP2 • ADD AX , [SI]; (AX) 🡨 (AX)+(DS:[SI])
REG REG • ADC [DI] , DX; (DS:[DI]) 🡨 (DS:[DI])+(DX)+CF
REG MEM • ADD WORDPTR[BP] , 3Ch; WORD(SS:[BP]) 🡨 WORD(SS:[BP])+003Ch
MEM REG • ADC SP , 9F60h; (SP) 🡨 (SP)+9F60h+CF

MEM IMM • ADD AX , NUM1; (AX) 🡨 (AX)+45D0h

REG IMM
Where NUM1 EQU 45D0h
ACC IMM
ARITHMETIC INSTRUCTIONS

◼ Example for Add with Carry (ADC) B 4 C 9

Q: Add ‘5F85B4C9h’ with ‘6DA4C280h’ in 8088/8086 microprocessor: C 2 8 0 +
7 7 4 9 ; CF = 1
MOV AX , B4C9h
5 F 8 5
ADD AX , C280h 6 D A 4 +
MOV DX , 5F85h C D 2 A ; CF = 0
ADC DX , 6DA4h
ARITHMETIC INSTRUCTIONS

◼ SBB*/SUB OP1 , OP2

(OP1) 🡨 (OP1) – (OP2) – CF*
Examples:
All Status Flags are affected
• SUB SI , CX; (SI) 🡨 (SI)-(CX)
• SBB DH , CH; (DH) 🡨 (DH)-(CH)-CF
OP1 OP2
• SUB SP , [SI]; (SP) 🡨 (SP)-(DS:[SI])
REG REG • SBB [DI] , AL; (DS:[DI]) 🡨 (DS:[DI]-(AL)-CF
REG MEM • SUB WORDPTR[BP] , 100; WORD(SS:[BP]) 🡨 WORD(SS:[BP])-0064h
MEM REG • SBB BX , 0F560h; (BX) 🡨 (BX)-F560h-CF
MEM IMM • SUB AL , NUM1; (AL) 🡨 (AL)-D5h

REG IMM
Where NUM1 EQU D5h
ACC IMM
ARITHMETIC INSTRUCTIONS

◼ Example for Subtract with Borrow (SBB) B 4 C 9

Q: Subtract ‘6DA4C280’ from ‘5F85B4C9h’ in 8088/8086 microprocessor: C 2 8 0 -
F 2 4 9 ; CF = 1
MOV AX , B4C9h
5 F 8 5
SUB AX , C280h 6 D A 4 -
MOV DX , 5F85h F 1 E 0 ; CF = 1
SBB DX , 6DA4h
ARITHMETIC INSTRUCTIONS

◼ INC/DEC/NEG OP
(OP) 🡨 (OP) + 1 Examples:
(OP) 🡨 (OP) - 1 • INC SI; (SI) 🡨 (SI) + 1
(OP) 🡨 0 - (OP) • DEC DH; (DH) 🡨 (DH) - 1
• NEG BT1; BT1 🡨 0 - (DS:BT1)
Status Flags are affected
• INC WD1; WD1 🡨 WD1 + 1
OPERAND (OP) • DEC BYTEPTR [DI]; BYTE(DS:[DI]) 🡨 BYTE(DS:[DI] -1
• NEG WORDPTR [BP+40h] ; WORD(SS:[BP+40h]) 🡨 0 - WORD(SS:[BP+40h])
REG8
REG16
Where BT1 DB 5Dh
MEM WD1 DW 13F0h
 LOGIC INSTRUCTIONS

◼ AND/OR/XOR OP1 , OP2

(OP1) 🡨 (OP1) . / + / + (OP2)
Examples:
All Status Flags are affected
• AND DX , DI; (DX) 🡨 (DX) . (DI)
• OR BL , CH; (BL) 🡨 (BL) + (CH)
OP1 OP2 • XOR AX , [SI]; (AX) 🡨 (AX) +(DS:[SI])
REG REG • AND [DI] , DX; (DS:[DI]) 🡨 (DS:[DI]) . (DX)
REG MEM • OR WORDPTR[BP] , 3Ch; WORD(SS:[BP]) 🡨 WORD(SS:[BP]) + 003Ch
MEM REG • XOR SP , 9F60h; (SP) 🡨 (SP) +9F60h

MEM IMM • AND AX , NUM1; (AX) 🡨 (AX) . 45D0h

REG IMM
Where NUM1 EQU 45D0h
ACC IMM
LOGIC INSTRUCTIONS
Q. Given (AX) = E68Ah, choose the correct logic operation for the following:
MASK AX YAND YOR YXOR
1. Bit 5,6 and 8 are to be set
0 0 0 0 0
2. Bit 3, 10 and 11 are to be reset
0 1 0 1 1
3. Bit 2, 14 and 15 are to be complemented
1 0 0 1 1
Solution:
1 1 1 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 0 1 1 0 1 0 0 0 1 0 1 0 AX
0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 OR MASK
1 1 1 0 0 1 1 1 1 1 1 0 1 0 1 0 AX
1 1 1 1 0 0 1 1 1 1 1 1 0 1 1 1 AND MASK
1 1 1 0 0 0 1 1 1 1 1 0 0 0 1 0 AX
1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 XOR MASK
0 0 1 0 0 0 1 1 1 1 1 0 0 1 1 0 AX
 LOGIC INSTRUCTIONS

◼ NOT OP
(OP) 🡨 1s of complement of (OP)
Examples:
All Status Flags affected
• NOT SI; (SI) 🡨 1s complement of (SI)
• NOT DH; (DH) 🡨 1s complement of (DH)
OP • NOT BT1; (DS:BT1) 🡨 1s complement of (DS:BT1)
REG8 • NOT WD1; (DS:WD1) 🡨 1s complement of WD1
• NOT BYTEPTR [DI]; BYTE(DS:[DI]) 🡨 1s complement of BYTE(DS:[DI])
REG16
• NOT WORDPTR [BP+40h] ; WORD(SS:[BP+40h]) 🡨 1s complement of WORD(SS:[BP+40h])
MEM
Where BT1 DB 5Dh
WD1 DW 13F0h
COMPARE AND TEST INSTRUCTIONS

◼ CMP / TEST OP1 , OP2

Examples:
(OP1) – (OP2) will affect status flags
• CMP SI , DI; Status flags updated after (SI) - (DI)
(OP1) . (OP2) will affect status flags • TEST DH , CH; Status flags updated after (DH) . (CH)
• CMP SP , [SI]; Status flags updated after (SP) - (DS:[SI])
OP1 OP2 • TEST [DI] , AL; Status flags updated after (DS:[DI] . (AL)
• CMP WORDPTR[BP] , 100; Status flags updated after WORD(SS:[BP]) - 0064h
REG REG
• TEST BX , 0F560h; Status flags updated after (BX) . F560h
REG MEM
• CMP AL , NUM1; Status flags updated after (AL) - 5Dh
MEM REG
MEM IMM Where NUM1 EQU 5Dh
REG IMM
ACC IMM
THANK YOU