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POWER AND AREA EFFICIENT 10T SRAM WITH IMPROVED READ STABILITY

Article in ICTACT Journal on Microelectronics · April 2017

DOI: 10.21917/ijme.2017.0059

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ISSN: 2395-1680 (ONLINE) ICTACT JOURNAL ON MICROELECTRONICS, APRL 2017, VOLUME: 03, ISSUE: 01
DOI: 10.21917/ijme.2017.0059

POWER AND AREA EFFICIENT 10T SRAM WITH IMPROVED READ STABILITY
T.S. Geethumol, K.S. Sreekala and P.B. Dhanusha
Department of Electronics and Communication Engineering, Saintgits College of Engineering, India

Abstract The ultimate goal of this work is to improve the read stability
In this paper, a 10T Static Random Access Memory bit cell is proposed and power consumption. Thus an alternate bit-cell that provides a
to meet design specification for performance, stability, area and power better trade-off between area, performance, stability and power
consumption. In every state of SRAM cell designs low power and consumption. Our 10T SRAM bit cell is different from existing
increased noise margin plays an important role. The conventional 6T SRAM bit-cell topologies. The proposed 10T SRAM cell uses
SRAM cell is very much prone to noise during read operation. In order transmission gate and stacked transistor. The proposed SRAM
to overcome the Read SNM problem in the 6T SRAM cell designers
does not require pre-charge circuit as required in prior 8T SRAM
have implemented many other SRAM configurations such as 8T, 9T,
10T. These SRAM cell configurations improve the read stability but
cell and sense amplifier circuit as required in 6T SRAM cell. Then
increase the power consumption. We proposed a 10T SRAM cell which we propose a 1-bit SRAM memory array using the proposed 10T
can solve all these problems by introducing the transmission gate and SRAM bit cell which consumes less area than the conventional
using stacking effect in the configuration. In this paper different ones.
SRAM cells analyzed on the basis of power and read stability and we In this paper, we present a comprehensive comparison of the
proposed a 1-bit SRAM memory array using the proposed 10T SRAM proposed 10T SRAM bit cell with the conventional 6T and 8T
bit cell that achieves cell stability, lower power consumption and lesser
SRAM bit cell in terms of Read Static Noise Margin and power
area. The proposed circuit was implemented in Mentor Graphics
Design Architect, simulated using Mentor Graphics ELDO at supply consumption. Then we again compare the proposed 1-bit memory
voltage of 1.8V with the help of TSMC 180nm technology. Micro wind array using the proposed 10T SRAM cell with the conventional
is used to draw layout of SRAM cells and peripherals. 1-bit 6Tand 8T memory array in terms of power consumption and
area.
Keywords: The paper is organized as follows; in section 2 conventional
6T and 8T discussed, then their problems and the method to find
Static Random Access Memory, Static Noise Margin, Read Static Noise
Margin, Power Consumption, 10T SRAM Read Static Noise Margin are also discussed. In section 3 we
discussed about the proposed 10T SRAM cell. In section 4, 1-bit
memory array using the proposed memory cell, conventional 6T
1. INTRODUCTION SRAM cell and Conventional 8T SRAM cells are discussed. In
section 5 we present measured results. Finally, section 6
Currently more than 50% of the area of System-on-Chip summarizes and concludes.
designs is occupied by embedded memory [1]. This is mainly due
to the increased integration of functional blocks which require
large memories for storage and data manipulation. There are many 2. 6T AND 8T SRAM BIT CELL OVERVIEW
important aspects for SRAM cell designs: the cell area, cell
stability and power consumption. The cell area determines about In this section we discussed the conventional 6T and 8T
two third of the chip area and the cell stability determines the soft SRAM bit cells and the method to find Read Static Noise Margin
error rate and the sensitivity of the memory to process tolerances is discussed. The problems with 6T and 8T SRAM cells are also
and operating conditions [2]. discussed in this section.
Power consumption is one of the major concerns of VLSI 2.1 CONVENTIONAL 6T SRAM CELL
circuit designs for which CMOS is the primary technology [3].
Hence, power consumption of the SRAM must be reduced. To The conventional 6T SRAM bit cell is shown in Fig.1. It
achieve higher reliability and longer battery life for portable consists of two cross coupled inverters with two pass transistors
applications, low power cache is necessary. Since SRAM is used connected to complimentary bit-lines (BL and BLB). M1 and M2
in cache memory. Shirked transistor sizes and reduced power are called drivers, M3 and i4 are called the load transistors and
supply voltages lead to lower noise margin. Due to these M5 and M6 are access transistors. The output nodes of inverters
problems, devices more sensitive to noise sources [4]. This (M1 and M3) and (M2 and M4) are called Q and QB respectively.
prevents the scaling of the conventional 6T SRAM bit-cell to The gate of the pass transistors are connected to the Word Line
lower supply voltages and to newer technology. (WL). SRAM cells perform three different operations read, write
SRAM designs thus becomes more challenging if we need and hold operation [6].
low power, high performance fast responding SRAMs. Many The read operation is performed by activating WL and pre-
newer circuitry having larger transistor count i.e. 7T, 8T, 9T, and charging the bit lines to higher voltages. The hold operation is
10T etc. has been implemented. This leads to larger power performed by deactivating BL, BLB and WL. Assume that the cell
consumption. The probability of switching activity factor rises as is originally storing a “1” at node Q. If we wish to write a “0” then
the number of transistor increases and thus consumes larger space. activate WL and then set BL to “0” and BLB is given”1”. It is
The recent published works on dynamic feedback 8T SRAM [5] always not necessary to have two bit lines. The signal and its
improves the write ability not the read stability. inverse are given to improve the noise margin. These bit lines
carry the data from the memory cell to the sense amplifier.

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Fig.1. Conventional 6T SRAM cell

2.2 STATIC NOISE MARGIN (SNM)

Fig.3. Example butterfly curve for SNM during hold and read
Static Noise Margin (SNM) is the maximum static noise that operation [7]
the cell can tolerate, while still maintaining reliable operation [1].
2.3 PROBLEM WITH CONVENTIONAL 6T SRAM
CELL
The conventional 6T SRAM cell shown in Fig.1 is the most
commonly used implementation having the advantage of very less
area [8]. The cells are most vulnerable towards noise during the
read and write operation and causes potential stability problem in
the cell. So the cell structure must be designed properly for read
margin and write margin.
During the read operation, a stored “0” can be overwritten by
a “1” when the voltage at node reaches the threshold voltage of
Fig.2. Standard set up for finding SNM [7] NMOS M1 to pull node Q down to “0” and in turn pull node QB
up even further to “1” due to the mechanism of positive feedback
In Fig.2 DC voltage VN sources are introduced at the internal arising in the structure. This causes wrong data being read or
nodes in the bit-cell. As DC voltage sources increases the stability destructive read when the cell changes state [2].
of the cell changes [7]. The Fig.3 shows the most common way of To increase the RSNM, the potential of the gate electrode
representing the SNM graphically for a bit-cell holding and driver transistor made higher than that of the pass transistor so that
reading data. It plots the Voltage Transfer Characteristic (VTC) the cell ratio becomes higher [8]. Cell ratio [9] is defined as the
of inverter 2 and inverse VTC from inverter 1. The resulting is a transistor strength ratio of the driver transistor to the access
two-lobbed curve called “a butterfly curve” and is used to transistor. There are two techniques to implement such a
determine the SNM. SNM is obtained by finding the length of the relationship either suppress the word line voltage or boost the cell
side of the largest square that can be embedded inside the lobes of VDD level. If we suppress the word-line voltage, the cell current
the butterfly curve [2]. For the best way of understanding this becomes too low to read at the lower VDD boundary due to the
concept, increase the value of VN from “0”. This causes the VTC- suppressed word-line and for the boosted cell VDD, higher power
1 for inverter 1 to move downward and VTC for inverter 2 to move supply for the array cause excessive device reliability and power
towards right [7]. The curves meet at only two points once they also increases. The Cell Ratio should exceed much since it
are moved by the SNM value. The stability of the SRAM cell increases the area of the SRAM memory cell.
mainly depends up on the static noise margin [2]. Cell Ratio is very important parameter during the read
The stability of the SRAM during read operation i.e. Read operation. There is another parameter called pull up ratio which is
Static Noise Margin (RSNM) can be obtained by activating word- mainly considered to achieve the write ability of the cell. Pull up
line and pre-charging BL and BLB to higher voltage. The internal Ratio (PR) is defined as the ratio of the size of the load transistor
node representing a zero gets pulled upward through the access to the access transistor. So we cannot recommend this method in
transistor. This is mainly due to the voltage dividing effect across practical because increasing cell ratio results larger area and the
the access transistor (M5 and M6) and driver transistor (M1 and power consumption also gets increased. SRAM cells must be
M2). This increase in voltage degrades SNM during the read designed properly; otherwise it may change its state during read
operation [7]. and write operation [10].

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2.4 CONVENTIONAL 8T SRAM CELL degrades the logic level “0”. Thus a perfect pass gate is
constructed from the combination of NMOS and PMOS devices
The problem with conventional 6T SRAM cell can be working in a complementary way, leading to improved switching
overcome by using conventional 8T SRAM cell. The major performances. The proposed 10T SRAM cell is shown in Fig.5.
advantage of 8T SRAM cell is that the data nodes are fully
decoupled from read access and due to this the read stability of
the cell is improved. Two NMOS transistors, along with extra read
word-line and read-bit-line, are added to provide separate read
port to the 8T SRAM cell which is shown in Fig.4. The word line
for write is different from the word line read. The read operation
is performed by pre-charging read bit line (RBL) to higher
voltages and by activating read word line (RWL). Thus by doing
this the read stability problem in conventional 6T SRAM cell is
avoided and better read stability is retained in conventional 8T
SRAM cell. The read stack and the use of short local bit lines, the
8T can provide high performance [4].

Fig.5. Proposed 10T SRAM cell

RWLB is the inversion of the signal RWL. It controls the

transistor M9 of the transmission gate. When RWL and RWLB
are asserted, the transmission gate is ON; a stored node is
connected to RBL. The value at node Q is being transferred or
read through RBL. The advantage of this 10T SRAM cell is that
it does not require a pre-charge circuit cells. Hence the stored
value is passed directly through the transmission gate.
Charging/discharging power on the RBL is consumed only
when RBL is changed. Consequently no power is dissipated on
the RBL if an upcoming data is the same as the previous state.
Fig.4. Conventional 8T SRAM cell Thus the proposed design reduces the bit-line power in both cases
that the consecutive “0” and consecutive “1” are read out. The
Write operation is done through write access transistor and read stability of the proposed design is higher than that of others
from the write bit-lines BL and BLB. Read access to the cell is due to the introduction of transmission gate power consumption
through the read access transistor and controlled by the read word- is also reduced due to the introduction of stacking effect.
line, RWL. During the read access the read bit-line, RBL is pre-
charged. The problem with this structure is the higher bit-line 4. SRAM MEMORY SYSTEM FOR WRITING
leakage when the column for read (RBL) is not accessed, the AND READING A SINGLE DATA BIT
leakage current through M7 cause a severe voltage drop at the
read bit-line, leading to larger power consumption and causes In this paper the conventional 6T and 8T SRAM bit cells is
erroneous result at the output [9]. being compared with the proposed design as shown in Fig.5 that
For the 1-bit SRAM memory array implementation pre-charge enhances the data stability by improving the Read Static Noise
circuit, write driver, sense amplifier are needed hence the Margin and also reduces the power consumption. Thus proposed
complexity of the circuit increases and also leads to larger power 10T SRAM cell is being used for making an SRAM memory. For
consumption. So we proposed another 10T SRAM cell which can writing and reading a single data bit, there is a requirement of
solve all these kinds of problems discussed. write driver, pre-charge circuit and sense amplifier in
conventional 6T and 8T SRAM. One of the major advantages of
3. PROPOSED 10T SRAM CELL this proposed design is that it does not necessary to prepare a pre-
charge circuit and sense amplifier circuit in 6T and 8T SRAM
cells because the stored node is directly passed through the
In the proposed 10T SRAM cell, a transmission gate is used
transmission gate. The circuit for writing and reading a single
for read operation and also a pair of NMOS transistors is added in
data bit using the proposed 10T SRAM cell is shown in Fig.6.
each of the pull down path. Thus the sub-threshold leakage current
flowing through a stack of series connected transistors reduces The proposed circuit do not need sense amplifier and pre-
when more than one transistor of the stack is turned off. This charge circuit only write driver is used as peripheral circuit which
effect is known as the “stacking effect” [11].The leakage of a two considerably reduces the number of transistors which in turn
transistor stack is in an order of magnitude less than the leakage reduces the area. Write Enable (WE) of the write driver is
in a single transistor. Thus the power consumption is reduced activated and then data is given into the data pin of the write
considerably due to the stacking effect. Both NMOS devices and driver. Write driver provide data and its compliment BL and BLB
PMOS devices exhibit poor performances when transmitting a which is given to the proposed 10T SRAM cells BL and BLB
particular logic. NMOS degrades the logic level “1” and PMOS pins. The data and its inverse will obtain at Q and QB. For reading

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T.S. GEETHUMOL et al: POWER AND AREA EFFICIENT 10T SRAM WITH IMPROVED READ STABILITY

a data, the transmission gate is turned ON by activating RWL and The pre-charge circuit shown in Fig.9 pre-charges bit lines BL
RWLB. Thus the stored data can be read through RBL. The and BLB to an intermediate voltage between the high and low
schematic of conventional 6T, 8T is shown in Fig.7 and Fig.8. voltages. Before a read operation, signal will arrive to pre-charge
The conventional 6T and 8T SRAM cell has write driver, pre- and equalize the bit-line capacitances. This process is extremely
charge circuit and sense amplifier for reading a single bit. Use of important to ensure that the sense amplifier detects the correct
all these peripherals increases the power consumption. signals from the memory cells. The presence of pre-charge
circuits will help shorten the access time.
When pre-charge logic is “0” then both BL and BLB are
charged to VDD whenever the SRAM cell is in inactive state. For
the active state, pre-charge is made disabled by making it high.
4.1.2 Write Driver:

Fig.6. Block diagram of 10T SRAM cell for reading a single bit

Fig.7. Schematic of 6T SRAM cell for reading a single bit Fig.10. Schematic of write driver circuit

The write driver shown in Fig.10 is designed to write a new

bit to a cell or overwrite an already existing one. The write driver
has two input pins namely the data and write enable signal (WE).
Once the WE goes high the data is pushed into the appropriate
cell. The data and its inverse thus are written into the memory.
This is done by using an inverter. Also the write signal drives two
transmission gates. The write driver must be capable of writing a
voltage value on the bit line. When the WE is deactivated, then
the memory will retains the previously stored data.
Fig.8. Schematic of 8T SRAM cell for reading a single bit
4.1.3 Sense Amplifier:
4.1 PERIPHERAL CIRCUITS
The peripheral circuit for 1-bit memory array includes pre-
charge circuit, write driver and sense amplifier.
4.1.1 Pre-charge Circuit:

Fig.9. Schematic of pre-charge circuit Fig.11. Schematic of Sense amplifier

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Sense amplifier is one of the most prominent building blocks widely acceptable. It is important that the supply voltage must be
of SRAM since it enables the differentiation between logical “0” high for increasing SNM and also for cell stability.
and logical “1” stored in the memory cell. Thus Sense amplifier is
required to detect a small signal appears at the two bit-lines, and to Table.1. READ SNM analysis for supply voltage of 1.8V
amplify it to provide a full swing signal at the bit-lines. Therefore,
it symbolizes an indispensable element to fast access time. SRAM bit Cell Pull up READ
Technology cell Ratio Ratio SNM
Thus the sense amplifier shown in Fig.11 are used to sense
topology (CR) (PR) (mV)
which line is being pulled down and perform the read operation
of the stored data. READ and READBAR are the data stored and 6T 2 0.5 333
its compliment during read operation. 180nm 8T 2 0.5 633
Proposed 10T 2 0.5 666
5. SIMULATION RESULTS AND DISCUSSION
Mentor Graphics ELDO Pyxis Schematic Editor is used for
circuit design and the circuit is analyzed and verified the output
using E-Z wave viewer for functionality through simulations. The
target technology is TSMC 180nm CMOS process. Simulations
are carried out for a supply voltage of 1.8V in order to prove that
proposed design shows better performance for read SNM and
power consumption.

5.1 TRANSIENT ANALYSIS

The write, hold and read operation of the conventional 6T and
8T SRAM cells is shown in Fig.12 to Fig.14. A 1-bit memory
array using conventional 6T and 8T SRAM cells is shown in
Fig.15 to Fig.17. The write, hold and read operations of the
proposed 10T SRAM bit cell and proposed 1-bit memory array is
better than the conventional ones.

Fig.13. Transient analysis wave form of 8T SRAM bit cell

Fig.12. Transient analysis wave form of 6T SRAM bit cell

5.2 READ SNM ANALYSIS

The Read- SNM of the conventional 6T, 8T and proposed has
been simulated for input voltage of 1.8V is shown in Table.1. The
effect of power supply voltage [11] is important parameter which Fig.14. Transient analysis wave form of proposed 10T SRAM
changes the cell stability during read mode operation and has been bit cell

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Fig.17. Transient analysis wave form of proposed 10T SRAM

bit cell

Fig.15. Transient analysis wave form of proposed 6T SRAM bit 5.3 POWER CONSUMPTION ANALYSIS
cell
The existing and proposed bit cells and 1-bit memory array
have been simulated for a supply voltage of 1.8V. The Table.2
shows that the power consumption of proposed 10T SRAM cell
has less power consumption than the existing ones. From Table.3
we can see that the power consumption of proposed 1-bit memory
array using the proposed has remarkably less power consumption
compared to the existing 1-bit SRAM memory array using the 6T
and 8T SRAM bit cells.

Table.2. Power Consumption of different SRAM bit cells

Power Consumption
Technology SRAM topology
(pW)
6T 40.9323
180nm 8T 43.0151
Proposed 10T 21.708

Table.3. Power consumption of different 1-bit memory array

1-bit SRAM memory Power
Technology
array Consumption
6T 133.7634 µW
180nm 8T 144.2718 µW
Proposed 10T 75.8232 pW

Fig.16. Transient analysis wave form of proposed 8T SRAM bit

5.4 AREA ANALYSIS
cell The layout of SRAM cells and peripherals are drawn in micro
wind and the obtained results are tabulated in Table.4 and Table.5.

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From the Table.4, it is seen that the area of proposed 10T SRAM Table.4. Area analysis of different SRAM bit cells
bit cell is 1.8064×6T SRAM bit cell area. For the proposed 1-bit
memory array using the proposed 10T SRAM cell does not need SRAM cells 6T 8T Proposed 10T
pre-charge and sense amplifier. Therefore the area of the proposed Area (µm2 ) 28.1088 1.3934 1.8064
1-bit memory array is very less compared to the other two. Layout
of conventional 6T, 8T and proposed 10T SRAM bit cells are Table.5. Area analysis of peripheral circuits
shown in Fig.18 to Fig.20.
Pre-charge Sense
Peripherals Write driver
Circuit amplifier
Area (µm2 ) 12.1196 76.032 28.8948

6. CONCLUSION
In this paper, we have presented a 1-bit 10T SRAM memory
that provides better read stability, lower power consumption and
lesser area compared to conventional 6T, conventional 8T 1-bit
memory array. It also reduces the bit-line leakage problem in the
conventional 8T SRAM cell and the read stability problem in
conventional 6T SRAM cell. Thus the proposed 10T SRAM can
be used as a cache memory in internal CPU and can be also used
in industry and military purposes.
Measurements from an 180nm bulk CMOS confirm the
successful operation of the proposed 1-bit 10T SRAM memory.
Fig.18. Layout of 6T SRAM cell To conclude, for technologies that are challenging in read
stability, power and area, the proposed 1-bit 10T SRAM memory
is an alternative bit-cell option due to its high read stability, lower
power consumption and lesser area.

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