DRAFT ONLY

Application Report
SBAA417 – June 2020

AFE79xx Configuration Guide

K.S.V.Phanindra

ABSTRACT
The purpose of this document is to give a brief insight into various blocks of AFE79xx, explain how to
identify the proper settings for your system, and configure the AFE through Latte software.

Contents
1 Introduction ................................................................................................................... 3
1.1 Nomenclature ....................................................................................................... 4
1.2 Configuration Check List .......................................................................................... 4
2 System Configuration ....................................................................................................... 5
2.1 Introduction .......................................................................................................... 5
2.2 Sampling Rates, Interface Rates, Mixers and Number of Bands............................................. 7
2.3 Other Top Parameters ........................................................................................... 17
2.4 Case Study ......................................................................................................... 19
3 JESD Configuration ....................................................................................................... 20
3.1 Introduction ......................................................................................................... 20
3.2 ADC JESD TX Configuration .................................................................................... 21
3.3 DAC JESD RX Configuration .................................................................................... 28
3.4 JESD Common Settings.......................................................................................... 31
3.5 Case Study ......................................................................................................... 32
4 GPIO Configuration ....................................................................................................... 35
4.1 Introduction ......................................................................................................... 35
4.2 Key Points .......................................................................................................... 37
4.3 Configuring ......................................................................................................... 37
5 RX DSA, AGC and ALC .................................................................................................. 40
5.1 Introduction ......................................................................................................... 40
5.2 Common Controls ................................................................................................. 43
5.3 Internal AGC Controls ............................................................................................ 44
5.4 Automatic Level Controller (ALC) ............................................................................... 46
5.5 External AGC Mode ............................................................................................... 48
5.6 Choosing Settings for AGC ...................................................................................... 50
6 DSA Calibrations ........................................................................................................... 51
6.1 RX/FB DSA Calibration ........................................................................................... 51
6.2 TX DSA Calibration ............................................................................................... 51
7 Power Amplifier Protection (PAP) ........................................................................................ 52
7.1 Introduction ......................................................................................................... 52
7.2 Using PAP .......................................................................................................... 57
7.3 Configuration ....................................................................................................... 57
8 Miscellaneous Functions .................................................................................................. 60
8.1 SPIB1/SPIB2 ....................................................................................................... 60
8.2 TX DSA Control ................................................................................................... 60
8.3 FB DSA Control ................................................................................................... 61
8.4 Alarms .............................................................................................................. 62
8.5 NCO Switching .................................................................................................... 64

SBAA417 – June 2020 AFE79xx Configuration Guide 1

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com

8.6 Sysref ............................................................................................................... 65

8.7 ADC to DAC Post Decimation Loop Back ..................................................................... 65
8.8 ADC to DAC Low Latency Loopback: .......................................................................... 65
8.9 Using FB Chain as RX Chain .................................................................................... 65
9 Bring-Up Flow and Log File .............................................................................................. 66
9.1 Configuration File.................................................................................................. 66
9.2 Initialization Flow From Configuration File ..................................................................... 67
10 System Parameters ....................................................................................................... 76
10.1 TOP Parameters .................................................................................................. 76
10.2 JESD Parameters ................................................................................................. 80
10.3 GPIO Config ....................................................................................................... 82
10.4 AGC and ALC Parameters ....................................................................................... 90
10.5 PAP Config ......................................................................................................... 94
10.6 Miscellaneous ...................................................................................................... 96

List of Figures
1 RX Digital Chain ............................................................................................................. 8
2 TX Digital Chain.............................................................................................................. 8
3 FB Digital Chain.............................................................................................................. 9
4 iGui for Top System Parameters .......................................................................................... 9
5 iGui Showing the Clocking Diagram With Individual Clock Divider Settings ....................................... 11
6 Clocking Path Highlighted With Internal PLL for All TX, FB and RX ............................................... 12
7 Clocking Path Highlighted With Internal PLL for TX and FB and External Clock for RX ......................... 13
8 Clocking Path Highlighted With External Clock for TX, FB and RX ................................................ 14
9 ADC JESD TX Functional Block Diagram .............................................................................. 21
10 iGui for ADC JESD TX .................................................................................................... 27
11 DAC JESD RX Functional Block Diagram ............................................................................. 28
12 iGui for DAC JESD RX ................................................................................................... 31
13 Functional Block Diagram for GPIO Block ............................................................................. 36
14 iGui for GPIO Status ....................................................................................................... 38
15 Detectors in RX Digital Chain............................................................................................. 41
16 Digital Peak Detectors .................................................................................................... 41
17 Controller Algorithm for Internal AGC ................................................................................... 43
18 PAP Block in TX Chain ................................................................................................... 53
19 Triggers and Alarms to PAP .............................................................................................. 54
20 PAP Timing Diagram When a Single PAP Trigger Occurs ........................................................... 56
21 PAP Timing Diagram When Multiple PAP Triggers Occur ........................................................... 57
22 Alarms Recovery .......................................................................................................... 63
23 Initialization Flow for Continuous Sysref (Part 1) ...................................................................... 67
24 Initialization Flow for Continuous Sysref (Part 2) ...................................................................... 68
25 Initialization Flow for Continuous Sysref (Part 3) ...................................................................... 69
26 Initialization Flow for Continuous Sysref (Part 4) ...................................................................... 70
27 Initialization Flow for Single Shot Sysref (Part 1) ..................................................................... 71
28 Initialization Flow for Single Shot Sysref (Part 2) ..................................................................... 72
29 Initialization Flow for Single Shot Sysref (Part 3) ..................................................................... 73
30 Initialization Flow for Single Shot Sysref (Part 4) ..................................................................... 74

List of Tables
1 TX DAC to FB ADC Combinations ........................................................................................ 6
2 Supported Modes: Sampling Rates to Interface rates Mapping for RX .............................................. 6
3 Supported Modes: Sampling Rates to Interface rates Mapping for FB ............................................... 6

2 AFE79xx Configuration Guide SBAA417 – June 2020

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com Introduction
4 Supported Modes: Sampling Rates to Interface rates Mapping for TX ............................................... 7
5 External Clock Modes ..................................................................................................... 10
6 RX NCO Switching Modes to RX_NCOSEL_X Function Mapping .................................................. 16
7 TX NCO Switching Modes to TX_NCOSEL_X function mapping.................................................... 17
8 FB NCO Switching Modes to FB_NCOSEL_X function mapping.................................................... 17
9 List of RRF Modes ......................................................................................................... 18
10 JESD System Mode ....................................................................................................... 23
11 Default Output for Each JESD System Mode ......................................................................... 23
12 Valid Parameters for each JESD System Mode ....................................................................... 24
13 ADC JESD Sync Mux Mapping .......................................................................................... 25
14 DAC JESD Sync Mux Mapping .......................................................................................... 30
15 Use Case 1 Configuration ................................................................................................. 32
16 JESD Case Study 1: ADC Lane Mapping .............................................................................. 33
17 JESD Case Study 1: DAC Lane Mapping .............................................................................. 33
18 Use Case 3 Configuration ................................................................................................. 33
19 Lane-Wise ADC Data ...................................................................................................... 35
20 Lane-Wise DAC Data ...................................................................................................... 35
21 Bandwidths for Band Specific Detectors ................................................................................ 42
22 External AGC Detector Information on LSB and Pins ................................................................. 48
23 Bit Wise Mapping for Pin/LSB outputs of External AGC .............................................................. 49
24 8-Pin External AGC Mode: Pin Mapping ................................................................................ 49
25 PAP alarmChannelMask mapping for Each Channel ................................................................ 58
26 PAP alarmMask mapping ................................................................................................ 59
27 FB DSA Pin Based Switching ............................................................................................ 61
28 Alarms Onto Pin Description ............................................................................................. 63
29 Top Level Parameters ..................................................................................................... 76
30 List of Supported Input Functions ........................................................................................ 83
31 List of Supported Output Functions ...................................................................................... 88
32 List of AGC and ALC Parameters ........................................................................................ 90
33 List of PAP Related Parameters ......................................................................................... 94
34 List of Calibration Related Parameters .................................................................................. 96
35 List of DSA Related Parameters ......................................................................................... 96
36 List of Alarms Related Parameters ...................................................................................... 97
37 Miscellaneous Parameters ................................................................................................ 97
Trademarks
All trademarks are the property of their respective owners.

1 Introduction

TI's new generation transceiver, AFE79xx, has high level of integration of features and flexibility of
configurations. These benefits also increase the complexity of programming AFE79xx. The Latte software
serves as a high-level synthesizer tool by abstracting the necessary system parameters to generic
terminology in order to simplify the AFE79xx configuration generation. Once the parameters are entered in
Latte, the software checks for the validity of the configuration and gives the failing checks. Besides, Latte
software also acts as evaluation tool for EVM testing.
In each of the following sections, different blocks of the device are introduced, and the related system
parameters (parameter name in italics and brackets) are explained. The format to access the parameters
is present in Section 9.

SBAA417 – June 2020 AFE79xx Configuration Guide 3

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

Introduction www.ti.com

For example, Section 2.1 and Section 2.2 describes how to choose the sampling rates. Consider the “DAC
sampling frequency (Fdac)” in Section 2.2. The system parameter is in italics and brackets: Fdac. The
format to set the parameter in Latte when configuring through code is present in Section 9.2. The format is
given in the starting of the section:
Format: sysParams.<parameter>
The default value and explanation of the format for the same is present in Section 9.2. For DAC sample
rate of 8847.36 MHz, the parameter is set as:
sysParams.Fdac = 8847.36

1.1 Nomenclature
• DAC: Digital-to-Analog Converter (Transmitter Downlink)
• ADC: Analog-to-Digital Converter (Receiver Uplink)
• FB: Feedback ADC for Digital Pre-Distortion
• DPD: Digital Pre-distortion
• DGC: Digital Gain Compensation, also known as Automatic Level Control (ALC)
• ALC: Automatic Level Control, also known as Digital Gain Compensation.
• LCM: Least Common Multiple
• DSA: Digital Step Attenuator
• JESD204: JEDEC standard for Serial Link Transfer for Data Converters. Also referred to as JESD in
this document.
• NCO: Numerical Control Oscillator

1.2 Configuration Check List

This section acts as a check list of what features and settings are needed for configuration. Identifying
these requirements helps create a suitable configuration for the AFE.
System Use Case:
1. Frequency bands of interest
2. Number of RX channels
3. Number of FB channels
4. Number of TX channels
5. TDD or FDD system
6. Need External clock for RX/TX & FB
RX:
1. ADC sampling rate
2. Interface rate/Bandwidth
3. Single or Dual Band
4. Need dynamic NCO Switching?
TX:
1. DAC sampling rate
2. Interface rate/Bandwidth
3. Single or Dual Band
4. Need NCO Switching?
FB:
1. ADC sampling rate
2. Interface rate/Bandwidth
3. Single or Dual Band
4. Need NCO Switching?
4 AFE79xx Configuration Guide SBAA417 – June 2020
Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com System Configuration

5. Want dedicated ADC for FB or share analog with RX ADC (in TDD system scenario)?
JESD204:
1. Protocol (204B/204c)?
2. Independent or common Lanes for RX and FB
3. What all channels of RX form single link?
4. What all channels of FB form single link?
5. What all channels of TX form single link?
6. RX LMFSHd mode(s)
7. FB LMFSHd mode(s)
8. TX LMFSHd mode(s)
9. CMOS or LVDS Sync Interface?
RX AGC:
1. Internal AGC?
• What detectors are needed?
2. External AGC?
• What detectors are needed?
• Need the detector information on LSBs or pins?
• DSA control: 8-Pin based or 4-pin based or SPI Based Control?
3. ALC (DGC) Enable?
• Which mode of ALC is needed?
Miscellaneous:
1. PAP
2. Alarm pins
3. Gain Swap for RX/TX
4. Need additional SPI intefaces: SPIB1/SPIB2?
GPIO:
1. Need to identify the pins for each of the above functionalities

2 System Configuration

2.1 Introduction
The AFE79xx is a family of high-performance, wide bandwidth multi-channel transceivers, integrating four
RF sampling transmitter chains, four RF sampling receiver chains and up to two RF sampling digitizing
auxiliary chains (feedback paths). The high dynamic range of the transmitter and receiver chains allows
generating and receiving 3G, 4G, and 5G signals for wireless base stations, while the wide bandwidth
capability makes the AFE79xx devices suitable for multi-band 4G and 5G base stations. Each receiver
chain includes a 25-dB range DSA (Digital Step Attenuator), followed by a RF Sampling ADC (analog-to-
digital converter). Each receiver channel has two analog peak power detectors and various digital power
detectors to assist an external or internal autonomous automatic gain controller and RF overload detectors
for device reliability protection. The single or dual digital down converters (DDC) provide up to 600 MHz of
combined signal BW. In TDD mode, the receiver channel can be configured to dynamically switching
between traffic receiver (TDD RX) and wideband feedback receiver (TDD FB), with the capability of
reusing the same analog input for both purposes. Each transmitter chain includes a single or dual digital
up converters (DUCs) typically supporting up to 1200-MHz combined signal bandwidth. The output of the
DUCs drives a 12-GSPS DAC (digital to analog converter) with a mixed mode output option to enhance
2nd or 3rd Nyquist operation. The DAC output includes a variable gain amplifier (TX DSA) with 40-dB
range and 1-dB analog and 0.125-dB digital steps. The feedback path includes a 25-dB range DSA driving
a RF sampling ADC, followed by a DDC with up to 1200-MHz bandwidth.

SBAA417 – June 2020 AFE79xx Configuration Guide 5

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

System Configuration www.ti.com

Table 1. TX DAC to FB ADC Combinations

÷ Fdac (Msps)
3932.16 4432.68 4915.20 5898.24 7372.80 7864.32 8847.36 9830.40 11796.4
8
2 1966.08 2211.84 2457.6 2949.12
3 1474.56 1966.08 2457.6 2949.12
FadcFb (MSPS)
4 1228.80 1474.56 1966.08 2211.84 2457.60 2949.12
6 1228.80 1474.56

There is a constraint on the Fdac to FadcFb ratio. In Table 1, the entries in green are the supported full-
rate FadcFb sampling rates for each Fdac, and the blue entries are the supported half-rate FadcFb
sampling rates. If sampling rates other than those tabulated above are desired, similar ratios between
Fdac and FadcFb are supported, with each of Fdac and FadcFb scaled by the same factor. For instance,
a (6000.00 MSPS, 3000.00 MSPS) combination for (Fdac, FadcFb), is supported as a scaled variant of
the (5898.24 MSPS, 2949.12 MSPS) combination.

Table 2. Supported Modes: Sampling Rates to Interface rates Mapping for RX

RX ADC Sample Rate (MSPS)
AFE7920/AF AFE7921/AF
Output Rate
1228.8 1474.56 1966.08 2211.84 2457.6 2949.12 E7988 E7889
(MSPS)
Support Support
Single/Dual
61.44 20 24 32 40 48 Single Band
Band
Single/Dual
92.16 15 24 32 Single Band
Band
Single/Dual
122.88 10 12 16 20 24 Single Band
Band
Single/Dual
184.32 8 12 16 Single Band
Band
Single Band
for all. Dual
245.76 5 6 8 10 12 Single Band
Band for
non-greyed.
Single Band
for all. Dual
368.64 4 6 8 Single Band
Band for
non-greyed.
491.52 4 5 6 Single Band Single Band
737.28 4 Single Band -

Table 3. Supported Modes: Sampling Rates to Interface rates Mapping for FB

FB ADC Sample Rate (MSPS)
AFE7920/AF AFE7921/AF
Output Rate
1228.8 1474.56 1966.08 2211.84 2457.6 2949.12 E7988 E7889
(MSPS)
Support Support
122.88 10 12 16 20 24 Single Band Single Band
184.32 8 12 16 Single Band Single Band
245.76 5 6 8 10 12 Single Band Single Band
368.64 4 6 8 Single Band Single Band
491.52 2.5 3 4 5 6 Single Band Single Band
737.28 2 3 4 Single Band -
983.04 2 2.5 3 Single Band -
1474.56 2 Single Band -

6 AFE79xx Configuration Guide SBAA417 – June 2020

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com System Configuration

Table 4. Supported Modes: Sampling Rates to Interface rates Mapping for TX

TX DAC Sample Rate (MSPS)
Input AFE7920/ AFE7921/
Rate 4423.68 4915.2 5898.24 7372.8 7864.32 8847.36 9830.4 11796.48 AFE7988 AFE7889
(MSPS) Support Support
Single/Du Single
122.88 36 40 48 60 64 72 80 96
al Band Band
Single/Du Single
184.32 24 32 40 48 64
al Band Band
Single/Du Single
245.76 18 20 24 30 32 36 40 48
al Band Band
Single/Du Single
368.64 12 16 20 24 32
al Band Band
Single/Du Single
491.52 9 10 12 15 16 18 20 24
al Band Band
Single
Band for
all. Dual
737.28 6 8 10 12 16 -
Band for
non-
greyed.
Single
Band for
all. Dual
983.04 4.5 6 7.5 8 9 10 12 -
Band for
non-
greyed.
Single
Band for
all. Dual
1474.56 3 4 6 8 -
Band for
non-
greyed.
Supporte 1105.92 1228.8 1474.56 1228.8 983.04 1474.56 1228.8 1474.56
d Dual
DUC
Combine 2211.84 2457.6 2949.12 2457.6 1966.08 2949.12 2457.6 2949.12 Power optimal
d Rates combining rate will be
(MSPS) selected based on
Second 4 4 4 6 8 6 8 8 the band separation.
Stage
Interpolati 2 2 2 3 4 3 4 4
on factor

To translate the System Level requirements to AFE79xx configuration in Latte, the first step is to identify:
• Frequency bands of operation
• Output bandwidths
• Number of bands per channel
• NCO switching mode or fixed NCO mode

2.2 Sampling Rates, Interface Rates, Mixers and Number of Bands

The sampling rate is determined by frequency planning and interface rate is determined by the bandwidth
requirement. AFE79xx supports maximum ADC sampling rate of 3 GHz and DAC sampling rate of 12
GHz. AFE79xx has an internal integer PLL which can be used to generate the sampling clocks for the
converters. The internal VCO frequencies which are supported are 7372.8 MHz, 8847.36 MHz, 9830.4
MHz, and 11796.48 MHz. However, the AFE79xx also supports external clock mode in which the user can
directly feed the RX sampling clocks, TX sampling clocks, or both, into the input reference clock.

SBAA417 – June 2020 AFE79xx Configuration Guide 7

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

System Configuration www.ti.com

Figure 1. RX Digital Chain

Figure 2. TX Digital Chain

8 AFE79xx Configuration Guide SBAA417 – June 2020

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com System Configuration

Figure 3. FB Digital Chain

Figure 4. iGui for Top System Parameters

2.2.1 Related Parameters for Sampling Rates

See Table 29 for more information.
1. Input Reference clock (FRef):
This is the input clock frequency to the AFE79xx.
2. RX ADC sampling frequency (FadcRx):

SBAA417 – June 2020 AFE79xx Configuration Guide 9

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

System Configuration www.ti.com

Determine based on frequency planning. This can be a maximum of 3 GHz. Maximum RX lane rate is
FadcRx*10 for JESD 204B and FadcRx*8.25 for JESD 204C. This can be maximum 3 GHz.
3. FB ADC sampling frequency (FadcFb):
Determine based on frequency planning. This can be a maximum of 3 GHz. Maximum FB lane rate is
max(FadcRx, FadcFb)*10 for JESD 204B and max(FadcRx, FadcFb)*8.25 for JESD 204C. This can be
maximum 3 GHz.
4. DAC sampling frequency (Fdac):
Determine based on frequency planning. Maximum TX lane rate is FadcFb*10 for JESD 204B and
FadcFb*8.25 for JESD 204C. This value can be maximum 12 GHz.
5. External Clock Mode TX (externalClockTx):
This feature can be enabled if the sampling rate of the DAC must be derived from the external clock.
This is generally useful in cases where the DAC sampling rate is not supported by the internal PLL or
when phase noise that is better than the internal PLL is needed.
6. External Clock Mode RX (externalClockRx):
This feature can be enabled if the sampling rate of the RX ADC must be derived from the external
clock. This is independent of the externalClockTx. If this and externalClockTx are both set, then the
PLL is disabled. When the externalClockTx is not set the DAC sampling clock is derived from the PLL.
This is generally useful in cases where:
1. The ADC sampling rate is not supported by the internal PLL.
2. PLL to ADC rate is not supported.
3. When phase noise is better than the internal PLL is needed.

Table 5. External Clock Modes

externalClockTx externalClockRx Description
All converter sampling clocks are derived from on-chip PLL. This is typical use
0 0
case.
The RX sampling clock is directly derived from the device reference clock
input. TX and FB sampling clocks are derived from the on-chip PLL. The
0 1
reference clock goes through pre-dividers to PLL. In this case, the FRef
should be equal to or an integer multiple of FadcRx.
The TX and FB sampling clocks are directly derived from the device reference
clock input. RX sampling clock is derived from the on-chip PLL. The reference
1 0
clock goes through pre-dividers to PLL. This is not a typical use case. In this
case, the FRef should be equal to or an integer multiple of FDac.
In this case, all the converter sampling clocks are derived from the input
1 1 reference clock and the on-chip PLL is not used. In this case, the FRef should
be equal to or an integer multiple of FDac.

7. Half-Rate Mode for RX (halfRateModeRx):

Enabling this feature halves the sampling rate (to FadcRx/2) without changing the digital clock. The
prime advantage of the half rate mode is to saving power when running at lower sampling rate is
feasible (lower sampling rate will lead to lower power). For example, say the RX sampling rate of
1228.8MSPS is sufficient for us, we can potentially achieve this by setting FadcRx as 1228.8MSPS.
However, this limits the maximum lane rate to 12288.0Mbps in JESD204B (as mentioned in point 2
above). If we want to go for a higher lane rate, this approach is not supported. For this case, FadcRx
can be set to 1228.8*2 (=2457.6)MSPS and half rate mode parameter (halfRateModeRx) can be set to
True. This halves the ADC sampling rate to half but keeps the digital clock same to ensure the
maximum lane rate of 24576.0MSPS is achieved. This is per 2R setting and hence can also be used to
set one of RX AB/CD sampling rate as half the other.
8. Half-Rate Mode for FB (halfRateModeFb):
Similar to halfRateModeRx.
9. Half-Rate Mode for TX (halfRateModeTx):
Similar to halfRateModeRx.

10 AFE79xx Configuration Guide SBAA417 – June 2020

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com System Configuration

Figure 5. iGui Showing the Clocking Diagram With Individual Clock Divider Settings

Setting the above parameters calculates the internal dividers to appropriate values. The internal divider
values can be seen in the iGui PLL tab.

SBAA417 – June 2020 AFE79xx Configuration Guide 11

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

System Configuration www.ti.com

Figure 6. Clocking Path Highlighted With Internal PLL for All TX, FB and RX

12 AFE79xx Configuration Guide SBAA417 – June 2020

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com System Configuration

Figure 7. Clocking Path Highlighted With Internal PLL for TX and FB and External Clock for RX

SBAA417 – June 2020 AFE79xx Configuration Guide 13

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

System Configuration www.ti.com

Figure 8. Clocking Path Highlighted With External Clock for TX, FB and RX

2.2.2 Related Parameters for Digital Chain

See Table 29 for more information.
1. RX decimation Factor (ddcFactorRx):
This is per channel setting and determines the RX interface rate. The bandwidth is approximately 81%
of the interface rate.
2. Number of RX Bands (numBandsRx):
This determines if it is single band or dual band.
3. Number of active RX NCOs (numRxNCO):
This is the number of active RX NCOs per band. If NCO switching is not needed, keep this as 1.
Device supports up to 16 but current version of Latte software supports only maximum of 2. Note that
when numRxNCO is more than 2, the NCOs should be used in FCW mode and 1KHz mode is not
supported.
4. RX Mixer frequency for NCO 0 (rxNco0):
This is the array of mixer frequencies (NCOs) for each channel and band. For meeting performance of
the ADC, it is needed to have mixer frequencies of all the bands and NCOs corresponding to that RX
chain to be in same nyquist. The device supports multiple Nyquists programmed for each ADC,
however it may cause performance degradation.
5. RX Mixer frequency for NCO 1 (rxNco1):
This is the array of second set of mixer frequencies (NCOs) for each channel and band. If numRxNCO
is 1, this doesn’t matter. For meeting performance of the ADC, it is needed to have mixer frequencies
of all the bands and NCOs corresponding to that RX chain to be in same nyquist. The device supports
multiple Nyquists programmed for each ADC, however it may cause performance degradation.
6. FB decimation Factor (ddcFactorFb):

14 AFE79xx Configuration Guide SBAA417 – June 2020

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com System Configuration

This is per channel setting and determines the FB interface rate. The bandwidth is approximately 81%
if the interface rate.
7. Number of active FB NCOs (numFbNCO):
This is the number of active FB NCOs. If NCO switching is not needed, keep this as 1. Device
supports up to 16 but current version of Latte software supports only maximum of 4. Note that when
numFbNCO is more than 2, the NCOs should be used in FCW mode and 1KHz mode is not supported.
8. FB Mixer frequency for NCO 0 (fbNco0):
This is the first mixer frequency (NCO) for each channel. For meeting performance of the ADC, it is
needed to have mixer frequencies of all the NCOs corresponding to that FB chain to be in same
nyquist. The device supports multiple Nyquists programmed for each ADC, however it may cause
performance degradation.
9. FB Mixer frequency for NCO 1 (fbNco1):
This is the second NCO for each channel. If numFbNCO is 1, this doesn't matter. For meeting
performance of the ADC, it is needed to have mixer frequencies of all the NCOs corresponding to that
FB chain to be in same nyquist. The device supports multiple Nyquists programmed for each ADC,
however it may cause performance degradation.
10. TX interpolation Factor (ducFactorTx):
This is per channel setting and determines the TX interface rate. The bandwidth is approximately 81%
of the interface rate.
11. Number of TX Bands (numBandsTx):
This determines if it is single band or dual band.
12. Tri or Quad Band TX (combineDucMode):
This combines TXA and TXB when the numbandsTx is 1 for both TXA and TXB (resulting in quad
band) or when numbandsTx is 1 for one of TXA and TXB (resulting in Tri Band). Similar for TXCD.
13. Number of active TX NCOs (numTxNCO):
This is the number of active TX NCOs. If no NCO switching is needed, keep this as 1. This can be
maximum of 2 in dual band and 16 in single band. However, if in single band, if numTxNCO is greater
than 2, only FCW mode of the NCO is supported. 1KHz is not supported. Latte software currently
supports maximum numTxNCO of 2.
14. TX Mixer frequency for NCO 0 (txNco0):
This is the first mixer frequency (NCO) in MHz for each channel and band. This is the effective mixer
frequency for each band. The internal firmware splits it to front and back mixers (As shown in
Figure 2). If the mixer frequency is more than Fdac/2, then the chain operates in second Nyquist, in
mixed mode of operation. Note that the mixer frequencies of all the bands and NCOs should be in the
same nyquist.
For Dual Band Cases,
The maximum separation of the mixer frequencies in dual band case is limited by the combining rate of
TX Mentioned in Table 4. Say the input data rate is IDR, the combining rate is CMR, and the center
frequencies for the two bands of interest are NCO0 and NCO1 (NCO0> NCO1). The edges of the
bands are such that the individual bands do not go beyond the bandwidth at the combining rate (that
is, NCO0-NCO1 < 0.81*(CMR-IDR)). The maximum separation of the two bands is 0.81*(combining
rate – Input data rate). The multiplication factor, 0.81, is the filter bandwidth to rate ratio.
For the example, if the combining rate is 1474.56 MHz and the input data rate is 491.52 MHz, the
maximum separation between the bands is approximately 796 MHz.
Out of the two combining rate options mentioned for each case, the minimum value feasible will be
chosen based on the maximum separation between bands and NCOs (in case 2 NCOs are used). For
example, in case Fdac is 8847.36MSPS, the combining rate can be 1474.56MSPS or 2949.12MSPS.
Based on above calculation,
When numTxNco=1,
If the max(txNco0 band 0, txNco0 band 1)-min(txNco0 band 0, txNco0 band 1)<796MHz, then
1474.56MSPS will be the combining rate. Otherwise, 2949.12MSPS will be the combining rate.
When numTxNco=2,
max(txNco0 band 0, txNco0 band 1,txNco1 band 0, txNco1 band 1)-min(txNco0 band 0, txNco0 band
1,txNco1 band 0, txNco1 band 1)< 796 MHz, then 1474.56MSPS will be the combining rate.
Otherwise, 2949.12MSPS will be the combining rate.
In a dual band case, if the NCOs are intended to be changed after initialization, it is needed to give a
band separation of more than 0.81*(combining rate – Input data rate) for these parameters.

SBAA417 – June 2020 AFE79xx Configuration Guide 15

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

System Configuration www.ti.com

15. TX Mixer frequency for NCO 1 (txNco1):

This is the second NCO for each channel and band. In case when numTxNCO is 1, this doesn't matter.
The description and conditions are same as for txNco0.
16. NCO frequency mode (ncoFreqMode):
NCOs can either have a 32-bit resolution (FadcRx/2^32) or 1-KHz raster. Typically KHz mode with 1-
KHz raster is useful to match TX and FB frequencies. Both modes ensure phase consistency. The 1-
KHz mode is supported only when the DAC/ADC rates are the standard combinations above.
17. RX NCO Switching mode (ncoRxMode, broadcastRxNcoSel):
There are in total of 4 GPIO functions (RX_NCOSEL_0/1/2/3) for RX which can be used to switch the
NCOs. These pins can be used to control the NCOs in various methods based on use case. These two
parameters together give options to do this switching. Note that required number of the GPIO functions
based on numRxNco and the NCO Mode need to be brought on to the pins for the pin-based GPIO
control. (Refer to Section 4 on how to). More details on this will be covered in the NCO switching
section. Valid only when numRxNco is greater than 1.
Supported Modes:
0- No Control to both bands
1- 1Pin/RX NCOSEL_0 for RxA Band0, NCOSEL_1 for RxB Band0, NCOSEL_2 for RxC Band0,
NCOSEL_3 for RxD Band0. No control for Band 1. Note that in this case, NCO0/1 are switched for
A&C, NCO0/2 are switched for B&D. The pin value of 0 selects the first NCO (rxNco0) and value of
1 selects the second NCO (rxNco1) for band 0. This is in general good to avoid since it is relatively
more complex and NCO2 doesn’t support 1KHz mode.
2- 1Pin/2RX NCOSEL_0 for RxAB Band0, NCOSEL_1 for RxCD Band0. Same Pins control Band 1.
The pin value of 0 selects the first NCO (rxNco0) and value of 1 selects the second NCO (rxNco1)
for both band 0 and band 1.
3- 2Pin/2RX NCOSEL_0 for RxAB Band0, NCOSEL_2 for RxCD Band0. NCOSEL_1 for RxAB
Band1, NCOSEL_3 for RxCD Band1. The pin value of 0 selects the first NCO (rxNco0) and value of
1 selects the second NCO (rxNco1) for the corresponding band.
4- 2Pin/2RX NCOSEL_1/0 for RxAB Band0, NCOSEL_3/2 for RxCD Band0. No control to Band 1.
NCOSEL_0 is the LSB and NCOSEL_1 is the MSB for RXAB Band 0. NCOSEL_2 is the LSB and
NCOSEL_3 is the MSB for RXCD Band 0. Pin values of 0/1/2/3 selects the corresponding NCO
number.
5- Common NCOSEL_1/0 for all channels Band 0. This will be chosen if either of the entries are 5.
This is for cases where the numRxNco<=4. NCOSEL_0 is the LSB and NCOSEL_1 is the MSB for
all RX channels Band 0. Pin values of 0/1/2/3 selects the corresponding NCO number.
6- Common NCOSEL_3/2/1/0 for all channels Band 0. This will be chosen if either of the entries are
6. This is for cases where the numRxNco>4. NCOSEL_0 is the LSB and NCOSEL_3 is the MSB for
all RX channels Band 0. Pin values of 0/1/2../15 selects the corresponding NCO number.

Table 6. RX NCO Switching Modes to RX_NCOSEL_X Function Mapping

RXA RXA RXB RXB RXC RXC RXD RXD
Band0 Band1 Band0 Band1 Band0 Band1 Band0 Band1
ncoRxMod broadcast
(Function (Function (Function (Function (Function (Function (Function (Function
e RxNcoSel
number number number number number number number number
MSB:LSB) MSB:LSB) MSB:LSB) MSB:LSB) MSB:LSB) MSB:LSB) MSB:LSB) MSB:LSB)
0 x - - - - - - - -
1 0 0 x 1 x 2 x 3 x
1 1 0 x 1 x 0 x 1 x
2 0 0 0 0 0 1 1 1 1
2 1 0 0 0 0 0 0 0 0
3 0 0 1 0 1 2 3 2 3
3 1 0 1 0 1 0 1 0 1
4 0 1:0 x 1:0 x 3:2 x 3:2 x
4 1 1:0 x 1:0 x 1:0 x 1:0 x
5 x 1:0 x 1:0 x 1:0 x 1:0 x
6 x 3:0 x 3:0 x 3:0 x 3:0 x

16 AFE79xx Configuration Guide SBAA417 – June 2020

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com System Configuration

18. TX NCO Switching mode (ncoTxMode, broadcastTxNcoSel):

There are in total of 4 GPIO functions (TX_NCOSEL_0/1/2/3) for TX which can be used to switch the
NCOs. These pins can be used to control the NCOs in various methods based on use case. These two
parameters together give options to do this switching. Note that required number of the GPIO functions
based on numTxNco and the NCO Mode need to be brought on to the pins for the pin-based GPIO
control. (Refer to Section 4 on how to). More details on this will be covered in the NCO switching
section. Valid only when numTxNco is greater than 1.
Supported Modes:
0- No Control to both Bands
1- 1pin/2T NCOSEL_0 for TxAB Band0 and NCOSEL_1 for TxCD Band0. Same Pin Controls
Band1 also.
2- 2pin/2T NCOSEL_1/0 for TxAB Band0 and NCOSEL_3/2 for TxCD Band0. Same Pin Controls
Band1 also.

Table 7. TX NCO Switching Modes to TX_NCOSEL_X function mapping

broadcastTxNcoSe TXA(Function TXB (Function TXC (Function TXD (Function
ncoTxMode
l number MSB:LSB) number MSB:LSB) number MSB:LSB) number MSB:LSB)
0 x - - - -
1 0 TX_NCOSEL_0 TX_NCOSEL_0 TX_NCOSEL_1 TX_NCOSEL_1
1 1 TX_NCOSEL_0 TX_NCOSEL_0 TX_NCOSEL_0 TX_NCOSEL_0
TX_NCOSEL_1: TX_NCOSEL_1: TX_NCOSEL_3: TX_NCOSEL_3:
2 0
TX_NCOSEL_0 TX_NCOSEL_0 TX_NCOSEL_2 TX_NCOSEL_2
TX_NCOSEL_1: TX_NCOSEL_1: TX_NCOSEL_1: TX_NCOSEL_1:
2 1
TX_NCOSEL_0 TX_NCOSEL_0 TX_NCOSEL_0 TX_NCOSEL_0

19. FB NCO Switching mode (ncoFbMode):

There are in total of 4 GPIO functions (FB_NCOSEL_0/1/2/3) for FB which can be used to switch the
NCOs. These pins can be used to control the NCOs in various methods based on use case. This
parameter gives options to do this switching. Note that required number of the GPIO functions based
on numFbNco and the NCO Mode need to be brought on to the pins for the pin-based GPIO control.
(Refer to Section 4 on how to do this). More details on this will be covered in the NCO switching
section. Valid only when numFbNco is greater than 1.
Supported Modes:
0- No NCO switching Control
1- 2Pin/FB (NCOSEL_0 and NCOSEL_1 for FBAB, NCOSEL_2 and NCOSEL_3 for FbCD).
2- Common 4Pin NCOSEL_3/2/1/0 for all FB.

Table 8. FB NCO Switching Modes to FB_NCOSEL_X function mapping

ncoFbMode FBAB (Function number MSB:LSB) FBCD (Function number MSB:LSB)
0 - -
1 FB_NCOSEL_1:FB_NCOSEL_0 FB_NCOSEL_3:FB_NCOSEL_2
2 FB_NCOSEL_3:FB_NCOSEL_0 FB_NCOSEL_3:FB_NCOSEL_0

2.3 Other Top Parameters

These are some additional system level settings to configure the AFE. Refer to the Figure 5. Usage format
of the parameters is present in Table 29.
1. Enable or disable RX (rxEnable):
This is independent for the four RX channels. Need to identify what all RX need to be enabled.
2. Enable or disable FB (fbEnable):
This is independent for FBAB and FBCD. Need to identify what all FB need to be enabled.
3. Enable or disable TX (txEnable):
This is independent for the four TX channels. Need to identify what all TX need to be enabled.

SBAA417 – June 2020 AFE79xx Configuration Guide 17

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

System Configuration www.ti.com

4. ADC to Digital Mux (adcSelect0/ adcSelect1):

This parameter is used to select the ADC data that must be fed for each digital chain among FB and 2
RX. It is necessary that RX and FB sampling rates match in cases where the data is to be muxed
between the RX and FB chains.
5. System Mode (RRFMode):
This sets the System Mode.

Table 9. List of RRF Modes

SYSTEM MODE MODE NAME DESCRIPTION
0 FDD Mode This is a typical FDD mode with 4TX, 4RX chains and 2 FB chains,
where all RX and FB chains have independent ADCs.
2 4T2R2F FDD Mode Quad Band In this case, RX AB uses RXA ADC input and all 4 bands, combined of
RXA and RXB decimation chain outputs to operate in quad band mode.
Similarly, RXCD uses RXC ADC to get 4 bands.
5 4T4R2F TDD Non-Shared This is a typical TDD mode with 4TX, 4RX chains and 2 FB chains,
where all RX and FB chains have independent ADCs.
7 4T4R2F TDD Shared This is a typical TDD mode with 4TX, 4RX chains and 2 FB chains,
where each FB chain share ADCs with one RX ADC.
10 2T2R1F TDD AB / 2T2R1F FDD AB acts as TDD and CD as FDD.
CD
11 2T2R1F FDD AB / 2T2R1F TDD AB acts as FDD and CD as TDD.
CD

Key Points:
• Shared modes will use RXA ADC for FBAB and RXC for FBCD.
• In TDD Case, RX/FB cannot be active at the same time.
• In FDD Case, RX and FB can be active at the same time with their respective TDD pins controlling.
• In cases where FB is not used to act as 4R mode, the 'F' in the above mode names doesn't matter.
6. TDD Mode (modeTdd):
The user may need to control TDDs of different channels independently. This setting is common to RX,
FB, and TX chains. This setting in conjunction with GPIO muxing gives the flexibility to do so.
Supported modes by this are:
• 0- Single TDD Pin for all Channels: RXATDD control all RX channels. RXBTDD, RXCTDD and
RXDTDD functions are invalid. TXATDD control all TX channels. TXBTDD, TXCTDD and TXDTDD
functions are invalid. FBABTDD control both FB channels. FBCDTDD is inactive.
• 1- Separate Control for 2T/2R/1F RXATDD and RXCTDD functions control RXAB and RXCD
channels respectively. RXBTDD and RXDTDD are invalid. TXATDD and TXCTDD functions control
TXAB and TXCD channels respectively. TXBTDD and TXDTDD are invalid. FBABTDD and
FBCDTDD control corresponding FB channels.
• 2- Separate Control for 1T/1R/1F RXATDD, RXBTDD, RXCTDD, RXDTDD functions control the
corresponding RX channels. TXATDD, TXBTDD, TXCTDD, TXDTDD functions control the
corresponding TX channels. FBABTDD and FBCDTDD control corresponding FB channels. The
functions used can be connected to GPIO balls. Refer to Section 4 for the same.
For example, if is user needs to control the RXA, RXB and RXC through 1 TDD pin, control the RXD
through one TDD pin and connect all TX and FB channels to another TDD pin:
• Set modeTdd to 2
• Connect RXATDD, RXBTDD and RXCTDD to one GPIO pin.
• Connect RXDTDD to second GPIO pin.
• Connect TXATDD, TXBTDD, TXCTDD, TXDTDD, FBABTDD and FBCDTDD to third GPIO pin.
7. DAC interleaved mode (enableDacInterleavedMode):
This enables the DAC in interleaved mode. This mode operates in lower power but can result in a TX
interleaving image at Fs/2-Fin. It is a trade-off between AFE power and external filtering requirement.
This cannot be used in second Nyquist operation of TX.
8. SPI mode (spiMode):

18 AFE79xx Configuration Guide SBAA417 – June 2020

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com System Configuration

This sets SPI 3 wire or 4 wire mode.

2.4 Case Study

Consider a TDD system with a RF frequency requirement at 3500 MHz, a RX bandwidth of 400 MHz, and
a TX and FB bandwidth of 800 MHz.
For the required bandwidths, the data rates needed are 491.52 MSPS for RX and 983.04 MSPS for TX
and FB to account for the bandwidths of the decimation filters. The edges of the bands (including
decimation/interpolation filter transition bands) are 3254.24 MHz to 3745.76 MHz for RX and 3008.48 MHz
to 3991.52 MHz for TX and FB. By the inherent nature of RF sampling, Nyquist boundary cannot be in
band for either ADC or DAC. In case of TX, there will be Fdac/2 (Nyquist edge) and Fdac/2+fin (image)
spurs. In case of DAC interleaved mode, there will be an additional Fdac/2-Fin (DAC interleaving spur)
spur. These need analog filtering at the output and hence, it is good to choose DAC sampling rate such
that these spurs are away from the actual band to prevent need for sharp analog filtering.
With these in mind, for the given case, the typical ADC rate of 2949.12 MSPS is good since its Nyquist
boundaries are not in band. For TX, we can go by 2949.12*2 (= 5898.24) MHz and operate in second
Nyquist. However, 2949.12 (Fdac/2) is very close to edge of the TX band (3008.48) MHz and it is very
hard to filter out the Fdac/2 and the image. And in second Nyquist, DAC cannot be operated in interleaved
mode. However, if we move Fdac to 2949.12*3 (= 8847.36) MSPS, the Fdac/2 is moved to 4423.68 MHz,
which is away from the band of interest. The DAC interleaved mode can also be employed with relative
ease of filter design, to save power, since the DAC interleaving spur falls in the range 677.92 MHz to
1415.2 MHz, which is much away from the band of interest. Even though 11796.48 MSPS (2949.12*4)
without interleaved mode is also good for frequency planning, it consumes more power. FB sampling rate
can be chosen as 2949.12 MSPS with the same thought process.
Depending on the time needed between DPD cycles for a TX channel, and if same or different bands are
needed from TX, one or two FB channels can be used for DPD. In this case, let us assume that single FB
is being used. In such cases, second FB can be disabled for optimizing power consumption. In cases,
where the TX is in dual band or different TX operate in different bands (for example, TXA and TXB are in
one band and TXC and TXD are in another band), FB needs to look both the bands. This can be
addressed either by using one FB per band or by using the single FB and employing FB NCO switching.
Points to consider in choosing this are:
1. Appropriate FB sampling rate must be arrived such that Nyquist is not in band for both the bands.
2. Post-aliasing across the nyquist boundary in ADC, the bands shouldn’t overlap for the chosen
sampling rate, if the TX is in dual band.
3. TX output need to be filtered with analog filters for each band while feeding to FB to eliminate out-of-
band TX spurs.
4. Power consumption tolerated by the system design.
However, for the present case where all TX operate in same bands, there is no need to consider these
factors.
In this example, the key parameters are chosen as:
1. Fdac = 8847.36
2. FadcRx = 2949.12
3. FadcFb = 2949.12
4. ddcFactorRx= 6 for all the channels (2949.12/491.52)
5. ddcFactorFb= 3 for all the channels (2949.12/983.04)
6. ducFactorTx= 9 for all the channels (2949.12*3/983.04)
7. numBandsRx, numbandsTx = 0 for all channels
8. rxNco, fbNco and txNco = 3500 for all the channels. Band 1 corresponding values don’t matter.
9. numRxNco, numFbNco, numTxNco =1.
10. enableDacInterleavedMode = can be 0/1 based on the analog filtering vs power trade-off.
11. RRFMode = 5/6 depending on the system requirement if the analog input is to be shared between RX
& FB or not.

SBAA417 – June 2020 AFE79xx Configuration Guide 19

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

JESD Configuration www.ti.com

12. fbEnable = [True, False]

3 JESD Configuration

3.1 Introduction
SERDES refers to the physical layer responsible to transmit and receive the lane data. The purpose of this
is only to send and receive the data. This contains options of tuning the eye of the lanes and reading the
eye. There are two instances of SERDES core in AFE79xx, each containing 4 transmitter and 4 receiver
lanes. There are total of 8 transmitter lanes (STX) and 8 receiver lanes (SRX). Each SERDES core has
one PLL for four-transmitters and another four-receivers, which can support lane rates up to 32.5 Gbps.
Independent PLLs enable completely independent lane rates for the two groups of 4 STX lanes and 4
SRX lanes. Added to this, there are per lane dividers of 1/2/4/8 between each group of STX/SRX.
ADC JESD TX (ADC_JESD) refers to the JESD transmitter of the device, which is on the ADC (both RX
and FB chains) side. This contains the protocol decode and mappers converting converter-wise data to
lane data. There are two instances of ADC_JESD, each handling 2 RX channels and 1 FB channel and up
to 4 STX lanes. First ADC_JESD block handles RXA, RXB and FBAB. Second ADC_JESD block handles
RXC, RXD and FBCD.
DAC JESD RX (DAC_JESD) refers to the JESD receiver of the device, which is on the DAC side. This
contains the protocol decode and de-mappers converting lane data to converter wise data. There are two
instances of DAC_JESD, each handling 2 TX channels and up to 4 SRX lanes. First DAC_JESD block
handles TXA and TXB. Second DAC_JESD block handles TXC and TXD.
SUBCHIP refers to the top level block common to all the instances of JESD TX and RX. This contains
options of muxing (data, lanes, sync signals).

20 AFE79xx Configuration Guide SBAA417 – June 2020

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com JESD Configuration

3.2 ADC JESD TX Configuration

Figure 9. ADC JESD TX Functional Block Diagram

Key Blocks of the ADC JESD(Figure 9):

1. RX/FB DDC-JESD MUX:
This is the mux between the Decimation output to the JESD block. This mux can only be employed if
the default and the new channel has the same interface rates. Note that the 1-1 to 1-8 refer inputs to
the first instance of ADC-JESD and 2-1 to 2-4 represent the inputs to the second instance of ADC-
JESD after DDC-JESD MUX.
2. Mapper:
This is responsible in remapping the converter-wise data into the lane wise data based on the LMFSHd
setting.
3. System Mode Based Mux:
This re-maps the output of the mappers onto the lanes based on the system mode configuration
(jesdSystemMode) and the TDD.
4. IP Layer:
This handles the JESD protocol and sends the lane data to the physical layer (SerDes).
5. SerDes:
This is the physical layer responsible to send the data onto the lanes.
Each instance of ADC_JESD has 3 mappers,

SBAA417 – June 2020 AFE79xx Configuration Guide 21

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

JESD Configuration www.ti.com

1. RXMapper1:
Depending on the system mode and LMFSHd, this can handle either only the first RX channel of the
instance or 2 RX channels. However, the first instance of ADC_JESD can handle all the 4 RX
channels, by selecting M=8 for single band case and M=16 for dual band case.
2. RXMapper2:
This is active only in some system modes and can handle only second RX channel when active.
3. FB Mapper: This handles the FB data.
To tie the SYNCIN signal for multiple mappers together will make the corresponding lanes act as single
link. In general all the mappers which are to be under single link have same values for Scrambler, K and
F.
Note that for shared lane cases, the following conditions should be satisfied:
1. Lane rates should be same
2. F in the LMFSHd should be same.
3. K should be same.
Things to identify before configuring JESD:
1. How many links for RX?
1. Per RX channel, or
2. Per 2RX, or
3. Common for all 4 RX.
2. Independent or common link for FB?
3. RX and FB should share lanes or have independent lanes?
4. Which JESD protocol?
1. 204B mode
2. 204C, 64/66 mode
3. 204C, 64/80 mode
5. Which JESD mode/lane rate for each link? The data rate combined with JESD mode determines the
lane rate.

3.2.1 Finding Settings for Your Use Case

Make sure to identify the correct settings before moving forward.
1. Identify the JESD System Mode (jesdSystemMode).
2. Find the LMFSHd per 2RX/1RX (as the JESD system Mode needs) and 1FB.
3. Put the Sync Mux (rxJesdTxSyncMux/ fbJesdTxSyncMux) to groups channels into links as needed.
4. Choose rest of the settings.

3.2.2 JESD System Mode (jesdSystemMode)

There are multiple System Modes for the ADC_JESD that must to be chosen as per use case. This setting
is independent for each instance of ADC_JESD. Each JESD System Mode can be used for different use
cases. Most common use cases are:
• 1 for TDD RX-FB dedicated lane or FDD.
• 5 for TDD RX-FB lane share sharing

22 AFE79xx Configuration Guide SBAA417 – June 2020

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com JESD Configuration

Table 10. JESD System Mode

JESD SYSTEM MODE MODE NAME USE CASE
0 2R1F-FDD RXA, RXB and FBAB (RXC, RXD and
FBCD for instance 1) channels must:
• Act as different links, or
• Different data rates, or
• Different lane rates or LMFSHd
modes.
1 1R1F-FDD This is needed when both RX (AB for
instance 0 and CD for instance 1) have
same data rates and FB must be on
different lanes. In this mode, the two RX
channels of the instance will be in same
link.
• Need different links for RX and FB,
or
• Lane rate is not same for RX and FB,
or
• ‘F’ of LMFSHd of RX and FB are not
equal.
2 2R-FDD This is for cases where FB of the instance
is not needed and two RX channels of the
instance have:
• Different data rates, or
• Act as different links, or
• Different lane rates or LMFSHd
modes.
3 1R This is for the case where, FB is not
needed and only both channels of the RX
are to be treated as a single link.
4 1F This is for the case where, RX is not
needed and only FB is needed.
5 1R1F-TDD This is for RX and FB lane sharing case
with same link.
8 1R1F-TDD 1R-FDD This is for cases where RXMapper2 and
FB lanes are shared and RXMapper1 has:
• Different data rates than RXMapper2
or
• Act as different links from
RXMapper2, or
• Different lane rates or LMFSHd
modes from RXMapper2.

Table 11. Default Output for Each JESD System Mode

NAME 2R1F-FDD 1R1F-FDD 2R-FDD 1R 1F 1R1F-TDD 1R-FDD
1R1F-TDD
System Mode 0 1 2 3 4 5 8
Lane 0 rx1 rx12 rx1 rx12 fb rx12/fb rx1
Lane 1 rx2 rx12 - rx12 fb rx12/fb -
Lane 2 fb fb rx2 rx12 fb rx12/fb rx2/fb
Lane 3 fb fb rx2 rx12 fb rx12/fb rx2/fb

In Table 11:
1. rx1 refers to the RXA/RXC, rx2 refers to RXB/RXD, rx12 refers to RXAB/RXCD pairs.
2. If there is rx12 for a particular System Mode that means both RX channels comes out through same
mapper (RXMapper1).
3. If there is rx12/fb is present, TDD signals determine if RX 1 and 2 or FB data comes out. If there is
SBAA417 – June 2020 AFE79xx Configuration Guide 23
Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

JESD Configuration www.ti.com

rx2/fb is present, TDD signals determine if RX 2 or FB data comes out.

4. The number of lanes for each mapper output mentioned above is maximum and actual number
depends on the LMFSHd mode. For example, in system mode 1, if RX mode is 14810 and FB is
22210, lane 0 has RX 1&2 data and lanes 2-3 have FB data. Lane 1 is not used and is powered down
even though as per Table 11, rx12 is assigned both lane0 and lane 1.

3.2.3 ADC JESD IP Related

See Section 10.2 for more information.
Many of the settings listed in Section 9 are per mapper/IP Layer. The interpretation of the 4 entries in the
table of JESD system parameters above in case of RX (since RX has 2 mappers per ADC_JESD
instance) are based on the system mode shown in Table 12

Table 12. Valid Parameters for each JESD System Mode

JESD SYSTEM MODE 1ST ENTRY 2ND ENTRY 3RD ENTRY 4TH ENTRY
0/2/8 RXA RXB RXC RXD
1/3/5 RXA & RXB Doesn’t matter RXC & RXD Doesn’t matter

There are up to 6 CMOS sync signals (ADC_SYNC0/1/2/3/4/5). When LVDS sync mode is enabled,
ADC_SYNC0/3 can be used as LVDS SYNC, ADC_SYNC1/4 are used in conjunction with ADC_SYNC0/3
and cannot be used independently and ADC_SYNC2/5 can be used as CMOS. All the sync signals which
are needed have to be brought out on GPIO pins. Refer to Section 4 for this.

1. RX JESD mode (LMFSHdRx):

This is the LMFSHd setting for the RX ADC_JESD. This is a per-mapper setting. Supported LMFSHd
modes for RX decimation factors ≥ 4:
'24410', '14810', '14610', '24610', '1-4-12-1-0', '44210', '28810', '28610', '48610', '42111', '48410',
'12310', '22210', '48310', '24310', '44310', '1-8-12-1-0', '2-8-12-1-0','42220', '1-8-16-1-0', '1-8-24-1-0',
'12610', '12410', '1-4-16-1-0', '1-8-32-1-0', '1-16-32-1-0', '1-16-24-1-0'
Supported LMFSHd modes for RX decimation factors < 4:
'24820', '12810', '24620', '44620', '44420', '22320', '1-4-24-2-0', '41240', '41121', '44210', '42220',
'14810', '1-2-16-2-0_DUP', '2-4-12-2-0', '1-4-16-1-0', '42320', '24410', '12610', '12410', '12310', '1-2-16-
2-0', '1-2-12-2-0', '12820', '12620', '22210', '22310', '32411_DUP', '32211', '12810_DUP', '1-2-12-1-
0_DUP', '22420', '22620', '1-2-24-2-0_DUP', '1-2-16-4-0', '22840', '1-2-24-4-0', '3-2-12-3-0_DUP',
'32830_DUP', '32630', '1-4-16-2-0', '1-4-12-2-0', '24310', '24610', '14610', '1-4-12-1-0', '42111', '44840'
In modes with _DUP, each sample is repeated.
2. FB JESD mode (LMFSHdFb):
This is per JESD mode mapper setting for FB chain and has 2 entries, one for each ADC_JESD
instance.
Supported LMFSHd modes for FB
'24820', '12810', '24620', '44620', '44420', '22320', '1-4-24-2-0', '41240', '41121', '44210', '42220',
'14810', '1-2-16-2-0_DUP', '2-4-12-2-0', '1-4-16-1-0', '42320', '24410', '12610', '12410', '12310', '1-2-16-
2-0', '1-2-12-2-0', '12820', '12620', '22210', '22310', '32411_DUP', '32211', '12810_DUP', '1-2-12-1-
0_DUP', '22420', '22620', '1-2-24-2-0_DUP', '1-2-16-4-0', '22840', '1-2-24-4-0', '3-2-12-3-0_DUP',
'32830_DUP', '32630', '1-4-16-2-0', '1-4-12-2-0', '24310', '24610', '14610', '1-4-12-1-0', '42111', '44840'
In modes with _DUP, each sample is repeated.
3. ADC JESD Protocol (jesdTxProtocol):
This determines the protocol for ADC JESD. This is independent for the two instances of ADC_JESD.
4. Scrambler for RX (rxJesdTxScr):
This is per mapper scrambler enable for RX. For all the mappers under single link, this must be into
same value. It is recommended to enable scrambler since it randomizes the data when repeated
pattern is sent. This can improve the link stability and also prevent any coupling spurs caused by
repeating pattern on SerDes lanes. For example, a long repeating pattern on SerDes causes 7th and
9th harmonics (among others) of lane rate/20.

24 AFE79xx Configuration Guide SBAA417 – June 2020

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com JESD Configuration

5. Scrambler for FB (fbJesdTxScr):

This is per IP layer scrambler enable for FB. For all the mappers under single link, this must be into
same value. It is recommended to enable scrambler since it randomizes the data when repeated
pattern is sent. This can improve the link stability and also prevent any coupling spurs caused by
repeating pattern on SerDes lanes. For example, a long repeating pattern on SerDes causes 7th and
9th harmonics (among others) of lane rate/20.
6. K for RX mappers (rxJesdTxK):
This is per IP layer K value for RX. For all the mappers under single link, this must be into same value.
• JESD 204B (8b/10b): This is the number of frames in a multi-frame for JESD 204B. Supported
values are 8,16,24,32.
• JESD 204C (64b/66b): This is the number of multi-blocks in an extended multi-block for JESD
204C, also abbreviated as 'E'. This should be chosen such that number of frames in an extended
multi-block is integer. That is, (E*256/F) should be an integer, that is E=LCM(256,F)/256. The
number 256 is because there are 256 octets in a multi-block (32*64/8). Typically, for cases 16-bit
modes (F is a power of 2), this value should be 1. For 12/24-bit modes (F is a multiple of 3), this
value should be 3.
7. K for FB mappers (fbJesdTxK):
This is per IP layer scrambler enable for FB. For all the mappers under single link, this must be into
same value.
• JESD 204B: This is the number of frames in a multi-frame for JESD 204B. Supported values are
8,16,24,32.
• JESD 204C: This is the number of multi-blocks in an extended multi-block for JESD 204C. This
should be chosen such that number of frames in an extended multi-block is integer. That is, 256/F
should be an integer. Typically, for cases 16-bit modes (F is a power of 2), this value should be 1.
For 12/24-bit modes (F is a multiple of 3), this value should be 3.
8. Sync Mux for RX (rxJesdTxSyncMux):
This is per IP layer sync mux for RX. This is to select the sync_in function out of
ADC_SYNC0/1/2/3/4/5. Supported values are 0 to 5. In LVDS sync mode, values 1 and/or 2 are not
supported as described above. For each index, the value is the ADC_SYNC signal number. For all the
mappers which must be on single link, same value must be set here. When the same value is set for
multiple mappers, the corresponding mappers act as if together they are single mapper and single
JESD core. This is valid only in JESD 204B protocol.
9. Sync Mux for FB (fbJesdTxSyncMux):
This is per IP layer sync mux for FB. This is to select the sync_in function out of
ADC_SYNC0/1/2/3/4/5. Supported values are 0 to 5. In LVDS sync mode, values 1 and/or 2 are not
supported as described above. For each index, the value is the ADC_SYNC signal number. For all the
mappers which must be on single link, same value must be set here. When the same value is set for
multiple mappers, the corresponding mappers act as if together they are single mapper and single
JESD core. This is valid only in JESD 204B protocol.
10. Setting ILA Parameters (setIlaParams):
Setting this to True enables the below parameters which sets overrides the default ILA parameters.
11. ILA value of M(jesdTxIlaM):
Sets the M value to be output from lanes of each of the IP layer.
12. ILA value of Lane ID (jesdTxIlaLid):
Sets the Lane ID value to be output from each lane pre-lane mux.
13. ILA value of L (jesdTxIlaL):
Sets the L value to be output from lanes of each of the IP layer.

Table 13. ADC JESD Sync Mux Mapping

Link Number rxJesdTxSyncMux/fbJesdTxSync GPIO function to map
Mux
CMOS-0 0 ADC_SYNC0 to any pin. jesdABLvdsSync is False.
CMOS-1 1 ADC_SYNC1 to any pin. jesdABLvdsSync is False.
CMOS-2 2 ADC_SYNC4 to any pin.
CMOS-3 3 ADC_SYNC2 to any pin. jesdCDLvdsSync is False.

SBAA417 – June 2020 AFE79xx Configuration Guide 25

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

JESD Configuration www.ti.com

Table 13. ADC JESD Sync Mux Mapping (continued)

Link Number rxJesdTxSyncMux/fbJesdTxSync GPIO function to map
Mux
CMOS-4 4 ADC_SYNC3 to any pin. jesdCDLvdsSync is False.
CMOS-5 5 ADC_SYNC5 to any pin.
LVDS-0 0 ADC_SYNC0 and ADC_SYNC1 to H8 and H7 respectively.
jesdABLvdsSync is True. Note that this setting is common for
DAC_SYNC0-1 and ADC_SYNC0-1.
LVDS-1 3 ADC_SYNC2 and ADC_SYNC3 to N8 and N7 respectively.
jesdCDLvdsSync is True. Note that this setting is common for
DAC_SYNC0-1 and ADC_SYNC0-1.

3.2.4 ADC JESD MUXES and MISC

See Section 10.2 for more information

1. ADC JESD Lane Mux (jesdTxLaneMux):

This chooses the JESD lane (before the MUX, towards the AFE) for each SERDES lane (after the
MUX, towards the SERDES STX). For example, if the data on 4th JESD lane on to the 2nd SERDES
lane, make the 2nd element in the array as 3. This lane mux has corresponding lane mux and can mux
even lanes which are of different lane rates. This is especially useful for cases where a single
SERDES cannot support the two rates. Say, the RX lane rate is 9830.4 Mbps and FB lane rate is
14745.6 Mbps, single instance SERDES cannot support it. So the lane mux can be employed to get all
the RX lanes on one SERDES instance (STX1-4) and all FB lanes to second instance (STX5-6). It is to
be noted that there is no duplication allowed in this. And hence, the list should always contain all
values from 0-7.
2. ADC Data Mux enable (adcDataMuxEn):
This enables the data mux setting. If disabled, it uses the default values.
3. RX ADC Data Mux (rxDataMux):
This is the data mux, which exists before the mapper, between the decimation chain output to JESD
input.
Choose what will come in each location for RX Channel. RX channels 0/1/2/3 are referred as A/B/C/D.
B0 is band 0 and B1 is band 1.
Location Meaning:
[A_B0, A_B1, B_B0, B_B1, C_B0, C_B1, D_B0, D_B1]
Value meaning:
0-A_B0
1-A_B1
2-B_B0
3-B_B1
4-C_B0
5-C_B1
6-D_B0
7-D_B1
Eg: To swap RXA Band 0 and RXC Band 1,
[5,1,2,3,4,0,6,7]
Note that the data rates of the channel corresponding to location and the mux value should be same.
4. FB ADC Data Mux (fbDataMux) :
Choose what will come in each location for FB Channel.
Location Meaning:
[FBAB, FBCD]
Value meaning:
0-FBAB

26 AFE79xx Configuration Guide SBAA417 – June 2020

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com JESD Configuration

1-FBCD
Note that the data rates of the channel corresponding to location and the mux value should be same.
5. SerDes TX Polarity (serdesTxLanePolarity):
Sets the Lane Polarity of the STX lanes.
6. SerDes TX Cursor Settings (serdesTxPreCursor, serdesTxPostCursor, serdesTxMainCursor):
These can be tuned to adjust STX eye.

3.2.5 ADC_JESD iGUI

To enable easier and interactive interface, iGUI is helpful.
First select the System Mode and then select the LMFSHd mode of the mapper. The blocks which are not
used will automatically be disabled. Clicking the updateObjects button will do the following:
1. Determine if the mode is valid. Check the log for any errors.
2. Highlight the data muxes with corresponding colors of the mapper to show the path the data takes.
3. Lane rates for each lane.
4. Show the data in each lane, both before and after the lane mux.

Figure 10. iGui for ADC JESD TX

SBAA417 – June 2020 AFE79xx Configuration Guide 27

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

JESD Configuration www.ti.com

3.3 DAC JESD RX Configuration

Figure 11. DAC JESD RX Functional Block Diagram

DAC_JESD has 2 instances, DAC_JESD_AB and DAC_JESD_CD. Each DAC_JESD instance has one
mapper for each channel. Potentially, each channel can support an independent data/lane rate, LMFSHd
mode, and link. However, present versions of Latte supports AB and CD acts as single mapper. That is,
below parameters, in case of mapper settings with 4 entries, only the parameter entries at index 0 and 2
are valid.
Key Blocks of the DAC JESD (Figure 9):
1. SerDes:
This is the physical layer responsible to receive the data from the lanes.
2. IP Layer:
This handles the JESD protocol and receives the lane data to the physical layer (SerDes).
3. JESD-DUC MUX:
This is the mux between the JESD block output to the interpolation chain input. This mux can only be
employed if the default and the new channel have the same interface rates. Note that the 1-1 to 1-8
refer outputs of the first instance of DAC-JESD and 2-1 to 2-4 represent the outputs of the second

28 AFE79xx Configuration Guide SBAA417 – June 2020

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com JESD Configuration

instance of DAC-JESD before JESD-DUC MUX.

4. De-Mapper:
This is responsible in remapping the lane wise data into the converter-wise data based on the LMFSHd
setting.
There are up to 4 CMOS sync signals (DAC_SYNC0/1/2/3). When LVDS sync mode is enabled,
DAC_SYNC0/2 can be used as LVDS SYNC, DAC_SYNC1/3 are used in conjunction with DAC_SYNC0/2
and cannot be used independently. All the sync signals which are needed have to be brought out on GPIO
pins. Refer to Section 4 for this.

3.3.1 DAC JESD IP Settings

See Section 10.2 for more information.
There are 4 for all the mappers which need to be on single link, same value must be set here. All the sync
signals which are needed have to be brought out on GPIO pins. Refer to Section 4 for this.
1. DAC JESD Mode (LMFSHdTx):
This is per mapper setting. By setting M=4 modes in single band case and M=8 modes in dual band
case, corresponding 2 channels are combined into a single mapper.
List of Supported Modes:
'24410', '14810', '14610', '24610', '1-4-12-1-0', '44210', '12820', '48410', '28810', '28610', '48610', '2-8-
12-1-0', '24820', '48310', '24310', '44310', '1-8-12-1-0' ,'1-8-16-1-0', '42111', '42220', '22210', '12310',
'22310' ,'12410', '12610', '48820', '4-16-8-1-0' ,'2-16-12-1-0' ,'4-16-12-1-0', '2-16-16-1-0', '1-1-6-24-1-0',
'1-8-24-1-0' ,'2-16-24-1-0', '12620', '24620', '48620', '22840', '44840'
2. DAC JESD Protocol (jesdRxProtocol):
This determines the protocol for ADC JESD. This is independent for the two instances of ADC_JESD.
3. DAC JESD K setting (jesdRxK):
K value programming per IP layer:
• JESD 204B (8b/10b): This is the number of frames in a multi-frame for JESD 204B. This supported
values are 8, 16, 24, 32.
• JESD 204C (64b/66b): This is the number of multi-blocks in an extended multi-block for JESD
204C. This should be chosen such that number of frames in an extended multi-block is integer.
That is, E*256/F should be an integer, that is,E=LCM(256,F)/256. Typically, for cases 16-bit modes
(F is a power of 2), this value should be 1. For 12/24-bit modes (F is a multiple of 3), this value
should be 3.
4. DAC JESD RBD setting (jesdRxRbd):
RBD value programming. This value should be less than the K value in case of 204B and less than 64
for 204C. This value depends on the sysref to LMFC counters for AFE and FPGA/ASIC.
5. DAC JESD SCR setting (jesdRxScr):
Scrambler value per IP layer. For all the mappers under single link, this must be into same value. It is
recommended to enable scrambler since it randomizes the data when repeated pattern is sent. This
can improve the link stability and also prevent any coupling spurs caused by repeating pattern on
SerDes lanes. For example, a long repeating pattern on SerDes causes 7th and 9th harmonics (among
others) of lane rate/20.
6. DAC JESD Sync Mux (jesdRxSyncMux):
Chooses the Sync Out signal per IP layer. When the same value is set for multiple mappers, the
corresponding mappers act as if together they are single mapper and single JESD core. This is to
select the sync_out function out of DAC_SYNC0/1/2/3. Supported values are 0 to 3. In LVDS sync
mode, values 1 and/or 2 are not supported as described above. For each index, the value is the
DAC_SYNC signal number. For all the mappers which must be on single link, same value must be set
here. When the same value is set for multiple mappers, the corresponding mappers act as if together
they are single mapper and single JESD core. Even though the Sync pins are needed only in JESD
204B protocol, this parameter is valid in 204C protocol also. In 204C, the IP waits for alignment of all
the lanes in a single link to move into data phase. This parameter determined what all channels are in
a single link.

SBAA417 – June 2020 AFE79xx Configuration Guide 29

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

JESD Configuration www.ti.com

Table 14. DAC JESD Sync Mux Mapping

Link Number jesdRxSyncMux GPIO function to map
CMOS-0 0 DAC_SYNC0 to any pin.
CMOS-1 1 DAC_SYNC1 to any pin.
CMOS-2 2 DAC_SYNC2 to any pin.
CMOS-3 3 DAC_SYNC3 to any pin.
LVDS-0 0 DAC_SYNC0 and DAC_SYNC1 to H9 and G9
respectively. jesdABLvdsSync=True. Note that
this setting is common for DAC_SYNC0-1 and
ADC_SYNC0-1.
LVDS-1 2 DAC_SYNC2 and DAC_SYNC3 to N9 and P9
respectively. jesdCDLvdsSync=True. Note that
this setting is common for DAC_SYNC0-1 and
ADC_SYNC0-1.

3.3.2 DAC JESD MUXES and MISELLANEOUS

See Section 10.2 for more information

1. DAC JESD Lane Mux (jesdRxLaneMux):

This chooses the SERDES lane (before the MUX, towards the SERDES) for each JESD lane (after the
MUX, towards the AFE). For example, if the 4th SERDES lane should be treated as 2nd JESD lane,
make the 2nd element in the array as 3. It is to be noted that there is no duplication allowed in this.
And hence, the list should always contain all values from 0-7.
2. DAC data Mux enable (dacDataMuxEn):
This enables the mux between DAC_JESD to DAC digital. Disabling this will use the default values.
3. DAC data Mux (txDataMux):
Choose what will come in each location for TX Channel. TX channels 0/1/2/3 are referred as A/B/C/D.
B0 is band 0 and B1 is band 1.
Location Meaning:
[A_B0, A_B1, B_B0, B_B1, C_B0, C_B1, D_B0, D_B1]
Value meaning:
0-A_B0
1-A_B1
2-B_B0
3-B_B1
4-C_B0
5-C_B1
6-D_B0
7-D_B1
Eg: To swap TXA Band 0 and TXC Band 1,
[5,1,2,3,4,0,6,7]
Note that the data rates of the channel corresponding to location and the mux value should be
same.
4. SerDes RX Polarity (serdesRxLanePolarity):
Sets the Lane Polarity of the SRX lanes.

3.3.3 DAC_JESD iGui

:
To enable easier and interactive interface, iGUI is helpful.
Select the LMFSHd mode of the mapper. The blocks which are not used will automatically be disabled.
Clicking the updateObjects will do the following:
1. Determine if the mode is valid. Check the log for any errors.
2. Highlight the data muxes with corresponding colours of the mapper to show the path the data

30 AFE79xx Configuration Guide SBAA417 – June 2020

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com JESD Configuration

takes.
3. Lane rates for each lane.
4. Show the data in each lane, both before and after the lane mux.

Figure 12. iGui for DAC JESD RX

3.4 JESD Common Settings

Usage format of the parameters is present in Section 10.2.
1. Serdes Firmware Enable (serdesFirmware):
This enables the SERDES firmware which performs the CTLE, PLL and DFE adaptations. It is
recommended that this is always set to True.
2. Enable the LVDS SYNC0 (jesdABLvdsSync):
This is common setting for ADC_SYNC0 and DAC_SYNC0. When this is enabled, the GPIO pins are
fixed. ADC_SYNC1 and DAC_SYNC1 are invalid.
3. Enable the LVDS SYNC1 (jesdCDLvdsSync):
This is common setting for ADC_SYNC3 and DAC_SYNC3. When this is enabled, the GPIO pins are
fixed. ADC_SYNC4 and DAC_SYNC4 are invalid.
4. Enable Hardware Sync (syncLoopBack):
If this is set, hardware sync loopback is enabled and hardware sync pins are used. Otherwise,
software sync can be used.

SBAA417 – June 2020 AFE79xx Configuration Guide 31

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

JESD Configuration www.ti.com

3.5 Case Study

3.5.1 Case 1
Consider a 4T4R1F TDD system with RX data rate of 368.64 MHz and TX and FB data rates of 737.28
MHz. All channels are with a single band, and all the RX channels are in single link, with all the FB
channels in a separate single link. If the user wants to set the configuration shown in Table 15 in the
JESD 204B protocol, follow these steps:

Table 15. Use Case 1 Configuration

CHANNELS DATA RATE (MHz) L-M-F-S-Hd LANE RATE (Mbps) NUMBER OF LINKS
4RX 368.64 4-8-4-1-0 14745.6Mbps All in 1 link
1FB 737.28 2-2-2-1-0 14745.6Mbps All in 1 link
4TX 737.28 8-8-2-1-0 14745.6Mbps All in 1 link

First consider at the ADC side. Since RXA and RXB are of same data rate and same link, go with
jesdSystemMode where rx2 mapper is not used. Since the user will need dedicated lanes for RX and FB,
jesdSystemMode 1 seems best fit. In this mode, entries 1 and 3 of the parameters do not matter and can
be kept same as 0 and 2, respectively.
1. jesdSystemMode: 0
2. LMFSHdRx:
4-8-4-1-0 is for 4 channels, for 2 channels it will become 2-4-4-1-0. (Need to half number of lanes (L)
and number of converters (M)).
[“24410”, “24410”, “24410”, “24410”]
3. LMFSHdFb: [“22210”, “22210”]. So that nothing breaks, good to put the same value for FB CD too.
4. jesdTxProtocol: Since it is 204B, the protocol value should be 0. [0, 0]
5. rxJesdTxSyncMux: [0,0,0,0]
Since all these channels are in a single link, all values should be same. For CMOS SYNC, keep this
value as 0 and bring ADC_SYNC0 to the required pin. In case of LVDS SYNC, keep this value as 0
and bring the ADC_SYNC0 and ADC_SYNC1 functions on the fixed pins.
6. fbJesdTxSyncMux:
[1,1] For CMOS Sync
[3,3] For LVDS Sync
Since all FB channels are in a single link, all values should be same and since FB link is different from
the RX link, the value of the sync mux should be different. For CMOS SYNC, keep this value as 1 and
bring ADC_SYNC1 to the required pin. In case of LVDS SYNC, keep this value as 0 and bring the
ADC_SYNC2 and ADC_SYNC3 functions to the fixed pins.
7. Lane Mux settings, K, scrambler can be set as needed.
On DAC side,

1. LMFSHdTx
8-8-2-1-0 is for four channels aggregate, for two channels aggregate it will become 4-4-2-1-0. (Need to
half number of lanes (L) and number of converters (M)).
LMFSHdTx = [“44210”, “44210”, “44210”, “44210”]
2. jesdRxProtocol: Since it is 204B, the protocol value should be 0. jesdRxProtocol=[0,0]
3. jesdRxSyncMux = [0,0,0,0]
Since all these channels are in a single link, all values should be same. For CMOS SYNC, keep this
value as 0 and bring DAC_SYNC0 to the required pin. In case of LVDS SYNC, keep this value as 0
and bring the DAC_SYNC0 and DAC_SYNC1 functions to the corresponding fixed pins (H9 and G9
respectively).
4. Lane Mux settings, K, scrambler can be set as needed.
The lane-wise ADC (assuming lane and data muxes are default) is shown below.

32 AFE79xx Configuration Guide SBAA417 – June 2020

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com JESD Configuration

Table 16. JESD Case Study 1: ADC Lane Mapping

LANE NUMBER DATA
STX1 RXA_I; RXA_Q
STX2 RXB_I; RXB_Q
STX3 FBAB_I
STX4 FBAB_Q
STX5 RXC_I; RXC_Q
STX6 RXD_I; RXD_Q
STX7 -
STX8 -

Table 17. JESD Case Study 1: DAC Lane Mapping

LANE NUMBER DATA
SRX1 TXA_I
SRX2 TXA_Q
SRX3 TXB_I
SRX4 TXB_Q
SRX5 TXC_I
SRX6 TXC_Q
SRX7 TXD_I
SRX8 TXD_Q

3.5.2 Case 2
Consider rates similar to case 1, but where the RXAB is one link and RXCD is another link. Similarly,
TXAB and TXCD are independent links. In this case, the user will need 3 SYNC IN pins (one each for
RXAB, RXCD and FBAB). Since AFE only has maximum of 2 LVDS pins, the user can either go with 2
LVDS sync and 1 CMOS sync, 1 LVDS sync and 2 CMOS syncs, or 3 CMOS sync. For this example,
assume 3 CMOS sync for now. Note that LVDS control is common to ADC_SYNC0 and DAC_SYNC0.
Except for the settings listed below, all other settings remain same.
1. rxJesdTxSyncMux: [0,0,1,1]
2. fbJesdTxSyncMux :
[3,3] For LVDS Sync
ADC_SYNC2 should be brought on to the required pins.
3. jesdRxSyncMux :
[0,0,1,1]
DAC_SYNC0 and DAC_SYNC1 should be brought on to the required pins (H9 and G9 respectively).

3.5.3 Case 3

Consider a 4T4R2F TDD system with RX data rate of 245.76 MHz and TX and FB data rates of 983.04
MHz. All channels are with single band, and all the RX channels are in single link with the FB channels as
a separate link. If the user wants to use the same configuration listed in Table 18 in the JESD 204C
protocol, follow these steps:

Table 18. Use Case 3 Configuration

Channels Data Rate (MHz) L-M-F-S-Hd Lane Rate (Mbps) Number of links
4RX 245.76 2-8-8-1-0 16220.16 All in 1 link
FBAB 737.28 1-2-4-1-0 24330.24 All in 1 link
FBCD 491.52 1-2-4-1-0 16220.16 All in 1 link

SBAA417 – June 2020 AFE79xx Configuration Guide 33

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

JESD Configuration www.ti.com

Table 18. Use Case 3 Configuration (continued)

Channels Data Rate (MHz) L-M-F-S-Hd Lane Rate (Mbps) Number of links
4TX 737.28 4-8-4-1-0 24330.24 All in 1 link

First consider the ADC side. This gives a different case where RX and FB lane rates are different. As
mentioned in Section 3.1 and the lane mux description of Section 3.2, in a set of 4 SerDes lanes, only
ratios of 1, 2, 4, and 8 are supported. However, the RX lane rate to FB lane rate is 2:3. To work with such
a scenario, the user must employ lane mux to get all the supported lane rates into one set of 4 lanes. That
is, the 2 RX and FB CD lanes should be brought to any lanes out of STX1-4 or STX5-6, and FB AB lanes
should be brought to the lanes on the other SerDes Core.
The settings are:
1. jesdSystemMode = [0,0]
2. LMFSHdRx:
2-8-8-1-0 is for 4 channels, for 2 channels it will become 1-4-8-1-0. (Need to half number of lanes (L)
and number of converters (M)).
[“1-4-8-1-0”, “1-4-8-1-0”, “1-4-8-1-0”, “1-4-8-1-0”]
3. LMFSHdFb = [“1-2-4-1-0”, “1-2-4-1-0”]
4. jesdTxProtocol: Since this is 204C, the protocol value should be 2. jesdTxProtocol = [2,2]
5. rxJesdTxSyncMux = [0,0,0,0]
Doesn’t matter. Can put any value. No Sync pins are needed.
6. fbJesdTxSyncMux = [1,1]
Doesn’t matter. Can put any value. No Sync pins are needed.
7. jesdTxLaneMux:
Default Mapping is,
Lane 0: STX1: RXA & RXB
Lane 2: STX3: FBAB
Lane 4: STX5: RXC & RXD
Lane 6: STX7: FBCD
This can be muxed as(there are many other possibilities):
Lane 2: STX3: FBAB
Lane 4: STX5: RXC & RXD
Lane 5: STX6: RXA & RXB
Lane 6: STX7: FBCD
Lane mux becomes: [5,1,2,3,4,0,6,7]
8. K, scrambler can be set as needed. Recommended K (Also called E) is 1.
On the DAC side,
1. LMFSHdTx:
4-8-4-1-0 is for 4 channels, for 2 channels it will become 2-4-4-1-0. (Need to half number of lanes
(L) and number of converters (M)).
[“2-4-4-1-0”, “2-4-4-1-0”, “2-4-4-1-0”, “2-4-4-1-0”]
2. jesdRxProtocol: Since it is 204C, the protocol value should be 2.
3. jesdRxSyncMux: jesdRxSyncMux = [0,0,0,0]
Since all these channels are in a single link, all values should be same. No Sync pins are needed
to be connected.

34 AFE79xx Configuration Guide SBAA417 – June 2020

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com GPIO Configuration

Table 19. Lane-Wise ADC Data

LANE NUMBER DATA
STX1 -
STX2 -
STX3 FBAB_I; FBAB_Q
STX4 -
STX5 RXC_I; RXC_Q; RXD_I; RXD_Q
STX6 RXA_I; RXA_Q; RXB_I; RXB_Q
STX7 FBCD_I; FBCD_Q
STX8 -

Table 20. Lane-Wise DAC Data

LANE NUMBER DATA
SRX1 TXA_I; TXA_Q
SRX2 TXB_I; TXB_Q
SRX3 -
SRX4 -
SRX5 TXC_I; TXC_Q
SRX6 TXD_I; TXD_Q
SRX7 -
SRX8 -

4 GPIO Configuration

4.1 Introduction
To enable flexibility in the GPIO mapping and to handle a much higher number of functions which are to
be brought on to a limited number of GPIO pins, there is a generic mux inside device which enables the
GPIO functions to be mapped to any GPIO pins/balls.
There are 3 different types of mapping between functions and GPIO Balls:
1. No Preferred Mapping functions: Not timing critical. Can be put to any ball.
2. Preferred: Even if these functions are mapped to a different balls other than the preferred ones, the
functionality is ensured with an additional propagation delay up to a few ns.
3. Fixed: If these functions are mapped to another ball, these may potentially (not necessarily) impact the
functionality. For safe side, these are marked as fixed mappings.

SBAA417 – June 2020 AFE79xx Configuration Guide 35

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

GPIO Configuration www.ti.com

Figure 13. Functional Block Diagram for GPIO Block

The preferred or fixed balls for key functions are present in Section 10.3.
As shown in Figure 13 , the input and output functions are handled differently. When the GPIO is
configured as an input, the signal passes through the input functions mux and when it is configured as
output, it passes through the output functions mux. This enables broadcast feature for non-preferred input
and output functions. That is, a single GPIO ball can drive multiple input functions, and a single output
function can be brought on to multiple GPIO balls.

36 AFE79xx Configuration Guide SBAA417 – June 2020

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com GPIO Configuration

In some cases, multiple fixed/preferred mappings may be seen for single ball name. However, typically
only one of them can be used at a time. For example, the RXAB_DSA_GAIN0 and RXA_DSA_GAIN0
have same preferred Ball, F5. However, both can't be used at the same time since either of them are
different ways of controlling the DSA.

4.2 Key Points

Description of Function Groups:
1. MAIN: This contains all the commonly used functions.
2. SPIB1: SPIB1, this is optional additional SPI.
3. SPIB2: SPIB2, this is optional additional SPI.
4. INTAGC: This contains the functions related to AFE internal AGC mode of RX.
5. FBINTAGC: This contains the functions related to AFE internal AGC mode when FB chain is used as
RX.
6. EXTAGC: This contains the functions related to AFE external AGC mode of RX.
7. EXTAGC_GPIOMode1: There are two modes of RX DSA control through pins. This has 6-bit per
channel. It has a channel select and latch enable. First the DSA values are to be set and the channel
select between A/B or C/D must be selected using ‘_GAINSEL’ pin. On the rise edge of the
‘_GAINLEN’, the DSA will be updated.
8. EXTAGC_GPIOMode2: There are two modes of RX DSA control through pins. Each channel has a 3
pin DSA control.
9. FBEXTAGC: This contains the functions related to AFE external AGC mode when FB chain is used as
RX.
Points to Remember:
1. For LVDS Sync case, SYNC pins are fixed.
2. SPIA is fixed.

4.3 Configuring

4.3.1 Configuring Through Code

Format:
For mapping multiple input functions to same Ball,
sysParams.gpioMapping[‘<ballName>’] = [ ‘<function0Name>’,] ‘<function1Name>’]
Example: sysParams.gpioMapping['H8'] = ['TXATDD','TXBTDD']

For mapping Single input functions to same Ball,

sysParams.gpioMapping[‘<ballName>’] = <functionName>
Example: sysParams.gpioMapping['H8'] = ['TXATDD']

4.3.2 Configuring Through iGUI

1. First Select if to configure the pin as input or output.

2. Then select the function groups of interest (same names as per the configuration guide).
3. Select the Function to map the GPIO.
4. Click “Apply”. This maps the GPIO function to the Ball. Note that if it is Input Function, it will add to the
existing functions mapped to the ball (to enable a single ball to drive multiple functions). And if it is
output, it will replace the existing function, if any (since a single ball cannot be driven by more than one
function).

SBAA417 – June 2020 AFE79xx Configuration Guide 37

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

GPIO Configuration www.ti.com

Figure 14. iGui for GPIO Status

4.3.3 Miscellaneous Configurations

1. GPIO Override (gpioOverrideValSet):
By default any GPIO function which is not mapped to the pin is set default to 0. If the GPIO override
value is to be set to high, the function name should be added to this list. For example, if the FB AB and
FB CD TDD are to be set to high all the time, then the value of this should be
['FBABTDD','FBCDTDD',]
2. GPIO Polarity Inversion (gpioPolarityInv):
By default any GPIO function has no polarity inversion. If the GPIO polarity is to be inverted, the
function name should be added to this list. For example, if in a TDD system, FB should be on
whenever RX TDD is off (there is no idle state) and want to control both by same pin, RX TDD and
FBABTDD can be mapped to same pin and FBABTDD polarity can be inverted. Then the value of this
should be ['FBABTDD',]

4.3.4 Standard Configurations

Assignment of more than one function to a pin means a single GPIO controls all those functions. Note that
all these functions are input functions.
Internal AGC Mode:
intAgcMode={
"P14": "GLOBAL_PDN",
"N16": "ALARM1",
"N15": "ALARM2",
"H9": "DAC_SYNC0",
"G9": "DAC_SYNC1",
"H8": "ADC_SYNC0",
"H7": "ADC_SYNC1",
"H15": "TXATDD",
"V5": "TXCTDD",
38 AFE79xx Configuration Guide SBAA417 – June 2020
Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com GPIO Configuration

"E7": "RXATDD",
"R15": "RXCTDD",
"K14": "FBABTDD",
"R6": "FBCDTDD",
"G8": "RXA_AGC_FREEZE",
"G7": "RXB_AGC_FREEZE",
"T8": "RXC_AGC_FREEZE",
"T7": "RXD_AGC_FREEZE",
"G13": ["RXA_GSW","RXB_GSW","RXC_GSW","RXD_GSW"],
"D5": "RXA_LNABYPASS_B0",
"G10": "RXB_LNABYPASS_B0",
"T6": "RXC_LNABYPASS_B0",
"T5": "RXD_LNABYPASS_B0",
"N9": "DAC_SYNC2",
"P9": "DAC_SYNC3",
"N8": "ADC_SYNC2",
"N7": "ADC_SYNC3",
"G12": "SPIB1_SDO",
"H11": "INTBIPI_SPIB1_SDI",
"H16": "SPIB1_CSN",
"G16": "SPIB1_CLK",
}
External AGC Mode:
extAgcMode={
"P14": "GLOBAL_PDN",
"N16": "ALARM1",
"N15": "ALARM2",
"H9": "DAC_SYNC0",
"G9": "DAC_SYNC1",
"H8": "ADC_SYNC0",
"H7": "ADC_SYNC1",
"H15": "TXATDD",
"V5": "TXCTDD",
"E7": "RXATDD",
"R15": "RXCTDD",
"K14": "FBABTDD",
"R6": "FBCDTDD",
"G8" :"RXA_PKDET_0",
"G7" :"RXA_PKDET_1",
"H12" :"RXA_PKDET_2",
"G10" :"RXA_PKDET_3",
"C6" :"RXB_PKDET_0",
"F6" :"RXB_PKDET_1",
"E5" :"RXB_PKDET_2",
"G6" :"RXB_PKDET_3",
"T8" :"RXC_PKDET_0",
"T7" :"RXC_PKDET_1",
"N13" :"RXC_PKDET_2",
"M15" :"RXC_PKDET_3",

SBAA417 – June 2020 AFE79xx Configuration Guide 39

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

RX DSA, AGC and ALC www.ti.com

"R5" :"RXD_PKDET_0",
"P8" :"RXD_PKDET_1",
"T6" :"RXD_PKDET_2",
"T5" :"RXD_PKDET_3",
"J14": "RXA_DSA_GAIN_0",
"H13": "RXA_DSA_GAIN_1",
"E8": "RXA_DSA_GAIN_2",
"F7": "RXB_DSA_GAIN_0",
"F5": "RXB_DSA_GAIN_1",
"H10": "RXB_DSA_GAIN_2",
"R7": "RXC_DSA_GAIN_0",
"U5": "RXC_DSA_GAIN_1",
"P7": "RXC_DSA_GAIN_2",
"P6": "RXD_DSA_GAIN_0",
"L14": "RXD_DSA_GAIN_1",
"M14": "RXD_DSA_GAIN_2",
"G13": ["RXA_GSW","RXB_GSW","RXC_GSW","RXD_GSW"]
}

5 RX DSA, AGC and ALC

5.1 Introduction
In real world signal, the signal level at the input can change, and the engineer must ensure that the ADC
achieves the best dynamic range even when signal amplitude is above the full scale of the ADC or is too
lower than average signal power. For this purpose, a DSA (Digital Step Attenuator) is present in AFE
through which gain/attenuation of the signal to the ADC can be changed. The range of this DSA is 25dB in
steps of 0.5dB. There is also a need for controller which controls the DSA gain/attenuation based on
signal level. That is where Automatic Gain Controller (AGC) comes into picture. The primary purpose of
the AGC is to maintain the signal level at the input of the ADC within two levels (upper threshold and
lower threshold).
For this, detectors are used to identify if the signal is above the upper threshold or below the lower
threshold. If the signal is above the upper threshold, then the DSA attenuation increases by the step
value. If the signal is lower than the lower threshold, then the DSA attenuation decreases (by the step
value).
To give a wider range of signal level, external LNA control can be enabled. In this, either the complete
LNA gain or part of the gain can be bypassed whenever the DSA range cannot support the signal level.
That is, if the signal level at the input of the AFE pins for the maximum DSA attenuation is beyond the
upper threshold, LNA can be bypassed to reduce the signal level.
AFE has internal AGC and also has an option to use external AGC. There are multiple detectors which
are used to detect the signal level. AFE internal AGC can be configured to control the DSA and LNA
bypass. In the case of external AGC mode, the detector outputs can come on LSBs of data or pins and
can be used to control the DSA using SPI or pins.
In the system point of view, it would be important to know the signal level at the input of the AFE pins. The
DSA attenuation must be compensated for this. That is, the gain equivalent to the DSA attenuation must
be added to the data. However, this will increase the data width beyond 16 bits, which would be tough to
accommodate through JESD. This is solved either by changing the data format or by transmitting the gain
information either through the pins or LSBs. This is handled by Automatic Level Controller (ALC) or also
called Digital Gain Compensation (DGC).
AFE has RX DSA in steps of 0.5 dB to enable finer control. The register value, referred also as DSA
index, can be programmed to DSA attenuation in dB × 2.

40 AFE79xx Configuration Guide SBAA417 – June 2020

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com RX DSA, AGC and ALC

5.1.1 Detectors in AFE

AFE79xx has following detectors which can be used for internal or external AGCs.

Figure 15. Detectors in RX Digital Chain

5.1.1.1 Digital Peak Detectors

These are four independent and identical detectors present at the output of the ADC. These detectors can
see complete signal bandwidth (RF sampling) and have low latency.
• Big Step Attack
• Small Step Attack
• Big Step Decay
• Small Step Decay
The big and small step detectors are identical per design in AFE. Small step detectors are used for more
gradual increases in signal level, and the settings are chosen so. Big step detectors are used for faster
response, with larger steps of DSA change.

5.1.1.2 Principle of Operation for These Detectors

Thresh Blength CountThresh

Peak among Count the number of Detector

ADC Output > Thresh > Thresh
8 samples crossings in a block Output

Figure 16. Digital Peak Detectors

• Estimate peak over every 8 samples

• Compare the peak with programmable 12-bit thresholds to determine threshold crossing
• Number of threshold crossings is counted over a programmable block period and compared with a

SBAA417 – June 2020 AFE79xx Configuration Guide 41

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

RX DSA, AGC and ALC www.ti.com

number of hits threshold to determine that the detector has triggered.

• Attack detector will trigger if in the window length the number of the times in the signal is above the
threshold for more times than the programmed numHits.
• Decay detector will trigger if in the window length the number of the times in the signal is above the
threshold for less times than the programmed numHits.

5.1.1.3 RF Analog Detector

This is analog detector and is typically used for very fast attack and for direct LNA bypass. This detector is
present in analog pre-ADC, and has very fast response. However being implemented with analog circuitry,
it is relatively inaccurate and is optional to use.

5.1.1.4 Power Detectors

There is one power attack and one power decay detector in the AFE79xx. For a typical Wireless use case,
only the ADC peak detector is generally used.
• Same tap-off point as the ADC digital peak detector
• Programmable integration times from 10 ns up to 10 ms, and thresholds 0 to –30 dBFS
• Step Size < 0.2 dB
• It computes Average(AdcOut^2)
• Number of samples used for averaging is configurable anywhere from 2^3 to 2^23
• Separate detector for attack and decay

5.1.1.5 Band Detectors for Dual LNA

This is specifically for dual-band decimation chain case, with and internal AGC where there is one LNA
per band. In this case, the engineer must identify which bands are saturating the signal and what
combined signal is needed to bypass the corresponding LNA. For this, the detectors should look at the
signal only in the bands. The observation bandwidth for these detectors for different sampling and output
data rates is shown in Table 21.

Table 21. Bandwidths for Band Specific Detectors

FadcRx (MHz) DECIMATION FACTOR AGC OBSERVATION BW AROUND
NCO (MHz)
2949.12 8 400 (±200)
2457.6 10 400 (±200)
2949.12 12 400 (±200)
2949.12 16 300 (±150)
2457.6 20 200 (±100)
2949.12 24 200 (±100)
2949.12 32 150 (±75)
2457.6 40 100 (±50)
2949.12 48 100 (±50)

42 AFE79xx Configuration Guide SBAA417 – June 2020

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com RX DSA, AGC and ALC

Figure 17. Controller Algorithm for Internal AGC

5.2 Common Controls

The AGC settings can be set. The format for setting the parameter is:
Format: sysParams.agcParams[chNo].<parameter>
Example: sysParams.agcParams[chNo].agcMode

SBAA417 – June 2020 AFE79xx Configuration Guide 43

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

RX DSA, AGC and ALC www.ti.com

The peak of signal over 8 samples is compared with the threshold. For the attack detector, if the number
of times the signal is above the threshold over a window length is more than the programmed number of
hits, the detector is triggered. For the decay detector, if the number of times the signal is above the
threshold over a window length is less than the programmed number of hits, the detector is triggered. This
triggered outputs are brought on to pins in case of external AGC mode and are used by the internal
controller in the internal AGC mode.
Some controls are (Table 32):

1. AGC Mode (agcMode):

Choose the mode of operation of AGC. Note that this is common control for 2RX.
0- disabled
1- Internal AGC
2- External AGC SPI based DSA control
3- External AGC Pin based DSA control (4-pin mode)
4- External AGC Pin based DSA control (8-Pin mode)
2. Detector enables (atken, decayen):
Enable the required attack and decay big step, small step, and/or power detectors.
3. Threshold (atkthreshold, decaythreshold):
This is the threshold for each of the detectors.
4. Window Length (atkwinlength, decaywinlength):
Window length of the detectors.
5. Num Hits (atkNumHitsAbs, decayNumHitsAbs):
Number of hits threshold for each of the detectors.
6. RF Detector Mode (custRfMode):
This is to determine how the RF analog detector is to be used.
0: extAgc: Use RF analog detector in External AGC.
1: bigStepAtk: Use RF analog detector as very big step attack in internal AGC. In this mode, the DSA
is changed on RF detector trigger and LNA bypass (in case LNA control is enabled) happens on DSA
attenuation reaching the maximum attenuation.
2: lnaBypass: Use RF analog detector for external LNA bypass in internal AGC. In this case, the LNA
is automatically bypassed on RF detector trigger.
7. RF detector Enable (rfdeten):
Use RF detector for internal AGC. To let RF detector be used by internal AGC.
8. RF detector Number of hits (rfdetnumhits):
Absolute Number of times signal crosses threshold above which attack is declared
9. RX Gain Swap:
For cases where the RX DSA must be set to a particular value, say for some system level calibration,
there is a feature in AFE called gain swap. When this is set, the value in rx_swap_setting_A/B/C/D_0
register will be taken as DSA index, irrespective of the AGC mode. Gain swap GPIO function(s),
RXA/B/C/D_GSW, must be brought on to the GPIO. In the internal AGC mode, this also freezes the
internal AGC along with changing DSA index to above register-based value.

5.3 Internal AGC Controls

Usage format of the parameters is present in (Table 32).
1. Step Size (atksize, decaysize):
Whenever some detector triggers, this step size mentions the DSA change that needs to happen in the
appropriate direction.
2. RF detector step size (rfdetstepsize):
Whenever RF analog detector triggers, this step size mentions the DSA change that needs to happen
in the appropriate direction.
3. Minimum DSA attenuation (minDsaAttn):
Minimum DSA attenuation used by AGC. This setting can be changed dynamically to adjust for the
temperature variation of LNA.
44 AFE79xx Configuration Guide SBAA417 – June 2020
Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com RX DSA, AGC and ALC

4. Maximum DSA attenuation (maxDsaAttn):

Maximum DSA attenuation used by AGC. This setting can be changed dynamically to adjust for the
temperature variation of LNA.
5. GPIO reset Enable (en_agcfreeze_pin):
There is a feature to freeze the RX AGC using a pin. When this is enabled, the
RXA/B/C/D_AGC_FREEZE functions must be brought on to the pins. Refer to Section 4 on how to do
this.
Another alternative for this is to use the gain swap function. Setting the gain swap function freezes the
AGC (in case internal AGC mode is enabled) and sets the DSA value to a register based value.
The difference between gain swap and freeze is that the gain swap will set the DSA setting to a
register-based value, while the freeze will hold the DSA value to the current state.
6. Response to TDD (tdd_freeze_agc):
This determines the way the AGC must react to TDD. With TDD OFF, the AGC can either be reset or
frozen. If it is in reset mode, then at the TDD off to on transition, the DSA value goes to default DSA. If
it is in frozen mode, then the previous value of the DSA will be held and will be carry forwarded into the
new TDD cycle.

5.3.1 Internal AGC LNA Control (for Single LNA Case and Common Controls)

1. Enable LNA control (lnaEn):

External LNA Control in Internal AGC mode. Note that based on if it is single or dual LNA mode, the
corresponding GPIO functions need to be brought on to the pins. (RX[A/B/C/D]_LNABYPASS_B[0/1])
A/B/C/D are the channels and the B0 and B1 correspond to band 0 and band 1.
2. Enable LNA control (singleDualBandMode):
Whether to use Single LNA control or dual LNA control in dual band configuration.
3. External LNA Gain and phase(lnagain0, lnagain1, lnaphase0, lnaphase1):
For the internal AGC and ALC to compensate for the external LNA bypass/enable, internal AGC needs
to know the external LNA gain. This is the setting (lnagain0, lnagain1). Similarly, for the LNA status not
to impact the signal chain phase, the effective phase of the LNA can be compensated by setting the
parameter (lnaphase0, lnaphase1). This phase is added to the signal when LNA is bypassed. In case
of single LNA mode, (lnagain1 and lnaphase1) can be ignored.
4. Blanking time for external component (blank_time_extcomp):
When the LNA is bypassed/enabled, there is a finite time between LNA status change by the AGC
controller to the time the signal reaches AFE input after the status change. During this time, the AGC
should ignore at the signal to prevent incorrect operation. This time is to be set to the internal AGC.
5. LNA Gain Margin (lnaGainMargin):
This is the Gain Margin which is used to determine when to enable the LNA. This is the hysteresis gap
between the Gain LNA enable and LNA disable. A typical good value for this is 2 dB.

5.3.2 Internal AGC LNA Control (for Dual LNA Case)

1. Dual LNA mode (dualLnaMode):

Whether to use LNA detectors as decay detectors or let the loop control the mode of detectors.
2. Dual LNA Approach (dualLnaDsaApproach):
Whether AGC should be conservative or aggressive.
3. Dual LNA Decay Threshold (dualLnaDecayThB0, dualLnaDecayThB1):
Decay threshold for LNA 0/1 detector.
4. Dual LNA Decay Mode for Number of Crossings (dualLnaDecayNumCrossingMode):
This is whether to define the number of crossings as a percentage of Window Length or absolute
number of crossings for LNA decay detectors. This is just to select the nomenclature to program and
does not have an implication on the functionality.
5. Dual LNA Decay Number of Crossings (dualLnaDecayNumCrossingsB0,
dualLnaDecayNumCrossingsB1):
Number of crossings to declare decay for LNA 0/1 detector. The units of the value depends on the
SBAA417 – June 2020 AFE79xx Configuration Guide 45
Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

RX DSA, AGC and ALC www.ti.com

dualLnaDecayNumCrossingMode.
6. Dual LNA Attack Mode for Number of Crossings (dualLnaAtkNumCrossingMode):
This is whether to define the number of crossings as a percentage of Window Length or absolute
number of crossings for LNA decay detectors. This is just to select the nomenclature to program and
doesn’t have an implication on the functionality.
7. Dual LNA Decay Number of Crossings (dualLnaAtkNumCrossingsB0, dualLnaAtkNumCrossingsB1):
Number of crossings to declare attack for LNA 0/1 detector. The units of the value depends on the
dualLnaAtkNumCrossingMode.

5.4 Automatic Level Controller (ALC)

ALC can work irrespective of it being internal AGC or external AGC mode. It is dependent only on the
current DSA setting. In the internal AGC Dual LNA mode, each band is compensated with corresponding
LNA gain, on its bypass. There are multiple modes for ALC.

5.4.1 Floating Point Mode

In this mode, the data is changed from fixed to “Sign-Exponent–Significand” floating point format.
There are multiple formats in floating point mode:
1. 1-bit Sign, 2-bit Exponent, 13-bit Mantissa(Significand)
2. 1-bit Sign, 3-bit Exponent, 12-bit Mantissa(Significand)
3. 1-bit Sign, 4-bit Exponent, 11-bit Mantissa(Significand)
An appropriate mode must be chosen to represent the complete attenuation range of operation.

5.4.2 Format Decoding

S = sign, S ∈ {0, 1}
E = exponent, 0 ≤ E ≤ 2w-1, where w = width of the exponent field
T = significand, 0 ≤ T ≤ 2t-1, where t = width of the significand field = 16 – w - 1
p = t + 1 = precision of the floating point number in bits
Option 1 (fltPtMode=0):
For E = 0, the sample value v = (-1)S·T, that is, ABS(v) < 2t,
For E > 0, sample value v = (-1)S·(2t+T)·2E-1, i.e. ABS(v) ≥ 2t
Option 2 (fltPtMode=1):
For all values of E, sample value = v = (-1)S·(2t+T)·2E-1

5.4.3 Coarse Fine Mode

In this mode, the gain to be added is divided into fine gain (which is directly added to the signal) and
coarse gain (which is transmitted through LSBs or pins).
The coarse gain is not transmitted directly but is transmitted as an index which multiple by a configurable
step gives the actual gain.
For example, if the coarse step is programmed as 6dB, and the coarse index is 2, then the actual signal
level is the signal received through JESD with 12 dB (6 × 2) gain added.
This coarse index can be transmitted either through pins or LSBs.
Supported modes for LSBs:
1. 2-bit Coarse Index, 1 LSB of I and Q
2. 3-bit Coarse Index, 2 LSB’s of I and Q
3. 4-bit Coarse Index, 2 LSB’s of I and Q

46 AFE79xx Configuration Guide SBAA417 – June 2020

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com RX DSA, AGC and ALC

4. 2-bit Coarse Index, 2 LSB’s of I(and repeated on Q)

5. 3-bit Coarse Index, 3 LSB’s of I(and repeated on Q)
When the index is spread across I and Q (not repeated), I has the MSB and Q has LSB by default. The
appropriate mode must be chosen to represent the complete attenuation range of operation.

5.4.3.1 Configuring
See Table 32 for more information

1. Enabling ALC (alcEn):

When this is enabled, the compensation happens based on the other settings. When disabled, no
compensation happens.
2. ALC Mode (alcMode):
Select the ALC mode between:
0: Floatingpoint: Floating point mode
2: coarsefineI: when the index is repeated on I and Q
3: coarsefineIQ: when the index is spread across I and Q.
3. Use Minimum attenuation AGC (useMinAttnAgc):
Just like the minimum attenuation in internal AGC, there is a minimum attenuation which can be
compensated by ALC. Typically this can be same as AGC minimum DSA attenuation. However, there
is a feature to independently set the ALC minimum attenuation. This setting is to choose between if to
use minimum attenuation from AGC of configured value.
4. Gain Range (totalGainRange):
This is the maximum DSA attenuation to be compensated by the ALC. Typically this can be equal to
the maxDsaAttn setting of the AGC.
5. Minimum attenuation ALC (minAttnAlc):
When the useMinAttnAgc is set to 0, this is the minimum attenuation compensated by ALC. The
compensation applied by ALC will be the current DSA attenuation—the ALC minimum attenuation (this
is true either for useMinAttnAgc 0 or 1). If this value is more than the current DSA attenuation value, no
compensation is applied (this doesn’t affect format selected). If that was the case, however, then the
signal wouldn’t be enough to go beyond 16 bits, and therefore no data is lost. Gain information in this
case, however, may be lost, therefore the minimum attenuation of ALC should be less than or equal to
the minimum attenuation of the AGC.
6. Floating point mode (fltPtMode):
Valid only in floating point ALC mode. Choose to send MSB of mantissa always in Floating Point mode
of ALC.
7. Floating point format (fltPtFmt):
Valid only in floating point ALC mode. Choose the number of exponent and mantissa bits.
8. Coarse step (stepSize):
Valid only in Coarse-Fine ALC mode. Choose the coarse step size. An appropriate value must chosen
to represent the complete attenuation range of operation.
9. Number of bits for Coarse Index (nBitIndex):
Valid only in Coarse-Fine ALC mode. Choose the number of bits of coarse index. An appropriate value
must be chosen to represent the complete attenuation range of operation.
10. Signal Back-off (sigBackOff):
Valid only in Coarse-Fine ALC mode. This is the signal back-off, the offset attenuation applied.
11. Invert coarse index (indexInvert):
Valid only in Coarse-Fine ALC mode. Choose to invert coarse index in coarse fine on LSB mode of
ALC.
12. Swap coarse index (indexSwapIQ):
Valid only in Coarse-Fine ALC mode. Choose to swap coarse index on I and Q. Applicable in
CoarsefineIQ mode of ALC.

SBAA417 – June 2020 AFE79xx Configuration Guide 47

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

RX DSA, AGC and ALC www.ti.com

5.5 External AGC Mode

The detectors used in this case are same as those in Section 5.2. There are two aspects of using external
AGC mode. First is how the detector status is conveyed to the host and second is how the DSA is
controlled.
Detectors status can be brought on to pins either on LSBs or pins. There are 4 functions per channel
which can be brought on to GPIO available (RX[A/B/C/D]_PKDET_[0/1/2/3]).
There are multiple detector outputs which can be ORed to be brought on to these pins:

1. Digital power attack /decay

2. Digital Big/Small step attack/decay
3. OVR bit: This is the OR of analog (ADC saturation) and digital chain overload detector.
To get the detector outputs on to pins or LSB bit(s) of the JESD data, the corresponding parameters as in
Table 22 need to be set. The same data as pin comes on to the LSB bit(s) of the JESD data. If the pin
output is not needed, the GPIO function need not to be mapped to GPIO pins. If pins are needed, the
corresponding functions (RX[A/B/C/D]_PKDET_[0/1/2/3]) are to be brought on to the GPIO. (refer to
Section 4). If the LSB output is needed, pkDetPinLsbSel/pkDetOnPenultimateLsb should be set to True.
Otherwise, they have to be made 0.
To control the DSA, there are 3 modes.
1. SPI: This way DSA can be changed through SPI. It is possible to use any of the SPIA/SPIB1/SPIB2.
2. 4-pin DSA control: In this mode, there are 4 pins per RX channel which can be used to set the DSA
value. To allow covering larger DSA change, there are step and init values. The effective DSA index
would be ((pin value × step) +offset). And since the DSA in 0.5-db steps, the effective DSA attenuation
would be ((pin value * step) +offset) × 0.5 dB.
3. 8-Pin DSA control: In this mode, there are 8 pins per 2RX to set the DSA. Out of the 8 pins, 6 pins
correspond to the value of the DSA, 1 pin to select the channel between the 2RX, and 1 pin to latch
the DSA value.
GPIO function under Group: EXTAGC_GPIOMode1 must be brought on to the pins as needed.

Table 22. External AGC Detector Information on LSB and Pins

Configuration Parameter to be set (to 1) to bring GPIO Function
Position on LSB
Parameter the value onto LSB Output
RX[A/B/C/D]_PKDET
pin0sel I LSB (bit 0) pkDetPinLsbSel
_0
RX[A/B/C/D]_PKDET
pin1sel I LSB (bit 1) pkDetOnPenultimateLsb
_1
RX[A/B/C/D]_PKDET
pin2sel Q LSB (bit 0) pkDetPinLsbSel
_2
RX[A/B/C/D]_PKDET
pin3sel Q LSB (bit 1) pkDetOnPenultimateLsb
_3

5.5.1 Configuring

1. Pin or LSB outputs (pin0/1/2/3sel):

Choose what are the functions which are to come on to the pins/lsbs. The OR of all the detector
outputs comes on to the pins. None of the pins are sticky, which means that they automatically clear
when the detector trigger is released.
Each Pin/LSB can be configured to carry ORed combination of selected bits. Setting a particular bit
gets the detector on to the corresponding pin/LSB.

48 AFE79xx Configuration Guide SBAA417 – June 2020

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com RX DSA, AGC and ALC

Table 23. Bit Wise Mapping for Pin/LSB outputs of External AGC
BIT NO DETECTOR DESCRIPTION
14 OVR Bit OR of analog and digital overload.
13 Band 0 power detector Power detector for band 0. For only in dual band
case.
12 Band 0 peak detector Peak detector for band 0. For only in dual band
case.
11 RF detector RF Analog Detector.
10 Band 1 power detector Power detector for band 1. For only in dual band
case.
9 Band 1 peak detector Peak detector for band 1. For only in dual band
case.
8 Reserved (0) Reserved. Keep it 0.
7 Digital big step attack Big Step Attack detector at the output of the ADC.
6 Digital small step attack Small Step Attack detector at the output of the
ADC.
5 Digital big step decay Big Step decay detector at the output of the ADC.
4 Digital small step decay Small Step decay detector at the output of the
ADC.
3 Dig power attack Power Attack detector at the output of the ADC.
2 Dig power decay Power decay detector at the output of the ADC.
0/1 Reserved (0) Reserved. Keep it 0.

2. LSB select (pkDetPinLsbSel):

Choose if the data or the detector information needs to come on to bit 0. This is common for I and Q.
3. Penultimate LSB select (pkDetOnPenultimateLsb):
Choose if the data or the detector information needs to come on to bit 1. This is common for I and Q.
4. 4-pin DSA control:
To enable this mode, agcMode must be set to 3 and the GPIO functions in function group
EXTAGC_GPIOMode2 must be brought on to the pins. You can also set dsaStep, dsaInit and
maxDelay parameters. In case you want to program fewer pins for DSA control, you can have only the
corresponding pins on to the GPIOs and override the other pins to required values.
RX[A/B/C/D]_DSA_GAIN_0 is the LSB and RX[A/B/C/D]_DSA_GAIN_3 in MSB.
5. 8-Pin DSA control:
To enable this mode, agcMode must be set to 4 and the GPIO functions in function group
EXTAGC_GPIOMode1 must be brought on to the pins. In case you want to program fewer pins for
DSA control, you can have only the corresponding pins on to the GPIOs and override the other pins to
required values. For example, if you want 1-dB step DSA control, you can override the corresponding
LSB GPIO function to 0 and connect the remaining functions to GPIOs.
RX[AB/CD]_DSA_GAIN_0 is the LSB and RX[AB/CD]_DSA_GAIN_5 in MSB.
Using 10 pins to control all the channels’ DSAs, instead of 16 pins, is also possible. To do this, the
functions RXAB_DSA_GAIN_[0-5] and RXCD_DSA_GAIN_[0-5] can be connected to the same GPIO
pins. However, you will need independent GAINSEL and LEN (Latch Enable) pins for AB and CD. In
this case, you can use the same pins for all the channels to set the DSA index. The appropriate
channel, the corresponding GAINSEL, and corresponding LEN must be set.

Table 24. 8-Pin External AGC Mode: Pin Mapping

RXAB_DSA_GAINSEL RXAB_DSA_GAINLEN RXCD_DSA_GAINSEL RXCD_DSA_GAINLEN
RXA 0 Transition from 0 to 1 to X X
0
RXB 1 Transition from 0 to 1 to X X
0
RXC X X 0 Transition from 0 to 1 to
0

SBAA417 – June 2020 AFE79xx Configuration Guide 49

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

RX DSA, AGC and ALC www.ti.com

Table 24. 8-Pin External AGC Mode: Pin Mapping (continued)

RXAB_DSA_GAINSEL RXAB_DSA_GAINLEN RXCD_DSA_GAINSEL RXCD_DSA_GAINLEN
RXD X X 1 Transition from 0 to 1 to
0

6. Step Value of DSA (dsaStep):

Valid only in 4-pin DSA control mode. This is the step value for the pin-based DSA.
7. Offset Value of DSA (dsaInit):
Valid only in 4-pin DSA control mode. This is the offset value for the pin-based DSA.
8. Delay Value of pins (maxDelay):
Valid only in 4-pin DSA control mode. This is the delay after the change of pin change to latch the
values. This is to account for the latency variation between pins. This should be the maximum latency
variation between the earliest pin and the last pin. This is the common control for 2RX. The unit is in
cycles of FadcRx/8 clock.
9. Reliability Detector:
Reliability detector is present in the AFE to protect the ADC from very high signal levels. It is a non-
programmable detector. This can be brought out on to the pins by connecting GPIO functions
RELSTATUS_RXA0, RELSTATUS_RXB0, RELSTATUS_RXC0, RELSTATUS_RXD0 on to the pin for
RXA/B/C/D and RELSTATUS_FBAB0/ RELSTATUS_FBAB1 for FBAB/FBCD.

5.6 Choosing Settings for AGC

The key parameters to choose for a detector are:
• Threshold (atkthreshold/decaythreshold)
• Window Length (atkwinlength/decaywinlength)
• Number of Hits (atkNumHitsAbs/decayNumHitsAbs)
The threshold can be chosen based on the signal characteristics. The window length can be chosen as a
multiple of the data packet length, if any. The parameter input is in ns. So the number of samples in the
window is,

(winlength*FadcRx)/(1000*ddcFactor)

For example, the FadcRx is 2949.12MHz, DDC Factor is 8 and the atkwinlength is 150, there would be 56
samples in the window.
The Number of Hits threshold to trigger the detector output is say, NumHitsAbs. So clearly, the

NumHitsAbs<floor((winlength*FadcRx)/(1000*ddcF
actor))

If this condition is not met, then the AGC will not trigger an output since the number of samples greater
than the threshold can never be greater than NumHitsAbs.

5.6.1 Important information for the AGC

1. The two digital (small step and big step attack/decay) detectors can be used together.
2. The threshold for the small step attack is lower than the threshold for the big step attack.
3. The window length for the big step attack should be smaller than the small step attack.
4. The threshold for the small step decay is higher than the threshold for the big step decay.
5. The window length for the big step decay should be smaller than the small step decay.
6. The window length of the decay detectors should be higher than the attack detectors.
7. Ensure that the window length of the decay is not higher than the TDD ON-time in the cycle.
8. Though there are analog detectors present in the analog, they are relatively inaccurate. These can be

50 AFE79xx Configuration Guide SBAA417 – June 2020

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com DSA Calibrations

used for very high signal levels.

9. By default the LNA and DSA settings carry forward from the previous TDD ON cycle in case of TDD
toggle. The AGC automatically freezes when TDD is OFF. This is the recommended setting.

6 DSA Calibrations

6.1 RX/FB DSA Calibration

Analog RX/FB DSA can have small errors in gain and phase. These errors depend on the frequency of
operation, the board matching, and can vary from device to device. It is for these reasons why this
calibration must be done in the customer factory. This calibration generates a packet which has correction
information and must be stored in the host and loaded each initialization of the AFE.

6.1.1 Configuration
See Table 34 for more information.
1. enableRxDsaCalibration:
Setting this to True does the DSA calibration as part of bring up. Alternatively, to run the DSA
calibration as a separate sequence, the function AFE.doRxDsaCalib(rxChainForCalib,
fbChainForCalib) can be called after the setting the below parameters and running the bringup. Here,
rxChainForCalib is bit wise enable for RX (bit0-RXA, bit1-RXB, bit2-RXC, bit3-RXD) and
fbChainForCalib is bit wise enable for RX (bit0-RXAB, bit1-FBCD).
2. rxDsaCalibMode:
Number of channels to calibrate at a time. Setting this to 0 will run one channel at a time and setting it
to 1 will run A&C simultaneously and then B&D simultaneously. the channels being currently calibrated
need to have signal at the input. Note that, having signal at the channels not being currently calibrated
is okay. For calibrating all the channels optimally, we can externally connect to the signal to all
channels, set this to mode 1.
3. rxDsaBandCalibMode:
Number of bands of a channel to calibrate at a time. This is valid only in dual band cases. 0-Calibrates
each band of the current channels (set by rxDsaCalibMode) being calibrated sequentially. 1-Calibrates
both the bands of the current channels simultaneously. Note that in case where bands are being
calibrated sequentially, giving signal in the current band is needed. But in simultaneous mode, one
tone for each band should be given to the ADC at the same time. The log generated contains
comments with "EXTERNAL-ACTION" tag which points the location in the sequence and the
connection to be made.
4. rxDsaGainRange:
Range of RX DSA to calibrate. This can be similar to the AGC minimum () and maximum DSA
attenuation () in case of internal AGC.
5. useTxForCalib:
This for cases where TX chain instead of external signal source is to be used for calibration. TX output
should still be looped through an external component to the AFE RX input.
6. rxDsaCalibPacket:
This is path in which to store the read DSA calibration packet during EVM evaluation. The file will be
saved as a test file with the read packet data in hex, with one byte printed per line.
7. fbChainSelForDsaCalib: Select the FB Channels to calibrate.

6.2 TX DSA Calibration

Analog TX DSA can have small errors in gain and phase. These errors depend on the frequency of
operation, the board matching, and vary from device to device. It is for these reasons why this calibration
must be done in customer factory. This calibration generates a packet which has correction information
and must be stored in the host and loaded each initialization of the AFE.
Refer to DSA calibration App note on how to do the calibration.

SBAA417 – June 2020 AFE79xx Configuration Guide 51

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

Power Amplifier Protection (PAP) www.ti.com

6.2.1 Configuration
See Table 34 for more information

1. enableTxDsaCalibration:
Setting this to True does the DSA calibration as part of bring up. Alternatively, to run the DSA
calibration as a separate sequence, the function AFE.doTxDsaCalib(txChainForCalib) can be called
after the setting the below parameters and running the bringup. Here, txChainForCalib is bit wise
enable for TX (bit0-TXA, bit1-TXB, bit2-TXC, bit3-TXD).
2. txDsaCalibMode:
Number of channels to calibrate at a time. Note that the TX channel should be connected to the
corresponding FB during this time. The log generated contains comments with "EXTERNAL-ACTION"
tag which points the location in sequence and the connection to be made.
3. txDsaBandCalibMode:
Number of bands of a channel to calibrate at a time.
4. txDsaGainRange:
Range of RX DSA to calibrate. This can be similar to the AGC min-Max.
5. txDsaCalibPacket:
This is path in which to store the read DSA calibration packet during EVM evaluation. The file will be
saved as a test file with the read packet data in hex, with one byte printed per line.

7 Power Amplifier Protection (PAP)

7.1 Introduction
Sudden jumps in data or high-power output can potentially damage the power amplifier, and the DPD
must be frozen on any errors like JESD link errors and analog overload. To handle these scenarios, the
Power Amplifier Protection (PAP) block is present in the AFE. The PAP must be triggered whenever any
fault can cause a glitch in TX data, impact the TX data, or impact the FB data that must be used by DPD.
PAP must be triggered whenever:
1. TX Data-Based Trigger: Moving Average and High-Pass filter based.
2. DAC JESD loss of link
3. ADC JESD loss of link
4. PLL Loss of lock
5. FB ADC overload alarm
6. TX Digital overload alarm
The AFE79xx incorporates an optional power amplifier protection (PAP) block to monitor when the input
signal changes too fast and prevent it from reaching the PA. This is important to prevent damage to the
PA due to glitches or sudden change in signal. The PAP block achieves this through three main sub-
blocks: PAP detectors, a PAP gain state machine and PAP gain module. The locations of the PAP blocks
in the TX digital signal chain are shown in the below figure.

52 AFE79xx Configuration Guide SBAA417 – June 2020

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com Power Amplifier Protection (PAP)

Dual NCOs

NCO1 NCO2

Band Summation Dual NCOs

Power
Meter
IQ1 NCO5 NCO6
PAP N
Detector #1

PAP PAP
Interpolation Complex
Detector Gain DAC DSA
filters Mixers M
SUM Module

Power
Meter
IQ2
PAP N
Detector #2

NCO3 NCO4

Dual NCOs

PAP
State
Other triggers Machine

Figure 18. PAP Block in TX Chain

7.1.1 PAP Operation

PAP in total has 3 main sections.
1. PAP Detector: This is the block that detects an abnormal signal (that is, a signal with sudden changes)
and sends the trigger to state machine. How sudden the detection occurs depends on the
programming, which will be as discussed later. The three detectors (Band0 detector, Band1 detector
and the Sum detector) are identical in principle of operation.
2. PAP State Machine: This is the state machine which decides how to react to the trigger.
3. PAP Gain Module: This is the gain blocks which applies a gain to prevent the data from reaching the
DAC. It also handles bringing the signal back to the original state once the trigger is released.

7.1.2 PAP Detector and Triggers

To handle dual-band cases, there is one PAP detector per band and a detector to handle the combined
signal. The per-band detectors operate effectively at interface rate and the Sum detector operates at the
combining rate of the TX Digital chain (refer to Section 2.1 for the combining rate for each use case). In a
single band case, the detector of only the first band is used and in a dual band case, all the three
detectors are used. There are multiple kinds of PAP detectors and triggers present to trigger the state
machine. Required triggers can be unmasked to give to the state machine. Figure 19 shows a block
diagram for the same.

SBAA417 – June 2020 AFE79xx Configuration Guide 53

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

Power Amplifier Protection (PAP) www.ti.com

Figure 19. Triggers and Alarms to PAP

1. Average Power Trigger: This is a data-based trigger to detect when the signal power is above a
threshold. The abs of I+jQ over a window of some (maNumSamples) samples is taken and compared
with programmable threshold (maThresh). The number of the times the signal is over the threshold is
compared against a programmable count threshold (maWindowCntrTh) and if it is higher, the PAP
trigger will go high and if it is lower, the trigger will go low.
2. High-Pass Filter Based Trigger: This is a data-based trigger to detect when the signal changes too
fast. The abs or I+jQ is passed through a 6-tap high pass filter. This value over a window of some
(hpfNumSamples) samples is taken and compared with programmable threshold (hpfThresh). The
number of the times the signal is over the threshold is compared against a programmable count
threshold (hpfWindowCntrTh) and if it is higher, the PAP trigger will go high and if it is lower, the trigger
will go low.
3. Other Triggers:
It may be needed that some other errors also trigger the PAP state machine. These include:
a. JESD loss of lock:

54 AFE79xx Configuration Guide SBAA417 – June 2020

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com Power Amplifier Protection (PAP)

If there is a loss of link, this goes to the PAP state machine. The errors corresponding to the lanes
corresponding to the TX data is sent to PAP state machine. Particular JESD errors can be masked
or set to 0 using alarms_to_pap_mask (making either of them 1 will prevent the corresponding
alarm to go to PAP.) in the DAC_JESD page.
b. PLL Alarm:
In case of loss of PLL lock, this trigger goes to the PAP state machine. However, it is to be noted
that in case of PLL lock, operation of PAP is not guaranteed. For this it is better to bring the PLL on
to all the alarm pins and externally handle it.
c. Signal Overflow:
This is for case where the signal chain overflows because of large signal input to it.
d. PAP triggers from other channels:
In case where it is needed to trigger PAP for the corresponding TX channel when other channels
see a PAP trigger, this can be employed.
PAP State Machine:
Once the PAP trigger is generated by any of the above sources, the state machine moves to
“Attenuate” state, when the ramp down signal is given to the gain block. The data-path output is
then multiplied by the ramp down signal. Any PAP trigger in this time is not honored.
After attenuation is done, the PAP state machine moves into the Wait state. A programmable 16-bit
counter operating at FadcFb/4 clock rate is used in the Wait state. During the wait state, it can be
programmed if to detect any extra PAP triggers or not. If PAP triggers are set to detect in wait state,
any PAP trigger during this time will reset the WAIT counter and hence state machine continues to stay
in wait phase for the programmed wait time from that time. If PAP triggers detection during this state is
disabled, the state machine will look at PAP trigger state only at the end of the wait state. If the PAP
trigger is on in this time, it resets the WAIT counter.
After the wait time ends, the state machine moves to gain state. The signal measurement PAP triggers
(Average Power and Filter Triggers) continuously monitor the incoming signal and become OFF when
the measurements doesn't exceed the threshold anymore. All other PAP triggers require the
intervention of the Host to perform the necessary steps to clear the source of the error and then clear
the Triggers. Once again in the Gain state, the signal is multiplied by the ramp-up signal. In case, PAP
trigger occurs again during the gain phase, the attenuate phase is started from the current value of the
ramp down signal.

7.1.3 PAP Gain Block

Gain block handles the Attenuate and Gain phases of the state machine.
In the “Attenuate” state, the ramp down of the signal can be done in one of two programmable modes:
• Linear ramp down: The gain step and time duration in a particular gain step for ramp down are all
programmable.
• Cosine Ramp down: Attenuation of the form (1+cosθ)/2 with θ going from 0 to π. The starting phase
and time duration in a particular phase value are all programmable.
The signal datapath works in the normal mode and is multiplied by the ramp down signal. In this mode,
the PA protection is achieved by ramp down as even the offending sample with attenuation is passed to
the PA.
The ramp-up is generated by the two modes:
• Linear ramp-up: Programmable ramp-up end and step. The end, step, and time duration for the ramp-
up are all different from the ramp-down values.
• Cosine ramp-up: the end phase and phase step are programmable and different from the cosine ramp
down values. If a PAP ON trigger occurs during the Gain state ramp-up then the state machine moves
to Attenuate state. The starting gain in the Attenuate state is equal to the value at which the Gain state
stopped.

SBAA417 – June 2020 AFE79xx Configuration Guide 55

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

Power Amplifier Protection (PAP) www.ti.com

Figure 20. PAP Timing Diagram When a Single PAP Trigger Occurs

56 AFE79xx Configuration Guide SBAA417 – June 2020

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com Power Amplifier Protection (PAP)

Figure 21. PAP Timing Diagram When Multiple PAP Triggers Occur

7.2 Using PAP

1. The delay from PAP trigger ON to starting ramp down is programmable and should be lower than the
latency of the chain between the detector block and the gain block.
2. The delay from PAP trigger OFF to starting ramp down is programmable and should be higher than the
latency of the chain between the detector block and the gain block.
3. The delays to be programmed depends on interpolation rates and can easily be found by experiment
by giving a fast-changing output which triggers the PAP and adjusting the delay so as not to see the
jump.
4. When NCO switching is done for TX, the detector is frozen for a few cycles to prevent false trigger.
5. The combined block is needed only in the dual-band case. In Single band case, only the detector in
the interface rate is to be used.

7.3 Configuration

7.3.1 Common Controls

Usage format of the parameters is present in Table 33.
SBAA417 – June 2020 AFE79xx Configuration Guide 57
Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

Power Amplifier Protection (PAP) www.ti.com

1. Enable the block (enable):

Enable the PAP block.
2. Gain Step Size (gainStepSize):
This the step size of ramp signal (which is multiplied with the data) during ramp up. This must be set
depending on the slew rate limitation of the PA.
3. Attenuation Step Size (attnStepSize):
This the step size of ramp signal (which is multiplied with the last good sample) during ramp down.
This must be set depending on the slew rate limitation of the PA.
4. Attenuation Update cycles (amplUpdateCycles):
This is the time domain wait time between each step time of the ramp up/down. This together with the
gain/attenuation step size determines the slope of the ramp signal, which is multiplied with data. This
must be set depending on the slew rate limitation of the PA.
5. Ramp sticky mode (rampStickyMode):
This is a factor of the control mechanism preferred. Typically, many of the aggressors of the PAP
alarm exist for short time and recovers automatically (say Data Based trigger or JESD bit errors). And
hence, the PAP trigger can be automatically released to let normal data to go through to the output.
The data recovery time of this method is faster. However, there is also an option to clear the PAP
alarm through SPI. This may be the preferred approach if you want to control when the data is again to
be transmitted.
6. Alarm pin sticky mode (alarmPinDynamicMode):
This is a factor of the control mechanism preferred. If this is in sticky mode, the PAP alarm which is
brought on to the pin acts as sticky bit. If this is in dynamic mode and PAP is the sole aggressor, the
alarm pin goes low whenever the PAP trigger is released. Note that, this being sticky or not doesn’t
impact the ramp up or ramp down but it only impacts the pin state.
In sticky bit approach, whenever the alarm occurs, the host needs to clear the sticky bit as an
acknowledgment of the alarm trigger. This is useful in cases where some operations outside AFE need
to be done on alarm trigger.
In dynamic approach, since there is no intervention by the host software needed, the alarm recovery is
faster. This would be useful especially if the alarm is used for a single operation like DPD freeze.
7. Attenuation Update cycles (triggerToRampDown):
This is the delay between getting PAP trigger to initiating the ramp down. This should be lower than
the latency of the interpolation chain and is expressed in number of FadcFb/4.
8. Attenuation Update cycles (triggerClearToRampUp):
This is the delay between PAP trigger clear to initiating the ramp up. This should be larger than the
latency of the interpolation chain and is expressed in number of FadcFb/4.
9. Wait Time (waitCounter): This is the wait time state after which the ramp up happens again.
10. Alarm Pulse width (alarmPulseGPIO):
Width of the pulse going to the pin. This is key when both rampStickyMode and
alarmPinDynamicMode are in dynamic mode. Since the pin auto clears, its pulse width would be
important to ensure the host catches the alarm. In this case it can also be used to ensure the pin is
high till the PAP state machine comes out of gain phase by programming this to ramp-down time +
wait time + ramp-up time.
11. PAP trigger Channel Mask (alarmChannelMask):
This is an option to trigger the PAP state machine of a channel whenever PAP triggers of other
channels. This is a bit wise field to mask the PAP triggers from other channels. If a bit is set to 1 for a
channel, the corresponding channel PAP trigger will be masked. Table 25 shows the interpretation of
bits for each channel.

Table 25. PAP alarmChannelMask mapping for Each Channel

CHANNEL BIT 3 BIT 2 BIT 1 BIT 0
TXA D C B A
TXB D C A B
TXC B A D C

58 AFE79xx Configuration Guide SBAA417 – June 2020

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com Power Amplifier Protection (PAP)

Table 25. PAP alarmChannelMask mapping for Each Channel (continued)

CHANNEL BIT 3 BIT 2 BIT 1 BIT 0
TXD B A C D

For example:
a. To get only the current channel PAP trigger to trigger the state machine, this value should be
0b1110 (mask all other channels’ triggers). This is a typical use case.
b. To trigger all the channels if any of the channels’ PAP state machine trigger, this value should be 0
for all the channels.
c. Say, we want to trigger TXA PAP state machine if any of TX A, TXB and TXC PAP triggers occur,
this value for TXA should be 0b1000.
12. PAP trigger Mask (alarmMask):
This is a 5-bit wide bit-wise field to trigger PAP state machine in case any other errors occur. It is good
to keep this value as 0 to let PAP state machine trigger by all the alarms.

Table 26. PAP alarmMask mapping

BIT NO ALARM DESCRIPTION
0 pll_alarm To trigger PAP when PLL loss of lock alarm
triggers.
1 Jesd_alarm This triggers if there are any errors in the
corresponding JESD lanes of the TX channel.
2 fifo_alarm This happens if any FIFO in the chain
overflows/underflows. Configuration takes care of
this and is not expected to trigger.
3 ovr_saturation_alarm This happens if there is a digital/analog overflow in
the TX chain.
4 Dual band detector alarm
5 Combined band det alarm

13. Ramp Up/Down mode (multMode):

This is the signal with which to multiply the incoming signal for ramp up/down. There are two options
for doing this, cosine and linear. In cosine ramp down case, a signal of the form (1+cosθ)/2 with θ
going from startVal to π is multiplied to the signal path. During ramp up, θ goes from π to 0. In linear
ramp down case, the signal is n where n changes from startVal to 0. During ramp up, this goes from 0
to 1.
14. Ramp Up/Down start value (rampDownStartVal):
This is the starting value for the ramp down. For cosine mode, the start phase in radians is (128-
rampDownStartVal)* π /128. For linear mode, (rampDownStartVal/128) is the start value. Good to keep
this as 128 to ensure that the ramp down starts from unity gain.
15. Detect in Wait State (detectInWaitState):
If this is 1, then the PAP trigger will be detected in the WAIT state and WAIT counter will reset. If this is
0, the PAP trigger will not be detected in the wait state and will be checked only at the end of wait
state.

7.3.2 Moving Average Based Detector

Usage format of the parameters is present in Table 33.
1. Enable (maEnable):
Enable the Moving Average detector block. If this is disabled, then this trigger is not used for PAP state
machine.
2. Thresholds (maThreshB0/maThreshB1/maThreshComb):
These are thresholds for the average power detectors of Band0, band1 and combined detectors, as a
percentage of full scale. In single band, only maThreshB0 is valid. In Dual Band, all the thresholds
matter.
3. Number of samples in a window (maNumSample):

SBAA417 – June 2020 AFE79xx Configuration Guide 59

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

Miscellaneous Functions www.ti.com

This is the number of samples in a window. The power is calculated over these number samples.
Supported values are 32, 64 and 128.
4. Number of windows (maWindowCntr):
This is the number of windows over which to compare the threshold. Valid range is 0 to 212 – 1.
5. Number of windows (maWindowCntrTh):
This is the threshold for the hit counter. If the average power over maWindowCntr windows is more
than this number, then the PAP state machine will be triggered. Valid range is 0 to 212 – 1. This should
be less than maWindowCntr.

7.3.3 High Pass Filter Based Detector

Usage format of the parameters is present in Table 33.
1. Enable (hpfEnable):
Enable the high pass filter based detector block. If this is disabled, then this trigger is not used for PAP
state machine.
2. Thresholds (hpfThreshB0/hpfThreshB1/hpfThreshComb):
These are thresholds for the HPF detectors of Band0, Band1 and combined detectors, as a
percentage of full scale. In single band, only hpfThreshB0 is valid. In Dual Band, all the thresholds
matter.
3. Number of samples in a window (hpfNumSample):
This is the percentage threshold with respect to full scale. Supported values are 4, 8 and 16.
4. Number of windows (hpfWindowCntr):
This is the number of windows over which to compare the threshold. Recommended value is 0.
5. Number of windows (hpfWindowCntrTh):
This is the threshold for the hit counter. If the average power over hpfWindowCntr windows is more
than this number, then the PAP state machine will be triggered. Recommended value is 0.

8 Miscellaneous Functions

8.1 SPIB1/SPIB2
SPIA is the primary SPI which is the only available SPI available on reset. However, there are 2 other SPI
interfaces, SPIB1 and SPIB2, which can be used to control the AFE. This can be configured by bringing
these on to GPIO. (Refer to Section 4).
However, there are a few constraints on using multiple SPIs
1. More than one SPI cannot access the global page (addresses <0x20) simultaneously.
2. More than one SPI cannot access the same page simultaneously.

8.2 TX DSA Control

The TX DSA Control is generally used to compensate for PA gain variation with temperature and time.
The TX DSA has analog and per-band digital gain components. The analog component is of 1-dB steps
from 0-dB to –29-dB gain, and the digital component is of 0.125-dB steps from +3-dB to –28.875-dB gain.
To prevent unwanted sudden step changes in the signal level, the digital and analog components are
applied simultaneously, whenever the analog gain is set. Adjusting TX DSA attenuation can be done
through SPI. However, there is also a gain swap feature by which the DSA setting can be swapped
another value through pin. For this, the TX the functions TX[A/B/C/D]_GSW have connected to GPIO pins.
If you want gain swap of multiple channels to be tied together, this can be done by assigning
corresponding functions to single GPIO pin.
When the gain swap is low, the TX DSA value is taken from txa/b_dsa_index (analog DSA control) and
txa/b_dsa_dig0/1_gain (digital DSA control) registers of DSA_0 page. When the swap pin is high, the
attenuation is taken from txa/b_dsa_index_swap (analog DSA control) and txa/b_dsa_dig0/1_gain_swap
(digital DSA control) registers of DSA_1 page. The dig0/1 corresponds to band number and dig1 can be
ignored for single band case. The swap DSA attenuation can also be changed dynamically.

60 AFE79xx Configuration Guide SBAA417 – June 2020

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com Miscellaneous Functions

8.3 FB DSA Control

FB DSA can be controlled through SPI using the registers. In 6R mode, in which all the channels are in
RX mode, the FB has its internal AGC, similar to the RX internal AGC mode. External AGC mode is also
supported in FB but the DSA control is only through SPI. The operation is through SPI.
There is one other feature to control the DSA attenuation based on pins. This can be used for cases
where the FB DSA setting needs to be set based on the TX connected to it. This can be configured using
the following parameters (Table 37).
1. fbDsaPerTxEn:
This should be True to enable this feature and False to disable it.
2. fbDsaPerTx:
This sets the FB DSA index for each of the 4 pin states. This parameter gets mapped to registers
spi_agc_dsa_fb_0/1/2/3 of "DSA Page 0" of AB and CD depending on txToFbMode.
3. txToFbMode:
Depending on which FB channel(s) are being used, the corresponding mode should be set. Value of 0
means only FBAB is being used, 1 means only FB CD is being used and 2 means both FBAB and
FBCD are being used.
4. GPIO Functions:
GPIO functions TX_FB_LOOP0/1/2/3 should be brought onto the pins.

Table 27. FB DSA Pin Based Switching

txToFbMode TX_FB_LOOP3 TX_FB_LOOP2 TX_FB_LOOP1 TX_FB_LOOP0 State
First value of fbDsaPerTx
0 0 0 0 will be applied to FBAB
DSA index.
Second value of
0 0 0 1 fbDsaPerTx will be applied
to FBAB DSA index.
Third value of fbDsaPerTx
0 0 1 0 will be applied to FBAB
DSA index.
0
Fourth value of
0 0 1 1 fbDsaPerTx will be applied
to FBAB DSA index.
x 1 x x The value of the default
DSA setting register
spi_agc_dsa_fb of Page
1 x x x "DSA Page0 AB" will be
applied to FBAB DSA
index.
First value of fbDsaPerTx
0 0 0 0 will be applied to FBCD
DSA index.
Second value of
0 0 0 1 fbDsaPerTx will be applied
to FBCD DSA index.
Third value of fbDsaPerTx
0 0 1 0 will be applied to FBCD
1 DSA index.
Fourth value of
0 0 1 1 fbDsaPerTx will be applied
to FBCD DSA index.
x 1 x x The value of the default
DSA setting register
spi_agc_dsa_fb of Page
1 x x x "DSA Page0 CD" will be
applied to FB DSA index.

SBAA417 – June 2020 AFE79xx Configuration Guide 61

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

Miscellaneous Functions www.ti.com

Table 27. FB DSA Pin Based Switching (continued)

txToFbMode TX_FB_LOOP3 TX_FB_LOOP2 TX_FB_LOOP1 TX_FB_LOOP0 State
First value of fbDsaPerTx
x x 0 0 will be applied to FBAB
DSA index.
Second value of
x x 0 1 fbDsaPerTx will be applied
to FBAB DSA index.
The value of the default
DSA setting register
spi_agc_dsa_fb of Page
x x 1 x
"DSA Page0 AB" will be
applied to FBAB DSA
index.
2
Third value of fbDsaPerTx
0 0 x x will be applied to FBCD
DSA index.
Fourth value of
0 1 x x fbDsaPerTx will be applied
to FBCD DSA index.
The value of the default
DSA setting register
spi_agc_dsa_fb of Page
1 x x x
"DSA Page0 CD" will be
applied to FBCD DSA
index.

8.4 Alarms
There 2 alarm pins which can be OR of multiple alarms. This can be used to identify any errors/faults in
AFE. The alarms which can be brought on to pins are:
1. SERDES errors
2. DAC and ADC JESD link errors
3. SPI conflict errors, which is useful when multiple SPIs are used.
4. PAP errors
5. PLL unlock errors.
For using these alarms, ALARM1 and/or ALARM2 should be brought on to the pins.

8.4.1 Configuration

1. JESD: JESD related errors. This is common for all the links on both ADC and DAC. This includes
SerDes errors. This is a sticky alarm.
2. SPI: This is for cases where multiple SPIs are used. In cases where the constraints in using multiple
SPIs mentioned in Section 8.1 are violated, an alarm is triggered. This can be brought on to pins. This
is a sticky alarm.
3. TXA/B/C/DPAP: This gets the trigger of PAP trigger on to the pin. This can be both sticky and non-
sticky, based on the setting done in Section 8.4. There is an independent alarm per channel TX.
4. PLL: This gets the PLL lock lost alarm on to the pin. This is a sticky alarm.
There are various control mechanisms which can be employed with the alarms. This is important for host
to act on the alarm.
For each of the two alarm pins, need to identify which alarms need to be ORed to be brought on to it. True
refers to having the alarm on to the pin and False refers to not having the alarm on to the pin.

62 AFE79xx Configuration Guide SBAA417 – June 2020

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com Miscellaneous Functions

Table 28. Alarms Onto Pin Description

PARAMETER DEFAULT VALUE AND FORMAT DESCRIPTION
JESD True JESD Alarms. This is common error for all the DAC
links. It goes high when any of the DAC links are lost.
SPI True SPI Alarms where the SPI conflict when using
multiple SPIs is present. (Refer to Section 8.1)
PLL True PLL Lost of Lock
TXAPAP True TXA PAP
TXBPAP True TXB PAP
TXCPAP True TXC PAP
TXDPAP True TXD PAP

8.4.2 Steps to Recover

Figure 22. Alarms Recovery

1. Interrupt on alarm trigger and start the interrupt service routine.

2. Read the alarm status registers to identify which alarm got triggered.
3. If it is PLL alarm, give hardware reset and reinitialize AFE.
4. If it is JESD alarm, read the current status and the alarms which triggered. JESD State machine will

SBAA417 – June 2020 AFE79xx Configuration Guide 63

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

Miscellaneous Functions www.ti.com

attempt recover of link failure through re-handshaking through the sync pin in case hardware Sync is
being used in JESD204B and by receiver automatically in JESD204C. If the auto-recovery of link didn’t
work, then re-sync operation of the JESD link need to be done. If that also fails, restart of the AFE is
needed.
5. If it is SPI alarm, it may be needed to redo the previous SPI operation.
6. If it is PAP alarm, first freeze the DPD or any feed-forward or feedback processing loop in the host.
(freezing the DPD can be done for even PLL or JESD alarms since they also trigger PAP)
a. If the PAP trigger is not in auto clear mode (rampStickyMode=1), need to clear the PAP trigger
continuously till the PAP trigger is not asserted. If it is in auto clear mode (rampStickyMode=0), this
action is not needed.
b. If the PAP pin Alarm is in sticky mode (alarmPinStickyMode=1), the alarm bit must be cleared till the
alarm pin goes low (PAP trigger is released). If it is not in sticky mode, no action is needed here.
However, in case the trigger to PAP persists, then the PAP trigger will not clear.
7. Clear the alarms and continue to monitor the pin state.

8.4.3 Sample Mechanism

Pin 0: JESD, SPI, PLL, TXAPAP and TXBPAP alarms
Pin 1: JESD, SPI, PLL, TXCPAP and TXDPAP alarms
PAP alarms as sticky.
Since anything other than SPI triggers PAP, it would be good to identify which PAP alarm was triggered.
This gets especially useful when DPD for each of the channels is independent.

8.5 NCO Switching

AFE has multiple NCOs for a channel and to switch between them. Phase consistency is maintained
across NCO switching. That is, if the AFE is NCO is changed from 0 to 1 and back to 0, the phase of the
signal will remain undisturbed. For enabling the NCO switching, need to configure do the following settings
as needed.
RX NCO switching:
1. ncoRxMode
2. broadcastRxNcoSel
3. numRxNCO
4. rxNco0
5. rxNco1
6. Configuring the valid functions out of RX_NCOSEL_[0-3] on to the GPIO.
FB NCO switching:
1. numFbNCO
2. ncoFbMode
3. fbNco0
4. fbNco1
5. fbNco2
6. fbNco3
7. Configuring the valid functions out of FB_NCOSEL_[0-3] on to the GPIO.
TX NCO switching:
1. ncoTxMode
2. broadcastTxNcoSel
3. numTxNCO
4. txNco0
5. txNco1
64 AFE79xx Configuration Guide SBAA417 – June 2020
Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com Miscellaneous Functions

6. Configuring the valid functions out of TX_NCOSEL_[0-3] on to the GPIO.

8.6 Sysref
1. Sysref Frequency:
To maintain deterministic latency, across devices and initializations, the sysref frequency input to the
AFE need to be an integer factor of a base frequency. The base sysref frequency depends on various
configuration settings including, data rates, interface rates, JESD configuration, and so on. Based on
the configuration set, this is displayed in the log and is also in the System Parameters iGui (Figure 4).
2. SPI sysref Mode (useSpiSysref):
Enabling this mode (setting it to True) uses internal Sysref override in AFE and pin sysref is not used.
This can be used in cases where there is no need for deterministic latency or phase consistency.
3. Continuous Sysref Mode (continuousSysref):
There is an option of operating in single or continuous Sysref mode. In single sysref Mode, the sysref
at the pin needs to be given at certain locations of the configuration. These locations will be logged in
the log file as External Actions. In continuous sysref mode, the sysref can be turned on at the start of
initialization and can be turned off at the end of it. Both modes maintain deterministic latency.
4. Sysref Termination (sysrefTermination):
Termination Resistance of Sysref input of AFE. This can be changed as needed, depending on the
sysref circuit.
0-100 Ω, 1-150 Ω, 2-300 Ω, 3-inf

8.7 ADC to DAC Post Decimation Loop Back

AFE supports RX ADC to DAC loopback through the internal JESD block. This can be enabled by setting
jesdLoopBackEn to True. Below are the conditions to be satisfied for using this feature.
1. The ADC and DAC interface rates should be same.
2. The JESD settings and the lane rates should be same for both RX and TX.
3. RXA loops back to TXA, RXB loops back to TXB, and so on.
4. The SerDes receiver need to see some random data at the SRX at the correct lane rate. Note that the
value of the data does not matter but some toggles at that front is needed since the post CDR clock of
the SRX is used for this operation.

8.8 ADC to DAC Low Latency Loopback:

This loops back the FB ADC output (before the decimation) to TX A/D, and therefore has very low
loopback latency. This can be set using the parameter enableTxFbLoopbackLowLatencyMode(Table 37).
It is independent control for looping back FBAB to TXA and FBCD to TXC. For example, to loopback
FBAB to TXA, and use FBCD and TXCD in straight mode, this parameter can be set as
sysParams.enableTxFbLoopbackLowLatencyMode=[True,False]. The first value in the list is for FBAB and
second is for FBCD.

8.9 Using FB Chain as RX Chain

There can be some configurations in which there is no need for FB chain and want to use the chain as an
additional receiver. AFE79xx supports such kind of configurations to achieve 6R mode of operation.
couple of key points of this mode are:
1. All the 6 ADCs of the AFE are similar. In the 6R mode, the FB digital will operate as RX.
2. FB digital chain supports only single band of operation.
3. This mode of operation is supported only when the interface rate of all the chains in the 2R1F/3R
group is less than FadcRx/4.
4. FB digital supports SPI control of DSA and internal AGC mode but does not support pin based external
AGC mode. For SPI based external AGC mode, the detector outputs can be brought onto pins/LSBs.
5. Even in 3R mode (of one 2R1F section), JESD treats the FB digital output similar to 2R1F mode.
However, the JESD can be configured so as to treat FB similar to RX. For cases where same lane rate
and link configuration is needed for all RX:

SBAA417 – June 2020 AFE79xx Configuration Guide 65

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

Bring-Up Flow and Log File www.ti.com

• jesdSystemMode can be made 0.

• Can select JESD mode as 12410 for 16-bit mode, 12610 for 24-bit mode or 12310 for 12-bit mode.
• Select same values for link related settings (rxJesdTxK-fbJesdTxK, rxJesdTxScr-fbJesdTxScr)
• Keep same sync mux value for rxJesdTxSyncMux and fbJesdTxSyncMux.
• Set the ILA parameters as needed (setIlaParams, jesdTxIlaM, jesdTxIlaL, jesdTxIlaLid).

9 Bring-Up Flow and Log File

9.1 Configuration File

For the format of the configuration file and the way to generate the file, using Latte, please refer to the
Latte User Guide.

66 AFE79xx Configuration Guide SBAA417 – June 2020

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com Bring-Up Flow and Log File

9.2 Initialization Flow From Configuration File

Figure 23. Initialization Flow for Continuous Sysref (Part 1)

SBAA417 – June 2020 AFE79xx Configuration Guide 67
Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

Bring-Up Flow and Log File www.ti.com

Figure 24. Initialization Flow for Continuous Sysref (Part 2)

68 AFE79xx Configuration Guide SBAA417 – June 2020

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com Bring-Up Flow and Log File

Figure 25. Initialization Flow for Continuous Sysref (Part 3)

SBAA417 – June 2020 AFE79xx Configuration Guide 69

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

Bring-Up Flow and Log File www.ti.com

Figure 26. Initialization Flow for Continuous Sysref (Part 4)

70 AFE79xx Configuration Guide SBAA417 – June 2020

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com Bring-Up Flow and Log File

Figure 27. Initialization Flow for Single Shot Sysref (Part 1)

SBAA417 – June 2020 AFE79xx Configuration Guide 71

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

Bring-Up Flow and Log File www.ti.com

Figure 28. Initialization Flow for Single Shot Sysref (Part 2)

72 AFE79xx Configuration Guide SBAA417 – June 2020

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com Bring-Up Flow and Log File

Figure 29. Initialization Flow for Single Shot Sysref (Part 3)

SBAA417 – June 2020 AFE79xx Configuration Guide 73

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

Bring-Up Flow and Log File www.ti.com

Figure 30. Initialization Flow for Single Shot Sysref (Part 4)

For ease of splitting the steps in the configuration file, the file is divided into multiple steps with
placeholders for external actions.
1. rstDevice:
a. Step 0: Do soft reset of the device.
b. Step 1: Wake up the device. Setting the clock to internal MCU.
74 AFE79xx Configuration Guide SBAA417 – June 2020
Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com Bring-Up Flow and Log File

2. efuseChain:
a. Step 0: Loading the EFuse chain and checking for errors.
3. mcuWakeUp:
a. Step 1: Bringing the MCU out of reset.
b. Step 2: Loading Patch to the MCU, if applicable. The patch is to add any functionalities or to fix
any bugs to the firmware in the ROM.
4. pllEfuse:
a. Step 0: Load the PLL related Trims and related writes for them to take effect.
5. pllConfig :
a. Step 0: Device reference dividers are configured, if needed. If these are employed, then a sysref
must be given to align the reference divider to the PLL. Otherwise, this step will be skipped.
b. Step 1: The device PLL and the output dividers are configured.
c. Step 2: The PLL output dividers need a Sysref, for the data converter clocks across chips to be in
sync.
d. Step 3: Switch the MCU clock to PLL clock from reference clock.
6. serdesConfig:
a. Step 0: Enable the clock to the SERDES and set its input clock dividers.
b. Step 1: Reset the SERDES.
c. Step 2: Configure the SERDES.
d. Step 3: Load the SERDES firmware.
7. topConfig:
a. Step 0: Set TOP controls.
b. Step 1: Configure RX DSA.
c. Step 2: Configure TX DSA
d. Step 3: Configure FB DSA.
8. sysConfig:
a. Step 0: Set System Mode related parameters to the MCU.
b. Step 1: Set the RX chain related parameters to the MCU.
c. Step 2: Set the FB chain related parameters to the MCU.
d. Step 3: Set the TX chain related parameters to the MCU and the PAP block.
9. configTune:
a. Step 0: Configures the Rx, Tx and FB chains for the specified decimation/interpolation factors, and
with the appropriate NCO frequencies in each band using the parameters provided earlier.
b. Step 1: Set the FIFO pointers.
10. analogWrites :
a. Step 0: Load Performance related trims.
b. Step 1: Configure RX analog.
c. Step 2: Configure FB analog.
d. Step 3: Configure TX analog.
e. Step 4: Load post analog configuration trims.
11. jesdConfig:
a. Step 0: Configure the JESD data, sync and lane muxes.
b. Step 1: Configure ADC JESD TX.
c. Step 2: Configure DAC JESD RX.
d. Step 3: Configure JESD Power Saving related writes.
12. agcConfig :

SBAA417 – June 2020 AFE79xx Configuration Guide 75

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

System Parameters www.ti.com

a. Step 0: Configure AGC and ALC.

13. miscConfig:
a. Step 0: Configure System Power Saving related writes.
b. Step 1: Set default DSA values.
14. gpioConfig:
a. Step 0: Configure the GPIO.
15. sysrefJesdLinkup:
a. Step 0: Bring the JESD state machine out of reset.
b. Step 1: Clear Sysref Flags.
c. Step 2: Give main Sysref. This is the Sysref used to align all of the digital clocks, NCOs and JESD
state machine.
d. Step 3: Clear the JESD data path.
e. Step 4: Check if sysref reached.
16. postLinkUp:
a. Step 0: Perform some performance configuration, toggle the TDDs and release the pin control to
the pins.
b. Step 1: Clear all alarms.
17. dlJesdLinkupCheck:
a. Step 0: Check if the DAC JESD link is up.

10 System Parameters
These are the parameters to set before the AFE.deviceBringup() function call. These determine the state
of the system. All the frequencies are in MHz.

10.1 TOP Parameters

Format: sysParams.<parameter>
Example: sysParams.clkIn

Table 29. Top Level Parameters

PARAMETER DEFAULT VALUE AND FORMAT DESCRIPTION
FRef 491.52 Input reference clock to the device.
FadcRx 2949.12 RX ADC sampling rate. (MHz)
FadcFb 2949.12 FB ADC sampling rate. (MHz)
Fdac 2949.12*3 TX DAC sampling rate (MHz)
RRFMode 0 0: 4T4R2F FDD Mode
1: 4T4R1F FDD Mode
2: 4T2R2F FDD Mode Quad Band
5: 4T4R2F TDD Non-Shared
6: 4T4R1F TDD Non-Shared
7: 4T4R2F TDD Shared
8: 4T4R1F TDD Shared
10: 2T2R1F TDD AB / 2T2R1F FDD CD
11: 2T2R1F FDD AB / 2T2R1F TDD CD
Shared modes will use RXA ADC for
FBAB and RXC for RXC for FBCD.In TDD
Case, RX/FB cannot be active at the
same time.
In FDD Case, RX and FB can be active at
the same time with their respective TDD
pins controlling.

76 AFE79xx Configuration Guide SBAA417 – June 2020

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com System Parameters

Table 29. Top Level Parameters (continued)

PARAMETER DEFAULT VALUE AND FORMAT DESCRIPTION
adcSelect0 [0,1,2] This is the parameter to mux the ADC
data to the digital in RRF 0. This
parameter is to select the ADC data which
must be fed for each digital chain, among
FB and 2 RX. Select the ADC for each of
[FBAB, RXA, RXB] Value meaning:
• Data from FB AB ADC is to be fed.
• Data from RX A ADC is to be fed.
• Data from RX B ADC is to be fed.
For example, to swap RX B ADC and FB
AB ADC inputs, this value should be
[2,1,0].
Note that to utilize this mux, the rates of
the ADCs corresponding should be same.
This is important when the RX and FB are
being swapped.
adcSelect1 [0,1,2] This is the parameter to mux the ADC
data to the digital in RRF 1. This
parameter is to select the ADC data which
must be fed for each digital chain, among
FB and 2 RX. Select the ADC for each of
[FBCD, RXC, RXD] Value meaning:
• Data from FB CD ADC is to be fed.
• Data from RX C ADC is to be fed.
• Data from RX D ADC is to be fed.
For example, to swap RX A ADC and RX
B ADC inputs, this value should be [0,2,1].
Note that to utilize this mux, the rates of
the ADCs corresponding should be same.
This is important when the RX and FB are
being swapped.
modeTdd 0 Mode to control TDD.
0: Single TDD Pin for all Channels
1: Separate Control for 2T/2R/1F
2: Separate Control for 1T/1R/1F
externalClockRx False Use PLL clock or external clock for RX
Sampling rate.
False: PLL derived clock for RX
True: External Clock Mode for RX
Note that in this case, the FRef should be
equal to the FadcRx. Fdac will be derived
use the FRef and PLL.
externalClockTx False Use PLL clock or external clock for TX
Sampling rate.
False: PLL derived clock for TX
True: External Clock Mode for TX
Note that in this case, the FRef should be
equal to the Fdac. RX clock will be
derived from this.
useSpiSysref False False: Use Pin based Sysref
True: Use internal SPI based Sysref. Note
that in this case, deterministic latency.
halfRateModeRx [False,False] Enabling Half Rate Mode for RX [AB,CD].
This will make the sampling rate half of
FadcRx.
halfRateModeFb [False,False] Enabling Half Rate Mode for FB [AB,CD].
This will make the sampling rate half of
FadcFb.
halfRateModeTx [False,False] Enabling Half Rate Mode for TX [AB,CD].
This will make the sampling rate half of
Fdac.

SBAA417 – June 2020 AFE79xx Configuration Guide 77

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

System Parameters www.ti.com

Table 29. Top Level Parameters (continued)

PARAMETER DEFAULT VALUE AND FORMAT DESCRIPTION
ddcFactorRx [8, 8, 8, 8] DDC decimation factor for RX A,B,C,D.
FadcRx/ddcFactorRx for the channel will
be output data rate, irrespective of the
mode.
numBandsRx [0,0,0,0] Number of bands per channel for RX A, B,
C, D.
1. 0-Single Band
2. 1-Dual Band
numRxNCO 1 Number of active RX NCOs. This can be 1
or 2. If no NCO switching is needed, this
can be 1.
rxNco0 [[1800,2600],[1800,2600],[1800,2600],[180 [Band0, Band1] for RxA for NCO0
0,2600]] [Band0, Band1] for RxB for NCO0
[Band0, Band1] for RxC for NCO0
[Band0, Band1] for RxD for NCO0
rxNco1 [[1800,2600],[1800,2600],[1800,2600],[180 [Band0, Band1] for RxA for NCO1
0,2600]] [Band0, Band1] for RxB for NCO1
[Band0, Band1] for RxC for NCO1
[Band0, Band1] for RxD for NCO1
ddcFactorFb [4, 4] DDC decimation factor for FB AB, CD
FadcFb/ddcFactorFb for the channel will
be output data rate.
numFbNCO 1 Number of active FB NCOs. This can be 1
or 2. If no NCO switching is needed, this
can be 1.
fbNco0 [1800,1900] NCO0 for [FBAB, FBCD]
fbNco1 [1800,1900] NCO1 for [FBAB, FBCD]
ducFactorTx [4, 4,4,4] DUC interpolation factor for TXA,B, C, D
Fdac/ducFactorTx for the channel will be
output data rate.
numBandsTx [0,0,0,0] Number of bands per channel for TX A,B,
C,D.
1. 0-Single Band
1. 1-Dual Band
combineDucMode [0,0] Combines the 2 TX channels of the 2TX
when set to 1. [TXAB,TXCD].
numTxNCO 1 Number of active TX NCOs. This can be 1
or 2. If no NCO switching is needed, this
can be 1.
txNco0 [[1800,2600],[1800,2600],[1800,2600],[180 This is the effective NCO frequency
0,2600]] (combined NCO frequency of front and
back mixers). This programs the first NCO
options in each of the band and common
mixers.
[Band0, Band1] for TxA for NCO0;
[Band0, Band1] for TxB for NCO0
[Band0, Band1] for TxC for NCO0
[Band0, Band1] for TxD for NCO0
txNco1 [[1900,2700],[1900,2700],[1900,2700],[190 This is the effective NCO frequency
0,2700]] (combined NCO frequency of front and
back mixers). This programs the second
NCO options in each of the band and
common mixers.
[Band0, Band1] for TxA for NCO1
[Band0, Band1] for TxB for NCO1
[Band0, Band1] for TxC for NCO1
[Band0, Band1] for TxD for NCO1
enableDacInterleavedMode False Operates DAC in interleaved mode. When
this is True, the DAC will operate
in !~second nyquist!~interleaved mode.

78 AFE79xx Configuration Guide SBAA417 – June 2020

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com System Parameters

Table 29. Top Level Parameters (continued)

PARAMETER DEFAULT VALUE AND FORMAT DESCRIPTION
sysrefTermination 0 Termination Resistance of Sysref
0: 100 Ω,
1: 150 Ω
2: 300 Ω
3: inf
ncoFreqMode "1KHz" "1KHz": 1-KHz Raster of the NCO is
realized.
"FCW": 32-Bit NCO is realized.
spiMode 1 1. 3-wire Mode
1. 1-4 wire mode
rxEnable [True,True,True,True] Enable or disable [RXA, RXB, RXC, RXD]
True is to enable the RX. False is to
disable it.
fbEnable [True,True] Enable or disable [FB AB, FB CD]
True is to enable the FB. False is to
disable it.
txEnable [True,True,True,True] Enable or disable [TXA, TXB, TXC, TXD]
True is to enable the TX. False is to
disable it.
ncoRxMode [0,0] This sets the mode on how to use the
NCO pin functions to control the NCO
switching. This control is independent for
AB and CD.
0: No NCO switching in both bands
1: 1Pin/R NCOSEL_0 for RxA Band0,
NCOSEL_1 for RxB Band0, NCOSEL_2
for RxC Band0, NCOSEL_3 for RxD
Band0. No control for Band 1.
2: 1Pin/AB NCOSEL_0 for RxAB Band0,
NCOSEL_1 for RxCD Band0. Same Pins
control Band 1.
3: 2Pin/2R NCOSEL_0 for RxAB Band0,
NCOSEL_2 for RxCD Band0. NCOSEL_1
for RxAB Band1, NCOSEL_3 for RxCD
Band1.
4: 2Pin/2R NCOSEL_1/0 for RxAB Band0,
NCOSEL_3/2 for RxCD Band0. No control
to Band 1
5: Common NCOSEL_1/0 for all channels
Band 0. This will be chosen if either of the
entries are 5.
6: Common NCOSEL_3/2/1/0 for all
channels Band 0. This will be chosen if
either of the entries are 5.
broadcastRxNcoSel 0 If this is set, then same control goes to AB
and CD. In this case, CD corresponding
pins are not used.
ncoFbMode 0 This sets the mode on how to use the
NCO pin functions to control the NCO
switching.
0: No NCO switching Control
1: 2Pin/Fb (FB_NCOSEL_0 and
FB_NCOSEL_1 for FBAB,
FB_NCOSEL_2 and FB_NCOSEL_3 for
FBCD)
2: Common 4Pin (NCOSEL_0 and
NCOSEL_1, NCOSEL_2 and NCOSEL_3
for FBAB/FBCD)

SBAA417 – June 2020 AFE79xx Configuration Guide 79

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

System Parameters www.ti.com

Table 29. Top Level Parameters (continued)

PARAMETER DEFAULT VALUE AND FORMAT DESCRIPTION
ncoTxMode [0,0] This sets the mode on how to use the
NCO pin functions to control the NCO
switching. This control is independent for
AB and CD.
0: No Control to both Bands
1: 1pin/2T Control to Band0 (NCOSEL_0
for AB and NCOSEL_1 for CD). Same Pin
Controls Band 1 also.
2: 2pin/2T Control to Band0
(NCOSEL_0/1 for AB and NCOSEL_2/3
for CD). Same Pin Controls Band 1 also.
broadcastTxNcoSel 0 If this is set, then same control goes to AB
and CD. In this case, CD corresponding
pins are not used.

10.2 JESD Parameters

Format: sysParams.<parameter>
Example: sysParams.clkIn

PARAMETER DEFAULT VALUE AND FORMAT DESCRIPTION

jesdSystemMode [1,1] System mode for Instance 0/1.
SystemMode 0: 2R1F-FDDrx1-rx2-fb-fb
SystemMode 1: 1R1F-FDDrx1-rx1-fb-fb
SystemMode 2: 2R-FDDrx1-rx1-rx2-rx2
SystemMode 3: 1Rrx1-rx1-rx1-rx1
SystemMode 4: 1Ffb-fb-fb-fb
SystemMode 5: 1R1F-TDDrx1/fb-rx1/fb-rx1/fb-
rx1/fb
SystemMode 6: 1R1F-TDD,1R-FDD(FB-
2Lanes)rx1/fb-rx1/fb-rx2-rx2
LMFSHdRx ["24410","24410","24410","24410"] JESD mode for rx1,rx2 mappers of 2T2R1F AB
and CD instances respectively
LMFSHdFb ["24410","24410"] JESD mode for fb mapper of 2T2R1F AB and
CD instances respectively
LMFSHdTx ["44210","44210"] JESD mode for tx1,tx2 mappers of 2T2R1F AB
and CD instances respectively
jesdTxProtocol [0,0] ADC side JESD Protocol for instance 0/1.
0- 204B
2- 204C 64/66
3- 204B 64/80
jesdRxProtocol [0,0] DAC side JESD Protocol for instance 0/1.
0- 204B
2- 204C 64/66
3- 204B 64/80
jesdTxLaneMux [0,1,2,3,4,5,6,7] This chooses the JESD lane (before the MUX,
towards the AFE) for each SERDES lane (after
the MUX, towards the SERDES). For example, if
the data on 4th JESD lane on to the 2nd
SERDES lane, make the 2nd element in the
array as 3.
jesdRxLaneMux [0,1,2,3,4,5,6,7] This chooses the SERDES lane (before the
MUX, towards the SERDES) for each JESD
lane (after the MUX, towards the AFE). For
example, if the 4th SERDES lane should be
treated as 2nd JESD lane, make the 2nd
element in the array as 3.
serdesFirmware True True will load the SERDES firmware and help in
dynamic adaptation. It is preferred to keep this
True.
jesdTxRbd [4, 4] RBD value programming must be according to
the lanes used for ADC JESD
rxJesdTxScr [False,False,False,False] For 4 RX mappersTrue will enable the 8-bit
scrambler.

80 AFE79xx Configuration Guide SBAA417 – June 2020

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com System Parameters

PARAMETER DEFAULT VALUE AND FORMAT DESCRIPTION
fbJesdTxScr [False,False] For 2 FB mappersTrue will enable the 8-bit
scrambler.
jesdRxScr [False,False] For 2 TX MappersTrue will enable the 8-bit
scrambler.
rxJesdTxK [16,16,16,16] For 4 RX mappersK value in 204B and E value
in 204C
fbJesdTxK [16,16] For 2 FB mappersK value in 204B and E value
in 204C
rxJesdTxSyncMux [0,0,0,0] Chooses the sync pin to be used for different
channels of RX ADC JESD
fbJesdTxSyncMux [0,0] Chooses the sync pin to be used for different
channels of FB ADC JESD
jesdRxSyncMux [0,0,0,0] Chooses the sync pin to be used for DAC JESD
jesdABLvdsSync False Setting this True makes the AB side LVDS Sync
is as True for both RX and TX.
jesdCDLvdsSync False Setting this True makes the AB side LVDS Sync
is as True for both RX and TX.
syncLoopBack False True – For Hardware SyncFalse – For Software
Sync
jesdRxRbd [4, 4] RBD value programming must be according to
the lanes used for DAC JESD AB & CD
jesdRxK [16,16] K value for DAC JESD RX AB & CD
adcDataMuxEn 0 Enable ADC side Data Mux selection
parameters (rxDataMux, fbDataMux).
False: Use default
True: Enable Data Mux
rxDataMux [0,1,2,3,4,5,6,7] Choose what will come in each location for RX
Channel.
Location meaning: [A_B0, A_B1, B_B0, B_B1,
C_B0, C_B1, D_B0, D_B1]
Value meaning:
0-A_B0
1-A_B1
2-B_B0
3-B_B1
4-C_B0
5-C_B1
6-D_B0
7-D_B1
Eg: To swap RXA Band 0 and RXC Band
1,[5,1,2,3,4,0,6,7]
Note that the data rates of the channel
corresponding to location and the mux value
should be same.
fbDataMux [0,1] Choose what will come in each location for FB
Channel.
Location meaning: [FBAB, FBCD]
Value meaning:0-FBAB1-FBCD
Note that the data rates of the channel
corresponding to location and the mux value
should be same.
dacDataMuxEn 0 Enable DAC side Data Mux selection
parameters (rxDataMux).
False: Use default
True: Enable Data Mux

SBAA417 – June 2020 AFE79xx Configuration Guide 81

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

System Parameters www.ti.com

PARAMETER DEFAULT VALUE AND FORMAT DESCRIPTION

txDataMux [0,1,2,3,4,5,6,7] Choose what will come in each location for TX
Channel.
Location meaning: [A_B0, A_B1, B_B0, B_B1,
C_B0, C_B1, D_B0, D_B1]
Value meaning:
0-A_B0
1-A_B1
2-B_B0
3-B_B1
4-C_B0
5-C_B1
6-D_B0
7-D_B1
Eg: To swap TXA Band 0 and TXC Band
1,[5,1,2,3,4,0,6,7]
Note that the data rates of the channel
corresponding to location and the mux value
should be same.
jesdLoopBackEn False True: Enable the RX to TX loop back.
False: Disable the RX to TX loop back.
serdesTxLanePolarity [False,False,False,False,False,False,False,Fals Sets the STX Lane Polarity. Setting the nth
e] value to True in the list inverts the lane polarity
of nth STX.
serdesRxLanePolarity [False,False,False,False,False,False,False,Fals Sets the SRX Lane Polarity. Setting the nth
e] value to True in the list inverts the lane polarity
of nth SRX.
serdesTxPreCursor [6,6,6,6,6,6,6,6] STX1-8 Pre-Cursor.
serdesTxPostCursor [0,0,0,0,0,0,0,0] STX1-8 Post-Cursor.
serdesTxMainCursor [3,0,0,0,0,0,0,3] STX1-8 Main-Cursor.
setIlaParams True True sets the ILA parameters of the ADC JESD
TX lanes as per the other ILA parameters.
Otherwise the default are sent.
jesdTxIlaM [8,8,2,8,8,2] M value per IP layer.
jesdTxIlaLid [0,1,2,3,4,5,6,7] Lane ID per lane.
jesdTxIlaL [4,4,2,4,4,2] L value per IP layer.

10.3 GPIO Config

List of GPIO Balls Supported:
'C5', 'C6', 'D5', 'D6', 'E5', 'E6', 'E7', 'E8', 'F14', 'F16', 'F5', 'F6', 'F7', 'G10', 'G11', 'G12', 'G13', 'G14', 'G15',
'G16', 'G6', 'G7', 'G8', 'G9', 'H10', 'H11', 'H12', 'H13', 'H14', 'H15', 'H16', 'H7', 'H8', 'H9', 'J14', 'J15', 'K14',
'L14', 'M14', 'M15', 'N10', 'N11', 'N12', 'N13', 'N15', 'N16', 'N7', 'N8', 'N9', 'P10', 'P13', 'P14', 'P16', 'P6', 'P7',
'P8', 'P9', 'R15', 'R5', 'R6', 'R7', 'T5', 'T6', 'T7', 'T8', 'U5', 'U6', 'V5', 'V6'
List of Input Functions Supported:
Broadcast of input functions, same GPIO pin driving multiple input functions is possible for non-fixed
functions.

82 AFE79xx Configuration Guide SBAA417 – June 2020

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com System Parameters

Table 30. List of Supported Input Functions

FUNCTION GROUP PSUEDONAME DESCRIPTION PREFERRED OR FIXED.(EMPTY
MEANS IT IS NEITHER)
EXTAGC_GPIOMode1 (RXAB 8- RXAB_DSA_GAIN_0 Bit 0 (LSB) of DSA Index for RXA & Preferred Ball Name: F5
Pin DSA configuration). RXB in 8-pin external AGC mode
(EXTAGC_GPIOMode1)
RXAB_DSA_GAIN_1 Bit 1 of DSA Index for RXA & RXB Preferred Ball Name: E5
in 8-pin external AGC mode
(EXTAGC_GPIOMode1)
RXAB_DSA_GAIN_2 Bit 2 of DSA Index for RXA & RXB Preferred Ball Name: F7
in 8-pin external AGC mode
(EXTAGC_GPIOMode1)
RXAB_DSA_GAIN_3 Bit 3 of DSA Index for RXA & RXB Preferred Ball Name: H10
in 8-pin external AGC mode
(EXTAGC_GPIOMode1)
RXAB_DSA_GAIN_4 Bit 4 of DSA Index for RXA & RXB Preferred Ball Name: G10
in 8-pin external AGC mode
(EXTAGC_GPIOMode1)
RXAB_DSA_GAIN_5 Bit 5 of DSA Index for RXA & RXB Preferred Ball Name: H9
in 8-pin external AGC mode
(EXTAGC_GPIOMode1)
RXAB_DSA_GAINSEL Gain Select, in 8-pin external AGC Preferred Ball Name: G9
mode (EXTAGC_GPIOMode1), to
choose between RX A and RXB. 0-
RXA. 1-RXB.
RXAB_DSA_GAINLEN Gain Latch Enable, in 8-pin external Preferred Ball Name: E8
AGC mode
(EXTAGC_GPIOMode1). The Gain
will be applied to the selected
channel on the rising edge of this
signal.
EXTAGC_GPIOMode1 (RXCD 8- RXCD_DSA_GAIN_0 Bit 0 (LSB) of DSA Index for RXC & Preferred Ball Name: P7
Pin DSA configuration). RXD in 8-pin external AGC mode
(EXTAGC_GPIOMode1)
RXCD_DSA_GAIN_1 Bit 1 of DSA Index for RXC & RXD Preferred Ball Name: T6
in 8-pin external AGC mode
(EXTAGC_GPIOMode1)
RXCD_DSA_GAIN_2 Bit 2 of DSA Index for RXC & RXD Preferred Ball Name: R7
in 8-pin external AGC mode
(EXTAGC_GPIOMode1)
RXCD_DSA_GAIN_3 Bit 3 of DSA Index for RXC & RXD Preferred Ball Name: T8
in 8-pin external AGC mode
(EXTAGC_GPIOMode1)
RXCD_DSA_GAIN_4 Bit 4 of DSA Index for RXC & RXD Preferred Ball Name: P8
in 8-pin external AGC mode
(EXTAGC_GPIOMode1)
RXCD_DSA_GAIN_5 Bit 5 of DSA Index for RXC & RXD Preferred Ball Name: P6
in 8-pin external AGC mode
(EXTAGC_GPIOMode1)
RXCD_DSA_GAINSEL Gain Select, in 8-pin external AGC Preferred Ball Name: U6
mode (EXTAGC_GPIOMode1), to
choose between RXC & RXD. 0-
RXC. 1-RXD.
RXCD_DSA_GAINLEN Gain Latch Enable, in 8-pin external Preferred Ball Name: U5
AGC mode
(EXTAGC_GPIOMode1). The Gain
will be applied to the selected
channel on the rising edge of this
signal.

SBAA417 – June 2020 AFE79xx Configuration Guide 83

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

System Parameters www.ti.com

Table 30. List of Supported Input Functions (continued)

FUNCTION GROUP PSUEDONAME DESCRIPTION PREFERRED OR FIXED.(EMPTY
MEANS IT IS NEITHER)
EXTAGC_GPIOMode2 (RX 4-Pin RXA_DSA_GAIN_0 Bit 0 of RXA DSA index Preferred Ball Name: F5
DSA configuration).
RXA_DSA_GAIN_1 Bit 1 of RXA DSA index Preferred Ball Name: E5
RXA_DSA_GAIN_2 Bit 2 of RXA DSA index Preferred Ball Name: H10
RXB_DSA_GAIN_0 Bit 0 of RXB DSA index Preferred Ball Name: G10
RXB_DSA_GAIN_1 Bit 1 of RXB DSA index Preferred Ball Name: H9
RXB_DSA_GAIN_2 Bit 2 of RXB DSA index Preferred Ball Name: G9
RXC_DSA_GAIN_0 Bit 0 of RXC DSA index Preferred Ball Name: P7
RXC_DSA_GAIN_1 Bit 1 of RXC DSA index Preferred Ball Name: T6
RXC_DSA_GAIN_2 Bit 2 of RXC DSA index Preferred Ball Name: R7
RXD_DSA_GAIN_0 Bit 0 of RXD DSA index Preferred Ball Name: P8
RXD_DSA_GAIN_1 Bit 1 of RXD DSA index Preferred Ball Name: P6
RXD_DSA_GAIN_2 Bit 2 of RXD DSA index Preferred Ball Name: U6
FBINTAGC FBAB_AGC_FREEZE Freeze FBAB AGC when it is being
used as RX
FBCD_AGC_FREEZE Freeze FBCD AGC when it is being
used as RX
INTAGC RXA_AGC_FREEZE Freeze RXA AGC
RXB_AGC_FREEZE Freeze RXB AGC
RXC_AGC_FREEZE Freeze RXC AGC
RXD_AGC_FREEZE Freeze RXD AGC
SPIB1 INTBIPI_SPIB1_SDI INTBIPI_SPIB1_SDI Fixed Ball Name: H11
SPIB1_CSN SPIB1_CSN Fixed Ball Name: H16
SPIB1_CLK SPIB1_CLK Fixed Ball Name: G16
SPIB2 INTBIPI_SPIB2_SDI INTBIPI_SPIB2_SDI Fixed Ball Name: H13
SPIB2_CSN SPIB2_CSN Fixed Ball Name: F16
SPIB2_CLK SPIB2_CLK Fixed Ball Name: J14

84 AFE79xx Configuration Guide SBAA417 – June 2020

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com System Parameters

Table 30. List of Supported Input Functions (continued)

FUNCTION GROUP PSUEDONAME DESCRIPTION PREFERRED OR FIXED.(EMPTY
MEANS IT IS NEITHER)
MAIN ADC_SYNC0 JESDTX Sync Pin 0. In LVDS Preferred Ball Name for CMOS
Mode, this will act as SYNC. Fixed Ball for LVDS SYNC:
ADC_SYNC0+. H8
ADC_SYNC1 JESDTX Sync Pin 1. In LVDS Preferred Ball Name for CMOS
Mode, this will act as ADC_SYNC0- SYNC. Fixed Ball for LVDS SYNC:
. H7
ADC_SYNC3 JESDTX Sync Pin 2. In LVDS Preferred Ball Name for CMOS
Mode, this will act as SYNC. Fixed Ball for LVDS SYNC:
ADC_SYNC1+. N8
ADC_SYNC4 JESDTX Sync Pin 3. In LVDS Preferred Ball Name for CMOS
Mode, this will act as ADC_SYNC1- SYNC. Fixed Ball for LVDS SYNC:
. N7
ADC_SYNC2 JESDTX Sync Pin 4. In LVDS
Mode, these remain as CMOS.
ADC_SYNC5 JESDTX Sync Pin 5. In LVDS
Mode, these remain as CMOS.
TXATDD TXATDD: If single pin TDD control, Preferred Ball Name: H15
acts as common for all channels. If
common TDD control for 2
channels is used, acts as common
control for AB. If per channel TDD
control is used, is used only for
TXA.
TXBTDD TXBTDD: If single pin TDD control,
is ignored. If common TDD control
for 2 channels is used, is ignored. If
per channel TDD control is used, is
used only for TXB.
TXCTDD TXCTDD: If single pin TDD control, Preferred Ball Name: R15
is ignored. If common TDD control
for 2 channels is used, acts as
common control for CD. If per
channel TDD control is used, is
used only for TXC.
TXDTDD TXDTDD: If single pin TDD control,
is ignored. If common TDD control
for 2 channels is used, is ignored. If
per channel TDD control is used, is
used only for TXD.
FBABTDD FBABTDD: If single pin TDD Preferred Ball Name: K14
control, is used for FBAB & FBCD.If
per channel/per 2-channel TDD
control is used, is used only for FB
AB.
FBCDTDD FBCDTDD: If single pin TDD Preferred Ball Name: R6
control, is ignored. If per
channel/per 2-channel TDD control
is used, is used only for FB CD.

SBAA417 – June 2020 AFE79xx Configuration Guide 85

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

System Parameters www.ti.com

Table 30. List of Supported Input Functions (continued)

FUNCTION GROUP PSUEDONAME DESCRIPTION PREFERRED OR FIXED.(EMPTY
MEANS IT IS NEITHER)
MAIN GLOBAL_PDN Sleep Pin Preferred Ball Name: P14
TX_FB_LOOP_0 TX_FB_LOOP_0 Preferred Ball Name: G14
TX_FB_LOOP_1 TX_FB_LOOP_1 Preferred Ball Name: H14
TX_FB_LOOP_2 TX_FB_LOOP_2 Preferred Ball Name: F14
TX_FB_LOOP_3 TX_FB_LOOP_3 Preferred Ball Name: H12
RXATDD RXATDD: If single pin TDD control, Preferred Ball Name: E7
acts as common for all channels. If
common TDD control for 2
channels is used, acts as common
control for AB. If per channel TDD
control is used, is used only for
RXA.
RXBTDD RXBTDD: If single pin TDD control,
is ignored. If common TDD control
for 2 channels is used, is ignored. If
per channel TDD control is used, is
used only for RXB.
RXCTDD RXCTDD: If single pin TDD control, Preferred Ball Name: V5
is ignored. If common TDD control
for 2 channels is used, acts as
common control for CD. If per
channel TDD control is used, is
used only for RXC.
RXDTDD RXDTDD: If single pin TDD control,
is ignored. If common TDD control
for 2 channels is used, is ignored. If
per channel TDD control is used, is
used only for RXD.
RXA_GSW RXA Gain Swap
RXB_GSW RXB Gain Swap
RXC_GSW RXC Gain Swap
RXD_GSW RXD Gain Swap
TXA_GSW TXA Gain Swap
TXB_GSW TXB Gain Swap
TXC_GSW TXC Gain Swap
TXD_GSW TXD Gain Swap

86 AFE79xx Configuration Guide SBAA417 – June 2020

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com System Parameters

Table 30. List of Supported Input Functions (continued)

FUNCTION GROUP PSUEDONAME DESCRIPTION PREFERRED OR FIXED.(EMPTY
MEANS IT IS NEITHER)
MAIN FB_NCOSEL_0 FB_NCOSEL_0. Refer to NCO Sel
mode description to determine how
this is used.
FB_NCOSEL_1 FB_NCOSEL_1. Refer to NCO Sel
mode description to determine how
this is used.
RX_NCOSEL_0 RX_NCOSEL_0. Refer to NCO Sel
mode description to determine how
this is used.
RX_NCOSEL_1 RX_NCOSEL_1. Refer to NCO Sel
mode description to determine how
this is used.
RX_NCOSEL_2 RX_NCOSEL_2. Refer to NCO Sel
mode description to determine how
this is used.
RX_NCOSEL_3 RX_NCOSEL_3. Refer to NCO Sel
mode description to determine how
this is used.
TX_NCOSEL_0 TX_NCOSEL_0. Refer to NCO Sel
mode description to determine how
this is used.
TX_NCOSEL_1 TX_NCOSEL_1. Refer to NCO Sel
mode description to determine how
this is used.
TX_NCOSEL_2 TX_NCOSEL_2. Refer to NCO Sel
mode description to determine how
this is used.
TX_NCOSEL_3 TX_NCOSEL_3. Refer to NCO Sel
mode description to determine how
this is used.
FB_NCOSEL_2 FB_NCOSEL_2. Refer to NCO Sel
mode description to determine how
this is used.
FB_NCOSEL_3 FB_NCOSEL_3. Refer to NCO Sel
mode description to determine how
this is used.

10.3.1 List of Output Functions Supported

Broadcast of output functions, getting same output function on multiple GPIO pins is possible for non-fixed
functions.

SBAA417 – June 2020 AFE79xx Configuration Guide 87

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

System Parameters www.ti.com

Table 31. List of Supported Output Functions

FUNCTION GROUP PSUEDONAME DESCRIPTION PREFERRED OR FIXED.(EMPTY
MEANS IT IS NEITHER)
EXTAGC RXA_PKDET_0 RXA_PKDET_0: Peak Detector Preferred Ball Name: E5
Output 0. Need to configure what
comes on this pin separately.
RXA_PKDET_1 RXA_PKDET_1: Peak Detector Preferred Ball Name: G8
Output 1. Need to configure what
comes on this pin separately.
RXA_PKDET_2 RXA_PKDET_2: Peak Detector Preferred Ball Name: G6
Output 2. Need to configure what
comes on this pin separately.
RXA_PKDET_3 RXA_PKDET_3: Peak Detector
Output 3. Need to configure what
comes on this pin separately.
RXB_PKDET_0 RXB_PKDET_0: Peak Detector Preferred Ball Name: F6
Output 0. Need to configure what
comes on this pin separately.
RXB_PKDET_1 RXB_PKDET_1: Peak Detector Preferred Ball Name: G7
Output 1. Need to configure what
comes on this pin separately.
RXB_PKDET_2 RXB_PKDET_2: Peak Detector Preferred Ball Name: E6
Output 2. Need to configure what
comes on this pin separately.
RXB_PKDET_3 RXB_PKDET_3: Peak Detector
Output 3. Need to configure what
comes on this pin separately.
RXC_PKDET_0 RXC_PKDET_0: Peak Detector Preferred Ball Name: P10
Output 0. Need to configure what
comes on this pin separately.
RXC_PKDET_1 RXC_PKDET_1: Peak Detector Preferred Ball Name: T8
Output 1. Need to configure what
comes on this pin separately.
RXC_PKDET_2 RXC_PKDET_2: Peak Detector Preferred Ball Name: U6
Output 2. Need to configure what
comes on this pin separately.
RXC_PKDET_3 RXC_PKDET_3: Peak Detector
Output 3. Need to configure what
comes on this pin separately.

88 AFE79xx Configuration Guide SBAA417 – June 2020

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com System Parameters

Table 31. List of Supported Output Functions (continued)

FUNCTION GROUP PSUEDONAME DESCRIPTION PREFERRED OR FIXED.(EMPTY
MEANS IT IS NEITHER)
EXTAGC RXD_PKDET_0 RXD_PKDET_0: Peak Detector
Output 0. Need to configure what
comes on this pin separately.
RXD_PKDET_1 RXD_PKDET_1: Peak Detector Preferred Ball Name: V6
Output 1. Need to configure what
comes on this pin separately.
RXD_PKDET_2 RXD_PKDET_2: Peak Detector Preferred Ball Name: T7
Output 2. Need to configure what
comes on this pin separately.
RXD_PKDET_3 RXD_PKDET_3: Peak Detector Preferred Ball Name: P8
Output 3. Need to configure what
comes on this pin separately.
RELSTATUS_RXA0 Reliability Detector status for RXA, Preferred Ball Name: C5
bit 0
RELSTATUS_RXA1 Reliability Detector status for RXA,
bit 1
RELSTATUS_RXB0 Reliability Detector status for RXB, Preferred Ball Name: D6
bit 0
RELSTATUS_RXB1 Reliability Detector status for RXB,
bit 1
RELSTATUS_RXC0 Reliability Detector status for RXC, Preferred Ball Name: R5
bit 0
RELSTATUS_RXC1 Reliability Detector status for RXC,
bit 1
RELSTATUS_RXD0 Reliability Detector status for RXD, Preferred Ball Name: N10
bit 0
RELSTATUS_RXD1 Reliability Detector status for RXD,
bit 1
RFPKDET_RXA RF Analog Peak Detector Output Preferred Ball Name: R5
for RXA
RFPKDET_RXB RF Analog Peak Detector Output Preferred Ball Name: T5
for RXB
RFPKDET_RXC RF Analog Peak Detector Output Preferred Ball Name: N10
for RXC
RFPKDET_RXD RF Analog Peak Detector Output Preferred Ball Name: P10
for RXD
FBEXTAGC RELSTATUS_FBAB0 Reliability Detector status for FBAB,
bit 0
RELSTATUS_FBAB1 Reliability Detector status for FBAB,
bit 1
RELSTATUS_FBCD0 Reliability Detector status for
FBCD, bit 0
RELSTATUS_FBCD1 Reliability Detector status for
FBCD, bit 1
RFPKDET_FBAB RF Analog Peak Detector Output
for FBAB
RFPKDET_FBCD RF Analog Peak Detector Output
for FBCD
FBAB_PKDET_0 FBAB_PKDET_0
FBAB_PKDET_1 FBAB_PKDET_1
FBAB_PKDET_2 FBAB_PKDET_2
FBAB_PKDET_3 FBAB_PKDET_3
FBCD_PKDET_0 FBCD_PKDET_0
FBCD_PKDET_1 FBCD_PKDET_1
FBCD_PKDET_2 FBCD_PKDET_2
FBCD_PKDET_3 FBCD_PKDET_3
SPIB1 SPIB1_SDO SPIB1_SDO Fixed Ball Name: G12
INTBIPO_SPIB1_SDO INTBIPO_SPIB1_SDO Fixed Ball Name: H11
SPIB2 SPIB2_SDO SPIB2_SDO Fixed Ball Name: J15
INTBIPO_SPIB2_SDO INTBIPO_SPIB2_SDO Fixed Ball Name: H13

SBAA417 – June 2020 AFE79xx Configuration Guide 89

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

System Parameters www.ti.com

Table 31. List of Supported Output Functions (continued)

FUNCTION GROUP PSUEDONAME DESCRIPTION PREFERRED OR FIXED.(EMPTY
MEANS IT IS NEITHER)
MAIN RXA_LNABYPASS_B0 RXA_LNABYPASS_B0 Preferred Ball Name: D5
RXB_LNABYPASS_B0 RXB_LNABYPASS_B0 Preferred Ball Name: G10
RXC_LNABYPASS_B0 RXC_LNABYPASS_B0 Preferred Ball Name: T6
RXD_LNABYPASS_B0 RXD_LNABYPASS_B0 Preferred Ball Name: T5
ALARM1 ALARM Pin 1 Preferred Ball Name: N16
ALARM2 ALARM Pin 2 Preferred Ball Name: N15
DAC_SYNC0 DAC_SYNC0In LVDS Mode, this Preferred Ball Name for CMOS
will act as DAC_SYNC0+. SYNC. Fixed Ball for LVDS SYNC:
H9
DAC_SYNC1 DAC_SYNC1In LVDS Mode, this Preferred Ball Name for CMOS
will act as DAC_SYNC0-. SYNC. Fixed Ball for LVDS SYNC:
G9
DAC_SYNC2 DAC_SYNC2In LVDS Mode, this Preferred Ball Name for CMOS
will act as DAC_SYNC1+ SYNC. Fixed Ball for LVDS SYNC:
N9
DAC_SYNC3 DAC_SYNC3In LVDS Mode, this Preferred Ball Name for CMOS
will act as DAC_SYNC1- SYNC. Fixed Ball for LVDS SYNC:
P9
RXA_LNABYPASS_B1 RXA_LNABYPASS_B1
RXB_LNABYPASS_B1 RXB_LNABYPASS_B1
RXC_LNABYPASS_B1 RXC_LNABYPASS_B1
RXD_LNABYPASS_B1 RXD_LNABYPASS_B1
FBAB_LNABYPASS FBAB_LNABYPASS
FBCD_LNABYPASS FBCD_LNABYPASS

10.4 AGC and ALC Parameters

Format: sysParams.agcParams[chNo].<parameter>
Example: sysParams.agcParams[chNo].agcMode

Table 32. List of AGC and ALC Parameters

PARAMETER DEFAULT VALUE AND FORMAT DESCRIPTION
agcMode 0 0: disabled
1: Internal AGC
2: External AGC SPI control
3: External AGC 4-pin control
4: External AGC 8-Pin control. Only values in chNo 0 and 2
are valid. Common control for 2R.
gpioRstEnable 0 0: Disable
1: EnableGPIO based reset to AGC detectors Enable
blank_time_extcomp 255 Blanking Time for all Detectors when external component
(LNA or DVGA) gain change.
en_agcfreeze_pin 0 0: Disable
1: Enable
Enable or Disable pin based AGC freeze.
tdd_freeze_agc 1 0: Reset
1: Freeze
Whether to reset or freeze the attack detectors during the
OFF period of TDD
atken [0,1,0] [big step, small step, power detector]
decayen Whether to use ADC Detectors in AGC loop operation.
1/True: Enable
0/False: Disable
atksize [1,2] [big step, small step & power detector]
decaysize Whenever some detector triggers, this step size mentions
the DSA change that needs to happen in the appropriate
direction. This value*0.5dB is the applied step size.

90 AFE79xx Configuration Guide SBAA417 – June 2020

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com System Parameters

Table 32. List of AGC and ALC Parameters (continued)

PARAMETER DEFAULT VALUE AND FORMAT DESCRIPTION
atkthreshold [-1,-2,-14] [big step, small step, power detector]
Detector threshold with the Resolution: 0.25 dB. This value*-
0.25dB is the applied threshold.
decaythreshold [-14,-8,-20] [big step, small step, power detector]
Detector threshold with the Resolution: 0.25 dB. This value*-
0.25dB is the applied threshold.
atkwinlength [170,170] [big step attack, small step attack]
Detector Time Constant expressed in absolute time in ns
(only allowed in steps of 10 ns).
All other attack detectors use the same value as small step
attack detector.
decaywinlength 87380 Detector Time Constant expressed in absolute time in ns
(only allowed in steps of 10 ns).
All detectors use the same value for decay time constant.
atkNumHitsAbs [8,8] Absolute Number of times signal crosses threshold. These
crossings are with respect to the FADC/8 clock.
This is for [big step attack, small step attack] detectors.
decayNumHitsAbs [8,8] Absolute Number of times signal crosses threshold.
These crossings are with respect to the FADC/8 clock. This
is for [big step decay, small step decay] detectors.
minDsaAttn 0 Minimum DSA attenuation used by AGC.
This is in steps of 0.5dB, that is, this value*0.5dB is the
applied minimum attenuation. The range of this is 0 to 50.
maxDsaAttn 50 Maximum DSA attenuation used by AGC.
This is in steps of 0.5dB, that is, this value*0.5dB is the
applied maximum attenuation. The range of this is 0 to 50.
totalGainRange 25 Total gain range used by ALC for gain compensation.
This is in steps of 1dB is the applied total Gain range. The
range of this is 0 to 50.
minAttnAlc 0 Minimum Attenuation used by ALC for compensation when
useMinAttnAgc = 0
useMinAttnAgc 1 0: Disable
1: Enable
Enable ALC to use minimum attenuation from AGC for which
compensation is required.
alcEn 0 0: Disable ALC
1: Enable ALC
alcMode 0 0: Floatingpoint
2: coarsefineI
3: coarsefineIQ
4: coarsefineALCpin
5: inputALC
fltPtMode 0 0: If exponent > 0, don’t send MSB
1: Send MSB always
Whether to send MSB of mantissa always in Floating Point
mode of ALC
fltPtFmt 1 0: 2 bit exponent , 13 bit mantissa and 1 bit sign
1: 3 bit exponent, 12 bit mantissa and 1 bit sign
2: 4 bit exponent, 11 bit mantissa and 1 bit sign
Number of Mantissa and Exponent bits to be used in floating
point mode of ALC
stepSize 6 Coarse gain step size in coarse fine mode of ALC.
Supported values are: 2, 3, 4, 6, and 8.
nBitIndex 3 Number of bits to be used for coarse index in coarse fine
mode of ALC. Valid values are 2, 3, and 4.
indexInvert 0 0: coarse index
1: 15 – coarse index
Whether to invert coarse index in coarse fine on LSB mode
of ALC

SBAA417 – June 2020 AFE79xx Configuration Guide 91

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

System Parameters www.ti.com

Table 32. List of AGC and ALC Parameters (continued)

PARAMETER DEFAULT VALUE AND FORMAT DESCRIPTION
indexSwapIQ 0 0: LSB on I, MSB on Q1: MSB on I, LSB on Q
Whether to swap coarse index on I and Q. Applicable in
CoarsefineIQ mode of ALC
sigBackOff 0 Signal Back-off in dB in coarse fine mode
outputDgcPinDelay 306. Delay applied to the gain before being sent on pins in
coarsefineALCpin mode of ALC
bitMode 0 0: 16 bit mode
1: 12 bit mode
lnaEn 0 0: Disable
1: EnableExternal LNA Control in Internal AGC mode
dvgaEn 0 0: Disable
1: EnableExternal DVGA Control in Internal AGC mode
minDvgaAttn 0 Minimum DVGA attenuation used by AGC
maxDvgaAttn 31 Maximum DVGA attenuation used by AGC
extLnaTempModel 0 0: Disable
1: Enable
Use Temperature model for LNA gain
lnagain0 12 LNA gain to be compensated by ALC for Band 0.
Resolution: 0.03125 dB
Used when extLnaTempModel = 0
lnaphase0 0 LNA phase to be compensated for Band 0 in Degrees.
Resolution: 360/1024 DegreeUsed when extLnaTempModel
=0
lnagain1 12 LNA gain to be compensated by ALC for Band 1.
Resolution: 0.03125 dB
Used when extLnaTempModel = 0
lnaphase1 0 LNA phase to be compensated for Band 1 in Degrees.
Resolution: 360/1024 Degree
Used when extLnaTempModel = 0
lnaGainMargin 6 Gain margin required before re-enabling LNA by AGC.
startTemp 0 Used when extLnaTempModel = 1
stepTemp 1 Used when extLnaTempModel = 1
NumStep 5 Used when extLnaTempModel = 1
temp_idxB0 0 LNA gain phase LUT temperature index in AGC for band 0.
Used when extLnaTempModel = 1
temp_idxB1 1 LNA gain phase LUT temperature index in AGC for band 1.
Used when extLnaTempModel = 1
singleDualBandMode 0 0: Single LNA control
1: Dual LNA control
Whether to use Single LNA control or dual LNA control in
dual-band configuration
dualLnaDecayThB0 15 Decay threshold for LNA 0 decay detector
dualLnaDecayThB1 15 Decay threshold for LNA 1 decay detector
dualLnaDecayNumCrossingMo 0 0: Absolute
de 1: Relative
Whether to use percentage of Time Constant/Window
Length or absolute number of crossings for LNA decay
detectors
dualLnaDecayNumCrossingsB 2048 Number of crossings to declare decay for LNA 0 detector
0 When dualLnaDecayNumCrossingMode = 0, expressed in
absolute Number.
When dualLnaDecayNumCrossingMode = 1, expressed as
percentage with resolution of 100/2^16.
dualLnaDecayNumCrossingsB 2048 Number of crossings to declare decay for LNA 1 detector
1 When dualLnaDecayNumCrossingMode = 0, expressed in
absolute Number.
When dualLnaDecayNumCrossingMode = 1, expressed as
percentage with resolution of 100/2^16.

92 AFE79xx Configuration Guide SBAA417 – June 2020

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com System Parameters

Table 32. List of AGC and ALC Parameters (continued)

PARAMETER DEFAULT VALUE AND FORMAT DESCRIPTION
dualLnaAtkNumCrossingMode 0 0: Absolute
1: Relative
Whether to use percentage of Time Constant/Window
Length or absolute number of crossings for LNA attack
detectors
dualLnaAtkNumCrossingsB0 2048 Number of crossings to declare attack for LNA 0 detector
When dualLnaAtkNumCrossingMode = 0, expressed in
absolute Number
When dualLnaAtkNumCrossingMode = 1, expressed as
percentage with resolution of 100/2^16.
dualLnaAtkNumCrossingsB1 2048 Number of crossings to declare attack for LNA 1 detector
When dualLnaAtkNumCrossingMode = 0, expressed in
absolute Number
When dualLnaAtkNumCrossingMode = 1, expressed as
percentage with resolution of 100/2^16.
dualLnaMode 1 0: Decay based
1: Loop state based
Whether to use LNA detectors as decay detectors or let the
loop control the mode of detectors.
dualLnaDsaApproach 1 0: Conservative
1: Aggressive
Aggressive or conservative approach for offsetting DSA
during LNA change.
rfdeten 0 Use RF analog detector for internal AGC.
rfdetstepsize 8 Whenever RF analog detector triggers, this step size
mentions the DSA change that needs to happen in the
appropriate direction
rfdetnumhits 8 Absolute Number of times signal crosses threshold above
which attack is declared
custRfMode 1 0: extAgc: Use RF analog detector in External AGC.
1: bigStepAtk: Use RF analog detector as very big step
attack in internal AGC.
2: lnaBypass: Use RF analog detector for external LNA
bypass in internal AGC.
pin0sel 16448 Peak Detector Data on 4 pins/LSBs. Each pin can be
pin1sel 16432 configured to carry ORed combination of selected bits.
pin2sel 16416 Setting a particular bit gets the detector on to the
pin3sel 16400 corresponding pin/LSB.
Bit 14: OVR Bit
Bit 13: Band 0 power detector
Bit 12: Band 0 peak detector
Bit 11: RF detector
Bit 10: Band 1 power detector
Bit 9: Band 1 peak detector
Bit 8: Reserved
Bit 7: Digital big step attack
Bit 6: Digital small step attack
Bit 5: Digital big step decay
Bit 4: Digital small step decay
Bit 3: Dig power attack
Bit 2: Dig power decay
Bit 1: Reserved (0)
Bit 0: Reserved (0)
pkDetPinLsbSel 0 0: send on Pin
1: send on Pin and LSB
Whether to send detector data on LSB in External AGC
mode
pkDetOnPenultimateLsb 0 0: Disable
1: Enable
Whether to send detector data on Penultimate LSB in
External AGC mode
dsaStep 1 This is the step value of DSA index in 4-pin DSA mode.
dsaInit 0 This is the offset value of DSA index in 4-pin DSA mode.

SBAA417 – June 2020 AFE79xx Configuration Guide 93

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

System Parameters www.ti.com

Table 32. List of AGC and ALC Parameters (continued)

PARAMETER DEFAULT VALUE AND FORMAT DESCRIPTION
maxDelay 0 This is the delay after the change of pin change (in 4-pin
DSA control mode) to latch the values. This is to account for
the latency variation between pins. This is in unit of cycles of
FadcRx/8.

10.5 PAP Config

Format: sysParams.papParams[chNo][<parameter>]
Example: sysParams.papParams[chNo][<parameter>]

Table 33. List of PAP Related Parameters

SNO PARAMETER DEFAULT VALUE AND DESCRIPTION
FORMAT
Moving Average Detector
1 maWindowCntr 1 Number of windows. Range: 0 to 2**12-1
2 maWindowCntrTh 1 Hits threshold in number windows. Range: 0 to 2**12-1
3 maThreshB0 90 Percentage threshold with respect to full scale for Band
0 detector.
4 maThreshB1 90 Percentage threshold with respect to full scale for Band
1 detector.
5 maThreshComb 90 Percentage threshold with respect to full scale for
combining detector.
6 maNumSample 128 Number of samples over which power is to be taken.
Supported values: 32/64/128
7 maEnable 1 0: Disable Moving Average Filter based Detector
1: Enable Moving Average Filter based Detector
High Pass Filter
1 hpfWindowCntr 0 Number of windows. Range: 0 to 2**12-1
2 hpfWindowCntrTh 0 Hits threshold in number windows. Range: 0 to 2**12-1
3 hpfThreshB0 30 Percentage threshold with respect to full scale for Band
0 detector.
4 hpfThreshB1 30 Percentage threshold with respect to full scale for Band
1 detector.
5 hpfThreshComb 30 Percentage threshold with respect to full scale for
combining detector.
6 hpfNumSample 4 Number of samples over which power is to be taken.
Supported values: 4/8/16
7 hpfEnable 1 0: Disable High Pass Filter based Detector
1: Enable High Pass Filter based Detector
Common Controls
1 enable 0 Enable the PAP block
2 multMode 0 This is the signal with which to multiply the incoming
signal for ramp up/down.
0: Cosine
1: Linear
3 rampDownStartVal 128 This is the starting value for the ramp down. For cosine
mode, the start phase in radians is (128-
rampDownStartVal)* π /128.
For linear mode, (rampDownStartVal/128) is the start
value. Good to keep this as 128 to ensure that the ramp
down starts from unity gain.

94 AFE79xx Configuration Guide SBAA417 – June 2020

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com System Parameters

Table 33. List of PAP Related Parameters (continued)

SNO PARAMETER DEFAULT VALUE AND DESCRIPTION
FORMAT
4 attnStepSize 5 This is the ramp step size while Ramping down.
In linear case, the gain will reduce by
(attnStepSize/1024) every amplUpdateCycles ns.
In Cosine case, the phase is incremented by
(pi*attnStepSize/1024) every amplUpdateCycles ns.
5 gainStepSize 5 This the step size of ramp signal (which is multiplied
with the data) during ramp up. In linear case, the gain
will increase by (attnStepSize/1024) every
amplUpdateCycles cycles.
In Cosine case, the phase is decremented by
(pi*attnStepSize/1024) every amplUpdateCycles cycles.
6 detectInWaitState 0 If or if not to honour PAP trigger in wait state.
0: Do not detect in wait state
1: Detect in wait state
7 triggerToRampDown 50 Time from trigger occurance to ramp down time (ns)
8 waitCounter 200 Wait time counter. (ns)
9 triggerClearToRampUp 50 Time from end of wait state to Ramp up (ns)
10 amplUpdateCycles 2 Time of each step during ramp up or down. (in ns)
11 alarmPulseGPIO 1000 Pulse width of PAP alarm going to GPIO (ns)
12 alarmMask 0b1000000 Bit wise alarms masking. Making the corresponding bit
0 will make the PAP state machine trigger on
corresponding alarm.
0: pll_alarm
1: serdes_alarm
2: fifo_alarm
3: ovr_saturation_alarm
4: dual-band det alarm
5: combined band det alarm
6: spi trigger
13 alarmChannelMask 0b1110 Bit wise alarms masking for other channels (bit-wise).
Making the corresponding bit 0 will make the PAP state
machine trigger on corresponding alarm. For each
channel the bit-wise description is different.
Channel: Bit No 3-2-1-0
TxA: D-C-B-A,
TxB: D-C-A-B,
TxC: B-A-D-C,
TxD: B-A-C-D
For triggering each channel by its own PAP trigger, this
value should be 0b1110 for all channels. For triggering
each channel by PAP trigger of all channels, this value
should be 0x0 for all channels.
14 alarmPinDynamicMode 1 1: dynamic
0: sticky
15 rampStickyMode 0 0: Auto clear PAP trigger.
1: Wait for pap clear bit to be written

SBAA417 – June 2020 AFE79xx Configuration Guide 95

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

System Parameters www.ti.com

10.6 Miscellaneous
Format: sysParams.<parameter>
Example: sysParams.rxDsaCalibMode

10.6.1 DSA Calibration Parameters

Table 34. List of Calibration Related Parameters

PARAMETER DEFAULT VALUE AND FORMAT DESCRIPTION
enableRxDsaCalibration False Enable for RX/FB DSA Calibration.
rxDsaCalibMode 0 Number of channels to calibrate at a time.
0: One channel at a time
1: A&C at once and B&D at once
rxDsaBandCalibMode 0 Number of bands of a channel to calibrate
at a time.
0: One Band at a time
1: Both bands together (applicable only in
dual-band case).
rxDsaGainRange [0,25] Range of RX DSA to calibrate.[minimum
DSA, maximum DSA]. Units are dB.
useTxCalib 0 When set to 1, TX can be looped back to
RX and be used for calibration instead of
an external signal source.
rxDsaCalibPacket \\Documents\Texas Path to store the calibration packet during
Instruments\Latte\lib\TxDSACalPkt.hex EVM testing.
fbChainSelForDsaCalib 0 0-Do not calibrate the FB DSA.
1-Calibrate only FB AB DSA.
2-Calibrate only FB CD DSA.
3-Calibrate both FB AB and CD DSA.
enableTxDsaCalibration False Enable for TX DSA Calibration.
txDsaCalibMode 0 FB channel to use.
0: Single Fb Mode
FB AB1: -Single Fb Mode
FB CD2: Dual FB_Mode. Both FB are
used.
txdsaStartStop [0,29] Range of TX DSA to calibrate. [minimum
DSA, maximum DSA]
txDsaBandCalibMode 0 Number of bands of a channel to calibrate
at a time.
0: One Band at a time
1: Both bands together (applicable only in
dual-band case).
txDsaCalibPacket \\Documents\Texas Path to store the calibration packet during
Instruments\Latte\lib\RxDSACalPkt.hex EVM testing.

DSA Params:
Format: sysParams.parameter
Example: sysParams.defaultFbDsa =[3,3,3,3]

Table 35. List of DSA Related Parameters

PARAMETER DEFAULT VALUE AND FORMAT DESCRIPTION
defaultRxDsa [0,0,0,0] Default RX DSA per channel. This value
*0.5dB is the applied attenuation.
This typically doesn’t matter because
internal/external AGC sets this mode.
defaultFbDsa [0,0] Default FB DSA per channel. This value
*0.5dB is the applied attenuation.

96 AFE79xx Configuration Guide SBAA417 – June 2020

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 DRAFT ONLY

www.ti.com System Parameters

Table 35. List of DSA Related Parameters (continued)

PARAMETER DEFAULT VALUE AND FORMAT DESCRIPTION
defaultTxDsa [0,0,0,0] Default TX DSA per channel. This value
*1dB is the applied attenuation.
Maximum value of this is 29.

10.6.2 Alarms Config

Format: sysParams.intPinsParams[alarmNo][<parameter>]
Example: sysParams.intPinsParams [alarmNo][‘JESD’]=True
For each of the two alarm pins, need to identify which alarms need to be ORed to be brought on to it. True
refers to having the alarm on to the pin and False refers to not having the alarm on to the pin.

Table 36. List of Alarms Related Parameters

PARAMETER DEFAULT VALUE AND FORMAT DESCRIPTION
JESD True JESD Alarms.
SPI True SPI Alarms
PLL True PLL Lost of Lock
TXAPAP True TXA PAP
TXBPAP True TXA PAP
TXCPAP True TXA PAP
TXCPAP True TXD PAP

10.6.3 Other Miscellaneous Parameters

Table 37. Miscellaneous Parameters

PARAMETER DEFAULT VALUE AND FORMAT DESCRIPTION
enableTxFbLoopbackLowLatencyMo
[False,False] Enable for TX to FB low latency Loop Back.
de
fbDsaPerTxEn False Enables the GPIO Based control for FB DSA.
DSA Index to be applied for FB DSA based on the
fbDsaPerTx [0,0,0,0]
TX_FB_LOOP pins.
Mode of looping back controlling the FB DSA.
0- Single FB mode with FB AB.
txToFbMode 0
1- Single FB mode with FB CD.
2- Dual FB mode with FB AB and FB CD.

SBAA417 – June 2020 AFE79xx Configuration Guide 97

Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
 IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated