A Continuous-Time Delta-Sigma Modulator for Biomedical Ultrasound

Beamformer Using Digital ELD Compensation and FIR Feedback

Zhang, Y., Chen, C. H., He, T., & Temes, G. C. (2015). A Continuous-Time
Delta-Sigma Modulator for Biomedical Ultrasound Beamformer Using Digital ELD
Compensation and FIR Feedback. IEEE Transactions on Circuits and Systems I:
Regular Papers, 62(7), 1689-1698. doi:10.1109/TCSI.2015.2434100

10.1109/TCSI.2015.2434100
IEEE - Institute of Electrical and Electronics Engineers

Accepted Manuscript
http://cdss.library.oregonstate.edu/sa-termsofuse
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A Continuous-Time Delta-Sigma Modulator for

Biomedical Ultrasound Beamformer Using Digital
ELD Compensation and FIR Feedback
Yi Zhang, Student Member, IEEE, Chia-Hung Chen, Member, IEEE, Tao He, Student Member,
IEEE, and Gabor C. Temes, Life Fellow, IEEE

 Abstract—This paper presents the design of a continuous-time Focal Point

Receive Beamformer Channels
∆Σ modulator (CTDSM) to be used in an ultrasound beamformer Dynamic
Transducer
for biomedical imaging. To achieve better resolution, the TS Delays
prototype modulator operates at 1.2 GHz. It incorporates a ∆Σ-M  1 1 , r1 
digital excess loop delay (ELD) compensation to replace the TS
Echo
active adder in front of the internal quantizer. A digitally
Signal ∆Σ-M  2  2 , r2  Process
Elements
controlled reference-switching matrix, combined with the data-
weighted averaging (DWA) technique, results in a delay-free r TS
feedback path. A multi-bit FIR feedback DAC, along with its  ∆Σ-M  n  n , rn 
compensation path, is used to achieve lower clock jitter sensitivity Wavefront TGA
and better loop filter linearity. The modulator achieves 79.4 dB
Fig. 1. Block diagram of an ultrasound receiver using dynamic focusing.
dynamic range, 77.3 dB SNR and 74.3 dB SNDR over a 15 MHz
signal bandwidth. Fabricated in a 65 nm CMOS process, the core
of integration [3][4]. As shown in Fig. 1, in the ∆Σ ADC based
modulator occupies an area of only 0.16 mm2 and dissipates 6.96
mW from a 1 V supply. A 58.6 fJ/conversion-step figure of merit beamforming receiver, the digital signal processing circuitry
is achieved. applies dynamic delays to the digitized output of the ∆Σ
modulator in the each channel, so that a coherent combination
Index Terms—Ultrasound beamformer, continuous-time ∆Σ of the received signals is focused at points along a particular
modulator, digital excess loop delay compensation, FIR feedback direction of interest [4][5]. In the few reported use of ∆Σ
DAC modulation in biomedical ultrasound beamformers [6][7], the
dynamic range was only around 60 dB. In the detection of the
I. INTRODUCTION blood flow by a pulsed Doppler ultrasound receiver, the

M EDICAL ultrasound imaging is commonly used for

obtaining diagnostic medical images, as a compact and
affordable diagnostic tool. It uses beamforming techniques to
ultrasound system sends a signal pulse into the body at F0. The
returning echo has a very strong component at F0 from
stationary tissue (the vessel walls) and a very weak signal
construct an image of the interrogated medium. within 1 kHz of F0 due to the slow blood flow. To detect this
The function of the beamforming receiver is to amplify and weak blood flow signal in the presence of the strong signal
demodulate the separate echo signals, provide the proper time from the tissue, it requires a dynamic range larger than 12 bits.
delay in each channel, and add the signals. Conventional In this work, a continuous-time ∆Σ modulator (CTDSM)
digital beamformers use Nyquist rate ADCs as an was chosen as a power-efficient solution to achieve 12-bit
interpolation filter to effectively up-sample the digital sample, effective number of bits (ENOB) over the target signal
so that accurately delayed samples are acquired [1][2]. bandwidth (BW = 15 MHz) of the medical ultrasound.
However, this requires increased hardware complexity. However, CTDSM is susceptible to severe non-idealities, such
Oversampling ∆Σ ADCs have recently become attractive in as excess loop delay (ELD) and clock jitter. Their correction
signal processing applications due to their simplicity and ease in this project will be discussed next.
In this paper, we give the details of the design, which was
reported earlier in [13]. The remainder of the paper is
Manuscript received January 09, 2015. This work was supported by
Maxim Integrated. organized as follows. Section II gives the architecture of the
Y. Zhang, C-H Chen, T. He, and G. C. Temes are with the School of modulator. Section III provides a brief overview of prior art
Electrical Engineering and Computer Science, Oregon State University, addressing the excess loop delay issue, and introduces the
Corvallis, OR 97331 USA.
Copyright © 2015 IEEE. Personal use of this material is permitted. proposed technique. Section IV presents the FIR filtering
However, permission to use this material for any other purposes must be applied in the feedback path, along with its compensation.
obtained from the IEEE by sending an email to [email protected]. Circuit design details of important building blocks of the
prototype are discussed in Section V. Measurement results of
the prototype test chip are provided in Section VI. Section VII
concludes the paper.
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Loop Filter Summation

kff 2 CMP[1]
2-bit QTZ VIN H(s) CMP[2]
kff 1 CMP[n] DOUT
k2 IN
QTZ
OUT
IN
Swing
Vref
VIN 1 k3 1
VREF
OUT
3
INVREF
OUT DOUT α
sTS sTS sTS VREF Excess Loop
kres Reference Delay Compen.
Switching
Vref DAC1 DAC2
DAC1 DAC2 k1 3
Matrix
ELD&DWA

TS


F(z) C(z) DAC3 z 2

Z-D DEM
Ptr. Gen.

TS Fig. 3. Block diagram of a general continuous-time ∆Σ modulator with a direct
2
z feedback path to compensate for the ELD [9].
Fig. 2. Block diagram of the proposed CT ∆Σ modulator using digital ELD
compensation and FIR feedback.

Rest of n CMP[1]
II. ARCHITECTURE DETAILS VIN CMP[2]
H(s) s  TS CMP[n] DOUT
The architecture of the proposed CT ∆Σ modulator is shown QTZ
Vref
in Fig. 2 [18]. It is well known in loop filter design that the
first-order path is usually required to be a fast one, since it DAC2,3
largely determines the unity-gain bandwidth of the loop filter,
DAC1 1-Z-0.5
and is essential for the loop stability [8]. Therefore, the
parasitic poles of the first-order path may degrade stability
[21]. In the conventional Cascade of Integrators with Z-1 DEM
Feedforward (CIFF) topology, the first-order path is (a)
IN REF[n]
implemented by the first integrator feeding the adder at the OUT
input of the quantizer. Hence the amplifier used in the first CMPs IN REF[5]
EN Delay
OUT
IN REF[4]
stage integrator is required to be very fast, so as not to limit ENOUT
IN REF[3] DOUT
the unity gain bandwidth of the first-stage integrator. Loop Filter ENOUT
IN REF[2] MUX
However, the in-band gain of the first-stage integrator also VIN ENOUT
IN REF[1]
H(s)
needs to be high enough to provide sufficient attenuation of ENOUT

Y(t) EN
the non-idealities from the following stages. Hence, it may not
be a power-efficient solution to place the first integrator in the DAC1 Z-1
CMP
Selection
high-speed path as in the conventional CIFF topology.
In order to separate the requirements of both high gain and Z-0.5 DEM
high speed in the first-stage integrator, this work incorporates
a 3rd-order loop filter with combined feedforward and (b)

feedback paths. Instead of implementing the fastest first-order Fig. 4. Prior art. (a) Discrete-time differentiation technique [8] (b) Comparator
switching technique [11].
path by the first integrator, the first-order path is formed by
the feedback path k1 to the input of the last integrator, which
replaces an extra summation node required in the CIFF DWA technique is introduced as shown in Fig. 2. In addition,
topology. The input feed-forward path kff1 and kff2 help to error due to the clock jitter applied in the feedback path
reduce the swing of the internal state. increases the in-band noise of CTDSM. To mitigate this effect,
In addition, a local resonator path kres formed by the second a multi-bit FIR filtering path F(z) are employed with its
and third integrator introduces zeros in the noise transfer compensation path C(z). Both techniques will be discussed in
function (NTF) to further suppress the in-band quantization the following sections.
noise. The out-of-band gain (OBG) of the NTF is chosen to be
2, allowed by the use of a 2-bit internal quantizer. Data
Weighted Averaging (DWA) technique is employed to III. EXCESS LOOP DELAY COMPENSATION
randomize the unit element mismatch in the feedback DAC.
A. Overview of the Prior Arts
The feedback DAC is implemented with switched-resistors,
which have better noise performance and matching under low A general block diagram of a continuous-time (CT) ∆Σ
supply voltage (1 V) than current steering DAC. To counter modulator with ELD compensation is depicted in Fig. 3
the RC time constant variation, the digitally tunable [9][10]. It contains a CT loop filter H(s) for in-band noise
integrating capacitor arrays are employed. attenuation; an internal quantizer; a feedback DAC; and a
The CTDSM suffers from the excess loop delay [9]. A dynamic element matching (DEM) block to filter the DAC
reference-switching matrix for both ELD compensation and element mismatch signal. The ELD compensation absorbs the
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Vrefp = 0.75 V
Loop Filter IN CMPs
OUT BN1BN0 BP1BP0
IN DOUT IN
VIN 1 VREF
OUT
H(s) 2 IN IN OUT RUNIT = 100Ω
VREF
OUT VREF
IN OUT
Y(t) REF[1] -0.5 VREF DOP/
Z Ptr. Gen. OUT
REF[1] DON Vref0' BN1BP0 BP1BN0 Vref0
DAC1 Switch
swing 1 QTZ
Matrix
2 
V
BN1BN0 BP1BP0
ref Vref0
REF BP1BN0
up/down BN1BP0
REFs
Vref switching Vref1' BN1BP0 BP1BN0 Vref1
Z-0.5 matrix
BP1BP0 BN1BN0
(a) B(P/N)1B(P/N)0 BP1BP0 BN1BN0
Embedded
DAC2 Vref1
BP1BN0 BN1BP0

Vref2' BP1BN0 BN1BP0 Vref2

DOP DON BP1 BP0 BN1 BN0 BP1BP0 BP1BN0 BP0BN1 BN1BN0 ∆Vref
111 000 1 1 0 0 1 0 0 0 -VFS/2 BP1 BP0 BN1 BN0
BP1BP0 BN1BN0
011 100 1 0 0 1 0 1 0 0 -VFS/6 T2B T2B Vref2
001 110 0 1 1 0 0 0 1 0 VFS/6
000 111 0 0 1 1 0 0 0 1 VFS/2 BN1BP0 BP1BN0
3 3
(c) 
TS

TS
2
z z 2

3 3 BN1BN0 BP1BP0
DOP DON
(b)
Vrefn = 0.25 V

Fig. 5. (a) Proposed ELD compensation by reference-switching technique with the scaled quantizer (b) Differential implementation details of the control logic
and reference-switching matrix, in which RUNIT = 100Ω (c) possible digitized output sample and the pointer generated to determine the shifted amount.

signal-dependent delay by introducing an intentional delay Z-D requires additional comparators in the quantizer, which results
between the quantizer and feedback DAC. As a result, a direct in the increased parasitic loading, and complicates the design
feedback path around the internal quantizer is necessary to of the last integrator. Furthermore, the multiplexing logic in
compensate the inserted delay Z-D. However, this the critical path, as shown in Fig 4(b), adds to the loop delay.
compensation path requires the use of an adder in front of the
B. Proposed Digital ELD Compensation
quantizer. This adder is in the main path, and may introduce a
parasitic pole, which is undesirable in high-speed operation. As illustrated in Fig. 5(a) [12][35], rather than switching in
Several techniques to eliminate the use of this adder have or out comparators with fixed reference voltages [11], this
been proposed in recent years [8] [28]. In [8], as illustrated in work proposes to switch the reference voltages of a fixed set
Fig. 4(a), the addition is shifted to the input node of the last of comparators, which eliminates the following multiplexing
stage integrator using discrete-time differentiation. The pulse as in [11]. A reference-switching matrix, digitally controlled
of the feedback DAC is first differentiated and then integrated by the pointer generation logic, replaces both the direct
on the capacitor of the last stage integrator, creating a path feedback path and the signal adder before the quantizer. Fig.
equivalent to summation in front of the quantizer. In [28], an 5(b) shows the details of the differential implementation of the
equivalent feedforward path is introduced by putting a phase- reference-switching matrix. In this work, an ELD coefficient α
lead resistor (PLR) in series with the integrating capacitor in of 0.5, shown in Fig. 3, was implemented. In Fig. 5(b), 𝑉̂𝑟𝑒𝑓𝑖
the last stage integrator. Thus it eliminates the use of a and 𝑉̂𝑟𝑒𝑓𝑖 ′ represent the differential threshold inputs to the ith
summing amplifier in front of the quantizer. Both technique comparator in the quantizer. The full-scale quantization
suffer from one drawback: a feed-in path to the last integrator range is 𝑉𝐹𝑆 ≜ 𝑉𝑟𝑒𝑓𝑝 −𝑉𝑟𝑒𝑓𝑛 . The reference levels in the
required to implement the ELD compensation. The extra feed- resistor string are shifted in the quantizer by an
in path mandates a wide opamp finite gain bandwidth amount ∆𝑉𝑟𝑒𝑓 ≜ 𝑉̂𝑟𝑒𝑓𝑖 − 𝑉̂𝑟𝑒𝑓𝑖 ′, which is determined by the
(FGBW) in the last integrator. In addition, the increased previous output sample DOP/DON of the modulator. In other
parasitics at the input node of the last integrator make it words, an equivalent summation is realized by shifting up or
difficult for this integrator to form the fast first-order feedback down the quantizer reference levels by ∆𝑉𝑟𝑒𝑓 given by:
path, especially for high speed operation
Instead of using an analog feedback path, [11] proposed a
digital ELD compensation method, shown in Fig. 4(b). The  BP1  BP 0 
 
 VFS VFS  BP1  BN 0 
VFS   
summation in front of the quantizer is replaced by a group of (1)
Vref     VFS 
switching comparators with fixed reference voltages. The  3 3   BP 0  BN 1 
increased number of comparators mandates the following  
multiplexing of the quantizer outputs. The comparator  BN 1  BN 0 
selection logic takes the previous output sample of the
modulator, enables the corresponding comparators upwards or where α is the ELD compensation coefficient which here is
𝑉 𝑉
downwards and controls the multiplexer to perform the digital equal to 0.5; [−𝑉𝐹𝑆 − 𝐹𝑆 𝐹𝑆 𝑉𝐹𝑆 ] are the four quantization
3 3
summation for ELD compensation. This technique, however, levels of the 2-bit quantizer. 𝐵𝑃𝑖 and 𝐵𝑁𝑖 are the converted
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Switching delay
on critical path

From loop
90 QTZ Therm. Shuffler DAC out
filter
+3σ ptr
88
REFs -1
SQNR [dB]

Enc. Z
86 mean
(a)
84 From loop Therm.
QTZ DAC out
filter
82 -3σ
Switch ptr
Matrix Z-1 Enc.
80
0 0.05 0.1 0.15 0.2 0.25 0.3
σoffset [LSB] REFs (b)
Fig. 7. Block diagram of (a) Conventional thermometer-code shuffling DWA
Fig. 6. Simulated SQNR as a function of comparator offsets with the line (b) Reference shuffling DWA.
representing the mean SQNR and SQNR distributed within ±3σ.

were simulated as shown in Fig. 6. The broken lines represent

binary representation of the digitized sample; 𝐵𝑃𝑖 ∙ 𝐵𝑁𝑖 are the mean SQNRs and the SQNRs distributed within ±3σ. It
generated by the pointer generation logic, which involves a shows that in the quantizer with downscaled reference
thermometer-to-binary conversion and an AND logic, as voltages, even with a 0.3 LSB 1-σ offset (12.5 mV), the
shown in the left part of Fig. 5(b); Fig. 5(c) gives all possible achieved SQNR is above 80 dB, leaving a 6 dB margin above
values of DOP/DON and pointers 𝐵𝑃𝑖 ∙ 𝐵𝑁𝑖 ; ∆𝑉𝑟𝑒𝑓 corresponds the target of 12-bit ENOB. Careful sizing of the comparator
to the shift in the reference levels. From (1), one shifted input pair and common centroid layout technique were used to
amount is selected out of the first vector for the next guarantee minimal degradation of the performance due to the
quantization based on the current quantized sample output in offset of the comparator.
the second vector. Based on (1), it can further implement the C. Reference Shuffling DWA
ELD coefficient α other than 0.5 by changing ∆𝑉𝑟𝑒𝑓 with
The use of 2-bit feedback DAC requires data-weighting
appropriate design of the adjacent reference levels.
averaging (DWA) to shape the DAC element mismatch error.
The operation of both the pointer generation logic and the
In the conventional DWA technique, as shown Fig. 7(a), the
reference-switching matrix is allocated half a clock period, so
thermometer output code of the quantizer is encoded and
that the shifted reference voltages are able to settle within the
generates a pointer to select the quantizer output. However,
other half a clock period for the next quantization. The unit
the shuffler functions in the main feedback path, and hence its
resistor in the reference matrix, as shown in Fig. 5(b), is
switching delay contributes to the excess loop delay. At a
chosen to be 100 Ω, leading to around 420 µW of power
clock rate of 1.2 GHz, the delay through such a shuffler is
dissipation. Care has to be taken in the routing so as to
comparable to the clock period, and thus significantly reduces
minimize the parasitics along the reference-switching path and
the regeneration time budget of the comparators.
the resulting settling requirement. The settling error in the
The converter described in this work uses a reference-
reference-switching matrix is approximated by an offset in the
switching matrix to eliminate the element shuffler located in
quantizer and fortunately it can be suppressed by the
the feedback path [21][22], as shown in Fig. 7(b). Rather than
preceding loop filter. This technique effectively reduces the
shuffling the thermometer code of the quantizer output, the
number of comparators in the quantizer and as a result, it
pointer generation logic follows the DWA rotation algorithm,
eliminates the multiplexing logic delay in the critical path.
and drives the switching matrix to shuffle the quantizer
In the described ELD compensation techniques, however,
reference voltages and obtain the next quantizer output to be
the swing of the loop filter output is increased in the presence
applied to the DAC. This technique effectively results in a
of the direct ELD compensation feedback path. In order to
delay-free path.
allow the use of a power supply as low as 1 V, the loop filter
Similar to the proposed ELD compensation technique, the
was scaled down by a factor of 2. Accordingly, the reference
pointer generation logic is also employed to manipulate the
voltages of the quantizer were also scaled by the same factor.
quantizer reference matrix. Thus, these two reference-
This effectively scales up the quantizer gain so that the loop
switching matrices are merged.
gain remains unaffected. This downscaling of the quantizer
reference voltages may make the comparator offset
IV. PROTOTYPE CT ∆Σ ADC WITH FIR FEEDBACK
requirements harder to meet. However, the number of the
comparators used in the quantizer is low, and extensive Another design challenge in CT ∆Σ modulators comes from
simulations were made to guarantee that the comparator offset the error introduced by the jitter-affected clock applied to the
in the quantizer would not be a major source of error in the feedback DAC. This error is referred to the input without
modulator. For each level of comparator offset, 1000 samples being shaped by the loop filter, as demonstrated in Fig. 8(a). A
modulator using multi-level feedback is less susceptible to
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0
VIN Loop DOUT
Filter

Magnitude [dB]
-5
e[n] QTZ N=2
-10 N=3
t t N=4
multi-bit
CLK DAC1 N=5
-15 N=6
TS,  T
1-bit
N=7
(a) BW
-20
-3 -2 -1
DOUT 0.001
10 0.01
10 0.1
10 0.5
VIN Loop Frequency [Fs]
1 Filter (a)
0.5
Y(t)
QTZ 20
Compen. Path

0
1 N=2
Y(t) DAC1
-0.5
0.5
15 N=3
-1
1 2 3 4 5 6 7 8 9 10
4
x 10 0
N=4

Magnitude [dB]
10 N=5
F(z) -0.5
N=6
-1
500 520 540 560 580 600 620 640 660 680 700
5 N=7
N-tap FIR
BW
(b)
0
Fig. 8. Block diagram of (a) clock jitter induced error model (b) FIR
feedback DAC, along with its compensation path. -5

-10
clock jitter than a single-bit one due to the reduced step size in -3
0.001
10
-2
0.01
10 0.1-1
10 0.5
the DAC. Frequency [Fs]
One technique to reduce the clock jitter sensitivity is the use (b)

of an FIR filter F(z) in the feedback path [15], as illustrated in

Fig. 8(b). The in-band noise power J due to the clock jitter
Occurrences

[16][17] with the FIR feedback path is:

 2jit  lsb
2

1  e j  NTF  e j  F  e j  d (2)
 2
J
TS  OSR
2  0

2 2
where 𝜎𝑗𝑖𝑡 is the variance of the clock jitter; 𝜎𝑙𝑠𝑏 is the -1 0 1 -1 0 1 -1 0 1
Voltage [V]
variance of the quantization noise of the internal quantizer; (c)
OSR is the oversampling ratio of the modulator; 𝑁𝑇𝐹(𝑒 𝑗𝜔 ) is Fig. 9. (a) Frequency responses of FIR feedback path F(z). (b) Frequency
the noise transfer function of the modulator; and 𝐹(𝑒 𝑗𝜔 ) is the responses of the FIR compensation path C(z) for different tap lengths N (c)
Histograms of the each integrator output swing in the loop filter for tap length
transfer function of the FIR feedback path. N = 3.
It is clear that the low-pass FIR filter F(z) attenuates the
quantization noise at high frequency, and thus reduces the Both methods tend to increase the parasitic in the last stage
integrated noise power due to the clock jitter. In the time integrator, which is problematic for a modulator running at 1.2
domain, the use of the FIR filter applied to the single-bit GHz.
feedback DAC averages the adjacent samples, and reduces the This work, as shown in Fig. 2, uses a simple FIR feedback
step size from sample to sample, which simulates the benefits path C(z) to compensate the delay introduced by the main FIR
of the multi-level feedback. However, the introduction of the feedback F(z). As discussed in Section II, the last integrator
FIR feedback path necessitates a compensation path for the implementing the fastest 1st-order path of the loop filter is in
added delay and phase shift. the high-speed path of the modulator loop. Additional feed-in
A. Compensation of the FIR Feedback Delay paths to the last stage integrator will tend to create parasitic
Techniques for the compensation of the FIR feedback delay poles and result in increased delay. Hence, rather than
have been proposed in recent works [19][20][25]. In [19], an connecting the compensation path to the last stage integrator,
analog feedback compensation path is employed. This as in [20], the compensation path C(z) feeds into the input of
technique increases the complexity, and the implemented NTF the second integrator. Simulations shows that this simple
is changed from the ideal one. Ref. [20] adopts another FIR change reduces the required unity gain bandwidth (UGBW) of
path to compensate for the delay of the main FIR feedback. the opamp of the last stage integrator from 1.6 times sampling
This compensation path is fed into the last-stage trans- frequency FS to 1.2 FS while maintaining the same
impedance amplifier (TIA) output. Ref. [25] feeds the FIR performance.
compensation path to the input of the last stage integrator. One concern about the feedback compensation path C(z) is
the increased output swing at the first-stage integrator output,
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2020 20
20
1-bit w/o w/o
single-bit FIR
FIR 1-bit w/ FIR
single-bit w/ FIR

Occurrences
1515 15
15

1010 10
10

55 55

σj = 0.1%TS
00 00
-1
-1 0
0
Voltage [V]
11 -1
-1 00
Voltage [V]
11
Voltage [V]
(a)

20
20 2020
2-bit w/o FIR
2-bit w/o FIR 2-bit 2-bit
w/ FIRw/ FIR

Fig. 10. In-band-noise due to a σj = 0.1%TS clock jitter versus the FIR

Occurrences
tap length N, for both single-bit and 2-bit FIR DAC. 15
15
1515

Occurrences

Occurrences
due to the input signal content feeding into this node. 10
10 10
10

However, the compensation path C(z) can have a high-pass

profile, as shown in Fig. 9(b). This is because the added low- 55 55
pass main FIR F(z) mainly affects the high-frequency
00 00
response of the loop filter, and hence the compensation path -1
-1 0
0
Voltage [V]
11 -1
-1 00
Voltage [V]
11
Voltage [V]
C(z) only needs to compensate the medium- to high-frequency (b)
loop gain. Fig. 11. Histograms of the loop filter input with or without FIR feedback for
Thus, the signal content is further attenuated before feeding (a) 1-bit internal quantization (b) 2-bit internal quantization.
into this node, and the output swing at the first-stage integrator
can be kept at a reasonable level, as shown in Fig. 9(c), which
referred noise power J’ even with the in-band attenuation by
illustrates the histograms of the integrator output swings,
the first integrator, as in (3). For high values of N, the
normalized to the full scale of the quantization. Note that the
compensation path C(z) may cancel the effects of F(z) in
low output swing of the first-stage integrator is mandatory for
reducing the input-referred noise power due to the clock jitter.
low-voltage design.
In the behavioural simulation, a 0.1% rms clock jitter was
B. FIR Filter and Feedback DAC Design Considerations applied to the sampling clock period in the feedback path. The
Eq. (2) shows that the FIR feedback DAC reduces the in-band-noise due to the clock jitter is plotted as a function of
sensitivity to clock jitter, due to its high frequency attenuation. the FIR filter order N for both single-bit and 2-bit FIR
This implies that increasing N must result in improved feedback DACs. Fig. 10 compares the in-band noise power for
performance in terms of the sensitivity to the clock jitter, as single-bit and 2-bit internal resolutions as the FIR order N
more shaped quantization noise is filtered out. However, this increases. An NTF with an out-of-band gain (OBG) is chosen
holds true only for F(z) with a small number of tap N. As N to be 1.5 for a CTDSM with a single-bit quantizer, according
increases, the main FIR feedback path F(z) exhibits better to Lee’s rule [36], and OBG = 2 for the one with a 2-bit
selectivity and higher stop-band attenuation, as shown in Fig. quantizer. As Fig. 10 shows, for FIR tap length N > 3, the in-
9(a). In other words, F(z) with larger N results in larger band noise power due to a 0.1% clock jitter saturates for both
attenuation in the medium-to-high frequency range. Therefore circuits.
it requires a compensation path C(z) with higher out-of-band Hence, this device uses a 3-tap FIR filter to achieve reduced
gain to stabilize the loop. This is illustrated in Fig. 9(b), where clock jitter sensitivity while maintaining design simplicity.
the frequency response of C(z) with different FIR lengths N is Fig. 11(a)(b) compares the histograms of the loop filter input
plotted. It is seen that F(z) with larger N leads to higher out-of- with or without the FIR feedback path for both single-bit and
band-gain of C(z). 2-bit quantization, demonstrating the linearity advantage due
From (2), the input-referred jitter-induced noise power J’ to the introduction of the FIR feedback path. As shown in Fig.
due to C(z) can be found as: 11(b), the use of a 2-bit feedback achieves much smaller input
swing compared to using a single-bit feedback. A 2-bit 3-tap
 FIR feedback branch was therefore adopted in our work.
JC ( z)
J' OSR
d (3)
0 G1 ( j )
V. CIRCUIT IMPLEMENTATION
 2jit  lsb
2

1  e j  NTF  e j  C  e j  d (4)
 2
JC ( z)  2
TS  OSR  0
The overall schematic of the CT ∆Σ modulator is shown in
Fig. 12. It includes a CT loop filter, a 2-bit flash quantizer, an
where G1(jω) is the frequency response of the first-stage FIR filtering feedback DAC F(z) with its compensation path
integrator, and JC(z) is the noise power due to C(z). C(z), and the reference-switching matrix for ELD
As (4) shows, higher out-of-band gain of C(z) tends to compensation and DWA. The key building blocks are
increase the jitter-induced noise power, and hence the input- described next.
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Rr
Rff2 GBW1 = 1FS GBW2 = 0.5FS GBW3 = 1.2FS -gmff
Rf
Rff1 C1 C2 C3
2-bit QTZ VINP VOUTN
VIP R1 R2 R3
X gm1 -gm2
DOUT
VIN R1 R2 R3 CMP[3]

C1 C2 Rf C3 QTZ
Rff1 3 Vref Fig. 13. Block diagram of the NCFF opamp.
Reference
Rff2 Switching Vref
Rr Matrix
ELD & DWA
0 Thermal Noise: 78 dB
TS
 Quantization Noise Only: 87 dB
2
2-b 2-b 2-b z -20
DAC1 DAC2 DAC3
3-tap
Ptr. Gen.
3-tap FIR Compensation
-40

PSD [dB]
F(z) C(z)
TS
 -60
2
z

Fig. 12. Schematic of the overall continuous-time ∆Σ modulator [13]. -80

-100
A. Loop Filter
The circuit of the opamp used in the loop filter is a two- -120
BW=15MHz
stage design that employs no capacitor feed-forward (NCFF) -140 6 7
compensation rather than a Miller capacitor [13][23]. The 10 10 108
single-end representation of the opamp block diagram is Frequency [Hz]
shown in Fig. 13. The feedforward path gmff creates a zero to Fig. 14. Simulated power spectrum density with only quantization noise,
stabilize the two-stage opamp. Compared to a Miller- and thermal noise also included.
compensated design, this architecture is more power-efficient,
since no extra power is spent on charging and discharging the DOUT Z-1 Z-1
Miller capacitors. Thanks to the FIR feedback DAC, the st 2nd
Tap 3rd Tap
1 Tap
linearity requirement of the first integrator is greatly relaxed. 2-bit FIR Switch-R DAC
2-bit FIR Switch-R DAC
All opamps used in the latter stages share the same topology. 2-bit FIR Switch-R DAC

The input resistance R1 and capacitance C1 of the first stage

integrator are chosen to be 2.5 kΩ and 1.5 pF, respectively. element #3

element #2
Power reduction and linearity enhancement can be achieved element #1
VREFN
by maximizing the R1 up to the thermal noise limit [37], which VREFP DINP DINP DINN

is given by: DTAP1

DINP DINP DINN

DTAP1 DTAP1 DTAP1

 R2 2  R1   (5)
2

PN  8kTBW  R1  RDAC 1 2  1   
 RDAC 3g m,OTA  RDAC  
 RDAC RDAC
where PN is the input-referred thermal noise of the modulator OUTN OUTP
and BW is the signal bandwidth; RDAC refers to the resistors To opamp virtual ground

used for feedback DAC, and gm,OTA represents the amplifier Fig. 15. Implemented 3-tap FIR DAC and its 2-bit switched-resistor
input transconductance. elements.
Fig. 14 shows the simulated modulator output power
spectrum density (PSD) with only quantization noise and with The SR DAC has a non-return-to-zero (NRZ) output. As
thermal noise also included. The quantization noise is shown in Fig. 15, the switches are located at the reference
designed to be well below the thermal noise and hence the levels, making the on-resistance of the switches unchanged
modulator performance is limited by the thermal noise. It with time. However, the distributed RC parasitics due to the
achieves an SQNR of 87dB and an SNR of 78 dB. resistor at the virtual ground of the loop filter may exacerbate
the inter-symbol interference (ISI) effects, and add loop delay.
B. FIR Feedback DAC Therefore great care has been taken in the sizing and routing
Rather than using a current steering DAC, this work of the SR feedback DAC.
adopted a switched-resistor (SR) feedback DAC. This was The FIR feedback DAC is implemented by a semi-digital
because for low-voltage (1 V) implementation the SR DAC is approach [24]. Equally weighted coefficients were chosen for
less noisy than a current-steering DAC, whose noise the main FIR feedback path F(z), whereas the coefficients of
performance is limited by the available voltage headroom. the compensation path C(z) were determined by using the
Also, the SR DAC can provide better matching performance Impulse-Invariant-Transformation (IIT).
than a current steering one with low headroom.
> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 8

80
80 SNR, 500kHz 78
78
SNDR, 500kHz SNR, 500kHz
VIN Loop 70 SNDR, 500kHz
70
Filter 76
76 SNDR, 1MHz
60
60 SNDR, 2MHz
CMP[3] DOUT SNDR, 3.9MHz
REF ELD

SNR [dB]

[dB]
[dB]
74
74

SNR [dB]
50
50

SNDR,SNR

SNDR, SNR
40
40
72
72

SNDR,

SNDR,
30
30
11 DWA
20
20 70
70

10
10
68
68
DR = 79.4 dB
00
ptr_eld ptr2 ptr1 ptr0 -10
-10 66
-80 -60 -20 -10 -5
-5 00
-80 -60 -40 0
Pointer Generation Logic Z-0.5 Input Amplitude
Input Amplitude[dBFS]
[dBFS]
Input
Input Amplitude [dBFS]
Amplitude [dBFS]

(a) (b)
Fig. 16. The implemented reference-switching matrix for ELD and DWA.
Fig. 19. Measured SNR/SNDR vs. input amplitude for (a) a 500 kHz input
and (b) a magnified plot at high input amplitudes for four different input
frequencies.

[dB]
90

Signal-to-Noise-Ratio [dB]
Signal-to-Noise-Ratio
80

70

60

50
Fig. 17. Die microphotograph of the prototype [13].
Peak
Simulated with FIR feedback
Peak 40
Measured with FIR feedback
-2 -1 0 1
10 10 10 10
00 Ain = -1.58dBFS Clock Jitter/Ts [%]
Fin = 500kHz
-20
-20 SNDR = 74.3dB Fig. 20. Measured and simulated SNDR as functions of the clock jitter.
PSD [dB]
[dB]

SNR = 77.3dB Signal Transfer Fuction

SFDR = 80.4dB
-40
-40 10
OutputPSD

5
Output

-60
-60
[dB]

0
-80
-80
|STF| [dB]
ADC
ADC

-5
|STF|

-100
-100 BW=15MHz

5 6 7 7 88 -10
10
10 10
10 10
10 10
10
Frequency [Hz]
Frequency [Hz] Simulated STF in this work
-15
Measured STF
Fig. 18. Measured modulator output spectrum (65,536-point FFT with 15
averages) [13]. BW
-20
-4 -2
0.0001
10 0.01
10 0.5
C. Reference-switching Matrix for ELD and DWA Frequency
Frequency [Fs][Fs]
The details of the reference-switching matrix for ELD Fig. 21. Measured signal transfer function.
compensation and DWA (Fig. 12) are shown in Fig. 16. The
two switching matrices are merged, and controlled by their The die was packaged in a 40-pin QFN package.
pointer generation logic. A four-layer board is used to characterize the chip. The sine
Once an output sample of the modulator is generated, the wave generated by the signal source (AWG710B) is applied to
pointer generator logic uses it to shift the reference voltage in a passive band-pass filter (Allen Avionics) with a center
the first matrix for ELD compensation. Then the shifted frequency of 500 kHz, and then converted to a differential
reference voltages are applied to the second matrix, and signal with a balun (Coilcraft PWB2010LB). An RF clock
shuffled according to the pointer generated by the DWA source (Agilent E4433B) is used to provide the clock signal of
algorithm. Both reference-switching operations are finished in 1.2 GHz. The modulator output bit-stream, transmitted by a
a half clock period. stubbed-series termination-logic (SSTL) interface, is captured
by a logic analyzer (TLA7012), and post-processed to obtain
VI. MEASUREMENT RESULTS the output spectrum.
The prototype CTDSM was fabricated in a 65 nm CMOS Running at a 1.2 GHz sampling rate, the modulator
process with MiM capacitors. It occupies an active core area dissipates 6.96 mW, of which 4.31 mW is consumed by the
of 0.16 mm2. The chip microphotograph is shown in Fig. 17. analog blocks, 2.17 mW by the digital blocks, and 0.47 mW
 > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 9

TABLE I
PERFORMANCE SUMMAY AND COMPARISON WITH PRIOR WORKS
[8] [26] [30] [19] [33] [31] [34] [11] [28] [29] [32]
Parameter This Work ISSCC JSSC JSSC JSSC JSSC JSSC JSSC ISSCC JSSC JSSC JSSC
2006 2011 2011 2012 2012 2012 2013 2013 2014 2014 2015
Topology FF-FB FF-FB CIFF CIFF FF-FB CIFF CIFF CIFF CIFF FF-FB MASH CIFF
Adder required No No No Active No Active Active Active No No Passive No
ELD Comp. R.S7 D.D3 D.D D.F4 D.D D.F D.F D.F C.S5 PLR6 D.F R.S
Technology(nm) 65 130 65 130 90 180 130 130 28 90 28 20
Area (mm2) 0.16 1.2 0.15 1.17 0.12 0.68 0.38 1.3 0.08 0.225 45 0.1
VDD (V) 1.0 1.2 1.2/1.3 1.2 1.2 1.8 1.3 1.2 1.2/1.5 1.2 0.9/1.8 1.2/1.5
FS (MHz) 1200 640 250 640 3600 800 1000 185 640 500 3200 2184
4.31 (Ana.)
Power (mW) 6.96 2.18(Dig.) 20 10.5 58 15 47.6 4 13.7 3.9 8.5 235 23
0.47 (Ref.)
BW (MHz) 15 20 20 20 25 16 15.6 10 18 25 45 80
FIN (MHz) 0.5 1 4 3.7 3.9 1 10 5 5 1 0.625 2 15 15
SNR (dB) 77.3 77.2 76.4 73.0 62.0 67.9 80.2 67 64.5 73.4 75.4 69.1 84.6 70
SNDR (dB) 74.3 74.1 73.7 74.0 60.0 63.9 73.3 65 59.8 71.9 73.6 67.5 72.6 67.5
DR (dB) 79.4 78.8 78.1 80.0 68.0 65.9 86.0 75 67.0 80 78.1 72.0 90 73
ENOB (bits) 12.0 12.0 12.0 12.0 9.7 10.3 11.9 10.5 9.7 11.7 11.9 11.8 11.8 10.9
FoM1Walden (fJ) 54.7 56.0 58.6 122.1 321.2 1110 79.4 1020 160 210 27.7 87.7 184 74.2
FoM2Schreier(dB) 172.7 172.1 171.4 170.0 160.8 151.1 178.2 160.3 162.9 168.6 174.7 162.2 172.9 168
1. FoMWalden = Power/(2(SNDR-1.76)/6.02 x 2 x BW). 2. FoMSchreier = DR + 10 x log10 (BW / P). 3. D.D: Discrete-time Differentiation as in [8]. 4. D.F: Direct Feedback as in [9].
5. C.S; Comparator Switching as in [11]. 6. PLR: Phase Lead Resistor as in [28]. 7. R.S: Reference-Switching as in this work.

by the reference voltage generators. Both the analog and simulated results.
digital blocks operate with 1 V supply voltages. The FIR feedback DAC will affect the signal transfer
Fig. 18 gives the measured ADC output power spectrum function (STF) of the modulator. A longer FIR filter results in
density (PSD) for a -1.58 dBFS input tone at 500 kHz. (The a more out-of-band peaking of STF [25], which is not
full scale or 0 dBFS is 2 VPP.) The sampling frequency was 1.2 desirable when an out-of-band blocker is present. The
GS/s. A 15-times averaged 65,536-point fast Fourier transform measured STF, along with the simulated one is shown in Fig.
with a Hanning window was used for spectrum analysis. The 21. They coincide, and show a peaking around 6 dB, which is
ADC achieved a peak SNR of 77.3 dB, and an SNDR of 74.3 much lower than in prior work with FIR feedback path
dB over a 15 MHz signal BW, resulting in an ENOB of 12. [19][25].
The measured SNR and SNDR are plotted for different input The performance of the ADC is summarized in Table I. It
amplitudes in Fig. 19(a) for a 500 kHz input tone. A dynamic compares the performance of the state-of-the-art ADCs. It can
range of 79.4 dB was achieved. This validates the use of be seen that the ADCs in which the active adder was
switched resistor feedback DAC with 1 V power supply. The eliminated achieved better power efficiency, as in [8][11][19]
SNDR curves for various input frequencies near the full-scale [29]. Furthermore, the ELD compensation without the
amplitude are plotted in Fig. 19(b). The peak SNDR is conventional direct feedback path relaxes the requirements of
degraded by 0.6 dB over an input signal frequency range from the last integrator stage. This change helps to achieve an even
500 kHz to 4 MHz. The rms jitter of the applied clock source better FoM, as in [11]. In our work, by removing the direct
is around 300fs, or 0.1% of the sampling clock period. feedback path, the required UGBW of the opamp of the last
To verify the effectiveness of the FIR feedback DAC, the integrator could be reduced from 1.6 FS to 1.2 FS. The
measured and simulated SNDRs with FIR feedback path proposed converter achieves a peak SNDR of 74.3 dB with 1
against the clock jitter are shown in Fig. 20. The clock jitter V power supply. The Walden and Schreier Figures of Merit
injection was obtained using the software interface to Agilent are below 60 fJ/step and above 170 dB, respectively, which
E4438C. The applied clock jitter is then characterized by the compare favorably with the state-of-the-art.
spectrum analyzer Agilent E4440A. It can be seen from Fig.
20 that the modulator achieves a measured SNDR larger than VII. CONCLUSION
70 dB when the applied rms clock jitter is less than 3 ps, A ∆Σ–based ultrasound beamforming receiver for
which is 0.4% of the clock period. Within this range, the biomedical imaging was described. It allows finer dynamic
thermal noise contributed by the input-referred noise of the delay increments to achieve better image quality. A 3rd-order
loop filter and switched-resistor feedback DAC dominates. In CT ∆Σ modulator clocked at 1.2 GHz and operating with a 1
addition, even-order harmonic distortion is also found and V power supply, was described. A digital ELD compensation
contributes to the performance degradation due to the ISI technique is proposed to eliminate the power-hungry adder
effect in the feedback DAC. This results in a levelling of the used in earlier circuits. Also, the DWA logic is incorporated
noise in the measured result, which includes the thermal noise, into the reference-switching matrix used in the digital ELD
the quantization error and the jitter-induced error. With the compensation, in order to minimize the delay in the critical
clock jitter larger than 0.6%TS, the noise power induced by the path. Finally, a 2-bit 3-tap FIR filter is introduced in the
clock jitter becomes dominant, and matches well with the feedback path, to make the modulator less susceptible to the
> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 10

clock jitter. The effect of increasing the FIR tap length on the [19] P. Shettigar and S. Pavan, “Design technique for wideband single-bit
continuous-time ∆Σ modulators with FIR feedback DACs,” IEEE J.
clock jitter sensitivity was analyzed. Fabricated in a 65 nm Solid-State Circuits, vol. 47, no. 12, pp. 2865-2879, Dec. 2012.
CMOS process, the prototype modulator achieves a 79.4 dB [20] J. Gealow et al., ‘‘A 2.8mW ∆Σ ADC with 83 dB DR and 1.92MHz BW
dynamic range, 77.3 dB SNR and 74.3 dB SNDR over a 15 using FIR outer feedback and TIA-Based Integrator,” IEEE Symp. VLSI
MHz signal bandwidth, with a FoM of 58.6 fJ/conversion-step. Circuits, pp. 42-43, June 2011.
[21] W. Yang, et al., “A 100mW 10MHz-BW CT ΔΣ modulator with 87dB
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ACKNOWLEDGEMENTS Feb. 2008.
The authors would like to thank Nancy Qian, Ed Liu, Philip [22] L. Doerrer et al., “10-bit, 3 mW continuous-time Sigma-Delta ADC for
UMTS in a 0.12 µm CMOS process,” in Proc. European Solid-State
Elliott and John Scampini from Maxim Integrated, and Brian Circuits Conf., pp. 245-248, 2003.
Young for the helpful technical discussions and insights. The [23] B. Thandri and J. Silva-Martinez, “A robust feedforward compensation
authors are also grateful to Patrick Chiang for arranging the scheme for multistage operational transconductance amplifiers with no
miller capacitors,” IEEE J. Solid-State Circuits, vol. 38, no. 2, pp. 237-
chip fabrication. 243, Feb. 2003.
[24] D. K. Su and B. A. Wooley, “A CMOS oversampling D/A Converter
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From 2010 to 2012, he was a Design Engineer with NXP Delta-Sigma Data Converters (IEEE Press/Wiley, 2005). He
Semiconductors, Shanghai, China. He was a Design Intern also wrote approximately 300 papers in engineering journals
with Analog Devices, Wilmington, MA, during the summer of and conference proceedings.
2014. His research interest is in the area of high-speed delta- Dr. Temes was Editor of the IEEE TRANSACTIONS ON
sigma modulators. CIRCUIT THEORY and Vice President of the IEEE Circuits
He received the Best Student Paper Award in Asian and Systems (CAS) Society. In 1968 and in 1981, he was co-
Technical Conference held by Analog Devices in 2009 and A- winner of the IEEE CAS Darlington Award, and in 1984
SSCC Student Travel Grant Award in 2014. winner of the Centennial Medal of the IEEE. He received the
Andrew Chi Prize Award of the IEEE Instrumentation and
Chia-Hung Chen received B.S. degree in Measurement Society in 1985, the Education Award of the
nuclear engineering from National Tsing IEEE CAS Society in 1987, and the Technical Achievement
Hua University, HsinChu, Taiwan, and M.S. Award of the IEEE CAS Society in 1989. He received the
degree in electrical engineering from IEEE Graduate Teaching Award in 1998, and the IEEE
Columbia University, New York, NY. Millennium Medal as well as the IEEE CAS Golden Jubilee
During 2009 to 2013, he studied his Ph.D. in Medal in 2000. He was the 2006 recipient of the IEEE Gustav
Oregon State University, Corvallis, OR. His Robert Kirchhoff Award, and the 2009 IEEE CAS Mac
doctoral research is in micro-power delta-sigma incremental Valkenburg Award. He is member of the National Academy
data converters. of Engineering.
Before his Ph.D. study in Oregon State University, he was
had been with Analog Devices Taiwan during 2003 to 2006.
And during 2006 to 2009, he was with start-up IC design
houses in Taiwan, designing audio codec circuits, DC-DC
power converters and PLL. In the summer of 2011, he was a
design intern with Maxim Integrated, CA. After his Ph.D.
degree, he was with Mediatek, Woburn, MA during 2013 to
2014. He is currently with Oregon State University, as a post-
doctoral scholar. His research interests are in the design of
precision analog circuit, energy-efficient data converters.

Tao He received the B.Sc degree in electrical

and computer engineering from University of
Macau, Macau, China, in 2010. Since 2012,
he is now with school of electrical
engineering and computer science in Oregon
state university, pursuing his Ph.D. degree.
His research interest includes high
performance analog and mixed-signal circuit
design in advanced CMOS technology.

Gabor C. Temes (SM’66–F’73–LF’98)

received the undergraduate degrees from the
Technical University of Budapest and
Eötvös University, Budapest, Hungary, in
1952 and 1955, respectively. He received the
Ph.D. degree in electrical engineering from
the University of Ottawa, ON, Canada, in
1961, and an honorary doctorate from the Technical
University of Budapest, Budapest, Hungary, in 1991.
He held academic positions at the Technical University of
Budapest, Stanford University, Stanford, CA, and the
University of California at Los Angeles (UCLA). He worked
in industry at Northern Electric R&D Laboratories (now Bell-
Northern Research), Ottawa, Canada, as well as at Ampex
Corp. He is now a Professor in the School of Electrical
Engineering and Computer Science at Oregon State
University. His recent research has dealt with CMOS analog
integrated circuits and data converters. He co-edited and
coauthored many books; the most recent one is Understanding