<br>

Router 1*3- RTL

Design and Verification

HDL: Verilog
HVL: System Verilog
TB Methodology: UVM
Tools: VCS, Questa sim, Design Compilers, and ISE
Linting: Synopsis SPY Glass
Name: POGIRIARJUN

Description: The router accepts data packets ona single 8-bit port and routes them to one of
the three output channels channel0, channel1 and
channel2.

ROUTER TOP VIEW AND INTERNAL MODULES CONNECTION:

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<br>

Router- Top-Level Block

clock
5ERdáta out 0

resetn
To
dataout 1 Destination
read_enb_0 Network
From data out2
Destination read _enb_1
Network Router
read_enb _2 1X3 valid_out_0
valid_out_1 To Destination
Network
data in valid _out 2

From Source
Network
pkt_valid error] To Source
busy Network

Router- Input Protocol

clock

resetD

packet vald
data PD PD PR
bugy

es
PI

:Header Byte
:
PD Payload Data
PR : Packet Parity byte
PM : Parity Mismatch

Router- Output Protocol

clock

etn
packetvalid
data
PDPDXPDXPDXPR
vid _out_x

read enb
data Out_x
<EX PD
PDX PD XPR
:
Header Byte
PD : PayloadData
PR : Packet Parity byte
: 0.1.2
<br>

**
*
*k
///******
* *
t*** k **** * //
3
4 RTL DESIGN
5
/f** *
*** * * * * * **** * *
** * ** * * ** * * * ** * * ** * * ** t*
* *
** ** * ***** ***** **** * * * */

1| fifo
10 module fifo 16x9 router (clk, reset,data in,write enb, read enb,soft reset, lfd state,full,
empty ,data out);
11
12 1 declaring the input and ouput ports
13
14 input clk, reset, write _enb, read _enb,lfd_state, soft_reset;
15 input [7:0]data in;
16 output full,empty;
17 output reg [7:0] data out;
18
19 7/ declaring the internal write addr read addr memory and fifi down count reg
20
21 reg [5:0] write addr, read addr;
22 reg (8:0]mem [0 :15] :
23 reg [6:0]fifo down counter;
24 reg lfd state temp;
25 integer i;
26
27 /* delaying the lfd state bcuz its arriving at one clock from the fsm mean
28 while data header comes at 2 clock pulses from register so we synxc the
29 two things so we using d flip flop to genrate 1 clk delay for lfd state */
30
31
32 always@ (posedge clk)
33 begin
34 if(!reset)
35 lfd state temp<=0;
36 else
37 lfd_state temp<=lfd_state;
38 end
39
=
40 1/ assign lfd state lfd state temp;
41
42 /*always@ (posedge clk)
43 begin
44 if (write enb && (! full) )

45 mem
[write _addr [3 :0]] [8] <- lfd_state temp;
46 else
mem <= mem
47 [write addr [3 :0] [8] ]
[write addr [3 : 0]] [81
48 end k /
49
50 7/ increment the write and read address
51
@
52 always (posedge clk)
53 begin
54 if (!reset )

55 {read addr, write addr <=0; }

56 else{ if (soft_reset)
57 write_addr, read addr) <=0;
58 else
59 begin
&& )
60 if (write enb (!full)
61
62 if (read enb &&
(!empty) )
63 read addr <= read addr +l;
64 end
65 end * /
66 7/ increment the read address
67
68 /*always@ (posedge clk)
<br>

69 begin
70 if (!reset)
71 read addr<=0;
72 else if (soft reset)
73 read addr<=0;
74 else if (read enb && (!empty) )
75 read addr <= read addr +l;
76 end
77 */
78 //writing opearion
79
80 always@ (posedge clk)
81 begin
82 if (!reset)
83 begin
84 for (i=0 ; i<16 ; i=itl)
85 begin
86 mem [i]<=0;
87 end
88 Write addr<=0;
89 end
90 else if (soft reset)
91 begin
92 for (i=0;i<l 6;i=i+l)
93 begin
94 mem[i]<=0;
95 end
96 Write addr<=0;
97 end
98 else
99 if (write enb && (!full) )

100 begin
101 mem[write_addr [3:0]]<<{lfd_state_temp,data_in}:
102 Write addr <= write: addr+1;
103 //mem [write addr [3 0]] [8] <= lfd _state temp:
104 end
105
106 end
107
108 // read opearion
109
110 always@ (posedge clk)
111 begin
112 if(!reset) begin
113 data Out<=0 ;
114 read addr<=0; end
115 else if (soft reset) begin
116 data out<=8 'bzzzz zzzz;
117 read addr<=0; end
118 else if (fifo down counter ==0 &&
data out !=0)
119 data out<=8'bzzzz zZZZ;
120 else
121 if (read enb &&
(!empty))
122 begin
123 data out<=mem [read addr [3:0]1;
124 read addr <= read addr +l;
125 end
126 end
127 7* fifo count logic when hear byte recived it check that
down 8 bt of the byt
128 it is one then fifo counte load with playload data then after ti decremented every clk
pulse/
129
130
131 always@ (posedge clk)
132 begin
133 if (! reset)
134 fifo down counter<=0;
135 else if (soft_ reset)
136 fifo down counter<=0;
<br>

137
138 else if (read enb && !empty)
139 begin
140 if (mem [read addr [3:0]] [8]==1'bl)
141 fifo down counter<=mem [read addr [3:0]][7:2] +1 ;
142 else if (fifo down counter != 0)
143 fifo down counter<=fifo down counter-l;
144 end
145 end
146 // fifo full signal logic and empty signal logic
147
148 assign full = (( (write addr [3:0] == read addr [3:01) && (write addr [41 != read addr [4
1))?1bl:1'b0;
[3: 0] ==
=
149 assign empty =( (write addr read addr [3 0])
: && (write addr [4] read addr [4
]))?1'bl:1'b0;
150
151 endmodule
152
153
154 1| fsmm
155
156 module fsm router controller (clk, reset,pkt valid, busy, parity done,data in,soft reset 0,
soft_ reset 1,soft_reset _2, fifo_full,low pkt_valid, fifo_empty 0, fifo_empty_l,fifo _empty_2,
detect_add,ld_state, laf_state, full_state, state) ;
write enb _reg,rst_int_reg,lfd_
157
158 1/ declaring the input and output ports
159
160 input clk, reset,pkt_valid, parity_done, soft_reset_0, soft_reset_1,soft_reset_2,
fifo_full, low pkt_valid, fifo _empty_0,fifo _empty1,fifo_empty 2;
161 input [l:0] data in;
162 output detect add, ld state, laf_state, full_state,rst int_reg, lfd state ;
163 output busy, write enb regi
164 / parameter and internal next state,present state regs declarations
l65
l66 parame ter
DECODE ADDRESS=3 'b000,LOAD FIRST DATA=3'b001, WAIT TILL EMPTY=3'b010,
,
LOAD DATA=3'b011 FIFO FULI STATE=33'b100, LOAD AFTER FULL=3'bl01,LOAD PARITY=3 'bll0,
CHECK PARITY ERROR=3' ;
Blll
l67 reg [l:0] addr data;
l68 reg [2:0]present,next;
169
170 // storng detecting the destination address signal
171
172 always@ (*)
173 begin
174 if(!reset)
175 addr data<=0;
176 else
177 begin
178 if (detect add)
179 addr data <= data in;
180 end
181
182 end
183
184 7 sequntial logic for present state
185
186 always@ (posedge clk)
187 begin
188 if (! reset)
189 present<=DECODE ADDRESS:
190 else if (soft reset 0 || soft reset 1 || soft reset 2)
191 present<=DECODE ADDRESS;
192 else
193 present<=next;
194 end
195
196 17 combinational logic for next state
197
198 always@ (*)
<br>

199 begin
200 case (presentt)
201 DECODE ADDRESS:
202 if ((pkt
valid && addr data == 2' d0 && fifo empty 0) || (
pkt valid && addr data==== 2'dl &&& & fifo empty 1) || (
pkt_valid &&
addr_data 2d2 fifo empty_2))
203 begin
204 next=LOAD FIRST DATA;
205 end
206 else if ((pkt&& valid && addr data == 2' do && (!fifo empty 0)) ||(
pkt valid addr data == 2'dl && (!fifo empty 1)) | (pkt valid
&&
addr data 2
= && (!fifo empty 2)))

207 begin
208 next=WAIT TILL EMPTY;
209 end
210 else
211 begin
212 next=DECODE ADDRESS;
213 end
214 WAIT TILL EMPTY:
=
215 if( (addr data 2' d0 && fifo empty 0) ||
addr data == 2'dl && fifo empty 1) || (addr data
= 2'd2&&
fifo _empty_2))
216 begin
217 next=LOAD FIRST DATA;
218 end
219 else
220 begin
221 next=WAIT ILL EMPTY;
222 end
223 LOAD FIRST DATA:
224 next=OAD DATA;
225 LOAD DATA
226
227 begin
if (fifo_ full)
228 next=FIFO FULL STATE;
229 end
&& )
230 else if ((!fifo full) (!pkt valid)
231 begin
232
;

next=LOAD PARITY
233 end
234 else
235 begin
236 nextFLOAD DATA;
237 end
238 FIFO EULL STATE :
239 if(! fifo full)
240 begin
241 next=IOAD AFTER FULL;
242 end
243 else
244 begin
245 next=FIFO FULL STATE;
246 end
247 LOAD AFTER FULL:
248 if((!parity_done) &&
(!low_pkt_valid) )
249 begin
250 next=LOAD_DATA;
251 end
( (!parity &&
252 else if done) low pkt valid)
253 begin
254 next=LOAD PARITY ;
255 end
256 else if (parity done)
257 begin
258 next=DECODE ADDRESS;
259 end
260 LOAD PARITY
<br>

261 next=CHECK PARITY ERROR;

262 CHECK PARITY ERROR:
263 if (fifo full)
264 begin
265 next=FIFO FULL STATE;
266 end
267 else
268 begin
269 next=DECODE ADDRESS;
270 end
271 default:next=DECODE ADDRESS ;
272 endcase
273
274 end
275
276 1/ combinational logic for output
277
278 77 busy is going to low at decode state and load stae other states it was
279 17 high bcaz it is not
280 1/ allowing new data from the sourece
281 assign busy = (present DECODE ADDRESS || present = LOAD DATA) ?1 'b0:1'bl;
282
283
284 assign detect add =(present DECODE ADDRESS) ?1 'bl:1 'b0;
285 assign ld state = (present LOAD DATA) ?1 'bl:1b0;
286 assign laf state = (present LOAD AFTER FULL) ? 1'bl:1 'b0;
287 assign full state = (present FIFO FULL STATE) ?1 'bl:1'b0;
288 assign lfd state =(present LOAD FIRST DATA) ?1 'bl:1!b0;
289 assign rst int reg= (present = CHECK PARITY ERROR) ?1 'bl:1'b0;
290
,
291 1/ write enb reg going tp high in these state bcaz
only these stae have
292 1/ capabul for sending payload and data to fifo when write enb reg is
parity
we know to send the data
293 // high then only which fifo destinastion.neccasary
294 17 at he particluar stae
295
296
297 assign
LOAD AFTER
write enb ? reg
FULL)
= (present
1'bl:1'b0;
= LOAD DATA || present == LOAD PARITY |T present

298
299 endmodule
300
301
302 11 register
303
304
305 module register router (clk, reset,pkt valid,data in, fifo full, rst int reg,detect add,
;
ld state, laf_ state, full_state, lfd_state, parity_ done,low pkt valid,error, dout)
306
307 1/ declaring the regs and wires
308
309 inputclk, reset,pkt valid, fifo full,rst int reg,detect add, ld state, laf state,
full state, lfd state;
310 input [7:0] data_in;
311 output reg error, low pkt valid,parity done;
312 output reg [7: 0] dout;
313
314 1/ creating 4
internal register for header byt storing, internal parity
315 // byte, packet parity byte, fifio full state byte each are 8 bits bcz all are bytes
316
317 reg [7: 0] header byte, internal parity byte, packet parity byte, fifo full_state byte;
318
319 writing logic for header byte sstoring
320 // header store add detect address and presetn state at load fikrst data and
321 1/ pkt valid is high and corect address destination
322
323 always @
(posedge clk)
324 begin
325 if(!reset)
326 begin
<br>

327 header byte<=0;

328 end
329 else
330 if (pkt valid &&
detect add &&
(data in[1: 0] != 2'd3))
331 begin
332 header_byte <=data_in;
333 end
334
335 end
336 11 logic for fifo sull state byte
337 // stroing the data in after full state
338
@
339 always (posedge clk)
340 begin
341 if(! reset)
342 fifo full state byte <= 0;
343 else if (ld state &&
fifo full)
344 full state byte
fifo <= data in;
345 else if (detect _add)
346 fifo full state byte <= 0;
347 else
348 fifo full state byte <= fifo full state byte ;

349
350 end
351
352
353 1/ writing logic for dout
354 // data out is wOrks only at play load data in header data writhout error
355
@
356 always (posedge clk)
357 begin
358 if (!reset)
359 begin
360 dout<=0;
361 end
362 else if (detect add && pkt _valid &&
(data in[l:0] != 2'd3) )
363 begin
364 dout <=dout ;
365 end
366 else if (lfd state)
367 begin
368 dout<=header byte;
369 end
370 else if (ld state &&(!fifo full) )
371 begin
372 dout <=data in;
373 end
374 else if (full state)
375 begin
376 dout <= dout;
377 end
378 else if (laf state)
379 begin
380 dout<=fi fo_full_state_byte;
381 end
382 else
383 begin
384 dout <=dout;
385 end
386 end
387
1
388 writing logic for internal parity
389 7
first it is ex or opeartion with header byte and then after contious ex or
390 7/ wuith each pay load data stored into internal parity
391
392
393 alwayse (posedge clk)
394 begin
<br>

395 if (! reset)
396 begin
397 internal parity byte<=0;
398 end
399 else if (detect add)
400 begin
401 internal parity_byte<=0;
402 end
403 else if (lfd state)
404 begin
405 internal parity_byte <= internal parity_byte header byte;
406 end
407 else if (ld state &&
!fifo full)
408 begin
409 internal_parity_byte <= internal_parity_byte ^ data_in;
410 end
411 else
412 begin
413 internal parity byte <= internal parity byte;
414 end
415 end
416
417 1/ writing logic for packet parity
418 1/ packet we parity check wheather state uis parity data only in this state
419 1
only are getting parity of packets
420
421 always e (posedge clk)
422 begin
423 if (!reset)
424 begin
425 packet parity_ byte <= 0;
426 end
427 else if (detect add)
428 begin
429 packet_parity_byte <=0;
430 end
&& &&
431 else i£ (ld_state (!pkt_valid) (!fifo_full))
432 begin
433 packet parity byte <=data in;
434 end
435 else if (!pkt valid &&
rst int reg)
436 begin
437 packet parity byte<=0;
438 end
439 else
440 begin
441 packet parity byte <= packet parity byte;
442 end
443 end
444
445 7/parity done logic
446
447
448 always@ (posedge clk)
449 begin
450 if (!reset)
451 begin
452 parity done <= 1'b0;
453 end
454 else if (ld state && (!pkt valid) && (!fifo full))
455 begin ;
456 parity done <=1'bl
457 end
&& &&
458 else if (laf_state (!parity done) low pkt_valid)
459 begin
460 parity_done <=1'bl;
461 end
462 else
463 parity done <=1'b0;
<br>

464 end
465
466
467 // error logic
468
469 always@ (posedge clk)
470 begin
471 i£(!reset)
472 error <=1'b0;
473 else if ( (packet parity byte != internal parity byte) &&
parity_done)
474 error <=1bl;
475 else if( (packet_
error <=1 'b0:
parity_byte = internal_ parity_byte) && parity_done)
476
477 else
478 error <= 0;
479
480
481 end
482
483 1/ low packet valid logic this means if ther is no packets packet goes low so
484 1/ this is negation of pkt valid
485
486 always@ ( *)
487 begin
488 if (!reset)
489 low pkt valid <=0;
490 else if (parity done)
491 low pkt valid <=1'bl;
492 else if(!pkt valid)
493 low pkt valid <=1'b1;
494 else
495 low pkt valid <=0;
496
497 end
498 endmodule
499
500
7
501 synchronizer
502
503
504 module synchronizer router (detect add,data in, write enb reg, clk,reset,vld out 0,vld out 1

,vld out 2,read enb 0,read enb 1, read enb 2,write enb, fifo full,empty 0, empty 1,empty 2,
soft reset 0,soft reset 1, soft reset 2, full 0, full 1, full 2) ;
505
506 7/ declaring the input and output ports
507
508 input detect add,Write enb reg,clk, reset, read enb 0,read enb 1,read enb 2,empty 0,
empty 1,empty2,full_ 0,full_1,full 2;
509 input [1:0]data in;
510 output vld out 0,vld out_1,vld out 2:
511 output reg [2:0]write enb;
512 output reg fifo full;
513 output reg soft reset 0,soft reset 1, soft reset 2 ;
514
515 // creating the internal register
516
517 reg [1:0] addr data;
518 reg [:0] out fifo 0 counter;
519 reg [6:0]out_fifo_1_counter;
520 reg [6:0]out fifo 2_counter;
521 7/ storng detecting the destination address signal
522
523 always (posedge clk)
524 begin
525 if (!reset)
526 addr data <=0;
527 else if (detect add)
528 addr_ data <= data_in;
529 end
<br>

530
531 1/ destinatoin addrss decode ing and sending write enb signal sending for
532 77 respective fifo
533
534 always@ (*)
535 begin
536 if (! reset)
537 write enb=0;
538 else
539 begin
540 if (write enb reg)
541 begin
542 case (addr data)
543 2'b00 :write enb=3'b001;
544 2'b01:write enb=3'b010;
545 2b10:write enb=3'bl00;
546 default:write enb=3'b000 ;
547 endcase
548 end
549 else
550 write enb=3 'b000;
551 end
552 end
553
554 1
fifo full signal asserted based on full status of each fifo
555
556 always@ (*)
557 begin
558 if(!reset)
559 fifo full=0;
560 else
561 begin
562 case (addr data)
563 2'b00:fifo_full=full_0;
564 2'b01:fifo full=full 1;
565 2'b10:fifo full=full 2;
566 default:fifo full=0;
567 endcase
568 end
569 end
570 1/ valid out signal genration
571
572 assign vld out 0=~empty 0;
573 assign vld out 1=~empty 1;
574 assign vld out 2=~empty 2;
575
576 1/ soft start signal generation foer each fifo
577 // the respective soft reset signal go high if read en is not asserted
578 17 with in colk cycle so we take colkc counter to counte clks
579 // vld out being assrent being assreted and taking the reset Condiotn also
580
= (out counter
wire count
=
581 0 fifo 0 6' d29) ? 1'bl:1'b0;
==
582 wire count 1 =
(out fifo 1
counter 6' d29) ?1'bl:1'b0;
583 wire count 2 = (out fifo 2 counter 6'd29) ? 1'bl:1'b0;
584
585 always@ (posedge clk)
586 begin
587 if (!reset)
588 begin
589 soft reset 0<=0;
590 out fifo 0 counter<=0;
591 end
0)
592 else if (!vld_out
593 begin
594 soft reset 0<=0;
595 out_fifo_0_counter<=0;
596 end
597 else if (read enb_0)
598 begin
<br>

599 soft reset 0<=0;

600 out fifo 0 counter <=0;
601 end
602 else if (count 0
603 begin
604 out fifo 0 counter <=0;
605 soft reset 0<=1;
606 end
607 else
608 begin
609 out fifo 0 counter <= out fifo 0 counter+1;
610 soft reset 0<=0;
611 end
612 end
613
614 always@ (posedge clk)
615 begin
616 if(! reset)
617 begin
618 Soft reset 1<=0;
619 out fi fo 1 counter<=0;
620 end
621 else if (!vld out_1)
622 begin
623 soft reset l<=0;
624 out fifo 1 counter<=0;
625 end
626 else if (read enb_1)
627 begin
628 soft reset 1 <=0;
629 out fifo 1 counter <=0;
630 end
631 else if (count_1)
632 begin
633 out fifo 1 counter <=0;
634 soft reset 1<=l;
635 end
636 else
637 begin
638 out fifo 1 counter <= out fifo 1 counter+l;
639 soft eset 1<=0;
640 end
641 end
642
643 always@ (posedge clk)
644 begin
645 if (!reset)
646 begin
647 soft reset 2<=0;
648 out fifo 2
counter<=0;
649 end
650 else if(!vld out 2)
651 begin
652 soft _reset 2<=0;
653 out fifo_2_counter<=0i
654 endl
655 else if (read enb 2)
656 begin
657 soft reset <=0; 2

658 out fifo 2 counter <=0;

659 end
660 else if (count 2)
661 begin
662 out fifo 2 counter <=0;
663 soft reset 2<=1;
664 end
665 else
666 begin
667 out fifo 2 counter <= out fifo 2 counter+1;
<br>

668 soft reset 2<=0;

669 end
670 end
671 endmodule
672
673
674
675 1/ top module
676
677 module router top (clk, reset, read enb 0,read enb 1, read enb 2,data in,pkt
;
valid, data out 0
,data out 1, data out 2,valid out 0,valid out 1,valid out 2,error,busy)
678
679 1/ input and output declaration
680 input clk, reset, read enb 0,read enb 1,read enb 2,pkt valid;
681 input [7:0] data in;
682 output [7:0] data out 0,data out 1, data out 2;
683 output valid out 0, valid out 1,valid out 2,error,busy;
684 77 declaring the internal wire for sub block connections
685 7/ fifo output wires
686
687 wire empty_0,full_0,empty_ 1, full_ 1, empty_2, full_2;
688
689 7/ synchronizer output wires
690
691 wire soft reset 0,soft reset 1,soft_ reset 2;
692 wire [2 : 0]write enb;
693
694 11 fsm output wires
695
696 wire detect add, ld state,laf_state, full state, write enb reg,rst int reg, lfd_state ;

697
698 // register output internal connections
699
700 wire parity done, low pkt valid;
701 wire [7:0] data out;
702
703 /*
704 module
fsm router controller (clk, reset, pkt valid, busy, parity done, data in, soft reset 0, soft rese
t_ 1, soft reset 2, fifo full, low pkt valid, fifo empty 0,fifo empty l, fifo empty 2, detect ad
d, ld state, laf_state, full_state, write enb reg, rst int reg, lfd_ state) ;
705 */
706
707 fsm router controller FSM(clk, reset,pkt valid,busy, parity done, data in[1:0] ,soft reset 0,
soft_reset_1, soft_reset_2,fifo_full,low_pkt _valid, empty_0,empty_1,empty_2, detect_add,
ld state, laf state,full state, write enb reg,rst int reg, lfd state);
708
709 /*
710 module
synchronizer router (detect add, data in, write enb reg, clk, reset, vld out 0, vld out 1, vld ou
t 2, read enb 0, read enb 1, read enb 2, write enb, fifo full, empty 0, empty l, empty 2, soft res
et 0, soft_reset 1, soft_ reset 2, full_ 0, full 1, full_ 2) ;
711 */
712
713 synchronizer router SYNCHRONI ZER(
714 detect add, data in[1:0] ,write enb reg,clk, reset,valid out 0, valid out 1, valid out 2,
read enb 0,read enb_ 1, read enb 2, write enb, fifo_full, empty_ 0,empty_ 1,empty 2,
soft reset 0, soft reset 1, soft reset 2, full 0, full 1, full 2) ;
715
716 /*
717
718 module
register router (clk, reset, pkt valid, data in, fifo full, rst int reg, detect add, ld state, la
f_state, full_state, lfd_state, parity_done, low_pkt_valid, error, dout)
;
719 *

720
721 register router REGISTER (clk, reset,pkt valid, data in,fifo full, rst int reg,detect add,
ld_state, laf_state, full_state, lfd_state,parity_done, low_pkt_valid, error, data_out) ;

722
<br>

723 /*
724
725 module
fifo 1 6x9 router (clk, reset, data in, write enb, read enb, soft reset, lfd state, full, empty, dat
a out);
726 *7
727
728 fifo _16x9_router FIFO1 (clk, reset, data out, write _enb[0],read enb 0,soft _reset 0, lfd_state,
full 0,empty 0,data out 0) ;
729 fifo 16x9 router FIFO2 (clk, ; reset,data out,write enb [1],read enb 1,soft reset 1,lfd state,
full_1,empty_l,data out_1)
730 fifo_16x9_router FIFO3 (clk, reset,data out,write _enb[2],read_ enb 2,soft_reset 2,lfd_state,
full 2,empty 2, data out 2);
731
732
733 endmodule
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751 *** * * * * * * * *** ** *** * *** ** * * * * * *** * * ** * * ** *
* * * ** * * *** *** * *** *
** * *** *
752 //
753 INTERFACES
754
//***** t** t***
*

755 **** *** **/

756
757
758 // interface for source
759
760 interface router source if (input bit clk) ;

761
762
763 input and output declaration
764 input clk, reset, read enb 0, read enb 1, read enb 2, pkt valid;
765 input [7:0] data in;
766 Output [7:0] data out 0, data out 1, data out 2;
767 output valid out_0, valid_out_1, valid_out_2,error, busy;
768
769
770
771 logic [7:0]data_in;
772 bit reset;
773 bit pkt valid;
774 bit error;
775 bit busy;
776
777 1/ declaring the clocking block for source driver
778
779 clocking source drv@ (posedge clk) ;
780 default input#1 output#1;
781
782 output reset;
783 output pkt valid;
784 output data in;
785 input busy;
786 input error;
<br>

787
788 endclocking
789
790 7/ declaring the clocking block for source monitor
791
792 clocking source mon@ (posedge clk) ;
793 default input#1 output#1;
794
795 input reset;
796 input pkt valid;
797 input data in;
798 input busy;
799 input erro;
800
801 endclocking
802
803 77 modports for mon and drv
804
805 modport S MON (Clocking source mon) ;
806 modport S DRV (clocking source drv);
807
808 endinterface
809
810
811
812
813
814
815 7/ destination interface
R16
817 interface router destin if (input bit clk) ;

818
819 input and output declaration
820 input clk, reset, read enb 0,read enb l, read enb 2,pkt valid;
821 input [7:0] data in;
822 output [7:0] data out 0, data out 1, data out 2;
823 output valid out 0,valid_out_1, valid out 2,error, busy;
824
825
826 logic [7:0] data out;
827 bit read enb;
828 bit valid out;
829
830
831 // clocking block for destination driver
832
;
833 clocking destin drv@ (posedge clk)
834 default input#1 output#1;
835
836 output read enb;
837 input valid out;
838 input data out;
839
840 endclocking
841
842 77 clocking block for destination monitor
843
844 ;
clocking destin mon@ (posedge clk)
845 default input # output #1;
846
847 input data out,
848 input read enb;
849 input valid out;
850
851
852 endclocking
853
854 1/ modports for destin drv and mon
855
<br>

TB ARCHITECTURE:

virtuay
Seonia

.Scinan Sounte Ard top

DRive1 hSegunlen Sequeme
vivtua
tale
monito Routon

peshinadi n X3
Rat toe
D-inO
DRiver h(Sequenen

mo te KiAgontca
Sc0se

bood
D-n.
pRive

non t1

envinonnent
Test
D-in-2-/ Sequam torj

nontol
<br>

HAVA SNAOA

6:12

X 09/12/2024

ns
350
ns
378

to
ns
O

ns
300

ns
250

ns
801 200

179

J3921|
ns
150

091

Help
ns
100

Window

Bookmarks

151
ns IWave
50
Layout
AL1Columns

6conpare

Tools
00 00 00
Ins
Wave ColumnLayout
DUT
Msgs
ns Ons wave_fle1
wave_fie1:/top

370
Add 8h80 8h00 8hzz 8h00
Ih1 1h1 1h0 1h0 1h0 1h0 1ho 1h0 1ho Ih0 Ih0 thi 1h0 1h1 1h0 1ho Ih0
1h Ih
Simulate reset1
_0
:/top/DUT|read_erb_0

Now 1
wave_fie1:/topDUTread_enb_1

enb_2 2 out0 _1
1:(top,DUT/data_out_1

0 2 Cursor
reset
View)
DUT|pkt_vald
out
1:/top/DUT/(data_out

out l:topDUT/valid_out 1:top,DUT|empty_0 1:top/DUT/empty_1 1:top,DUT/empty_2

1:topDUTfreset
topDUTread
in
DUT(data
|data
DUT/valid 1:top/DUT/error 1:top,DUT|busy
wave_flel:top/DUTfu0
Wave_fle1:hop/DUT/_1 wave_file1:/top,DUT/fhl_2

DUT/dk vald l:top/DUT/soft

soft ATransaiptwave_lel

(WLF Compile
Wave_file1:/top/DUT

topDUT
DUT
10.7c
Simulate
top wave_fle1:/top wave_fle1:/top
1:/top 1:/top
wave_fie1:
Sim-64 View 1: wave_fle wave_fie
wave_fle1;
wave_file Wave_fle wave_file wave_fle wave_fle wave_file wave_fle wave_fle
-Defadt wave_fie wave_fie _file _file
wave wave
Questa Edit Layout Wave

File
I
<br>

856 modport D MON (clocking destin mon) ;

857 modport D_DRV (clocking destin _drv) :
858
859 endinterface
860
861
862
863
864
865
866
867 UVM TB COMPONENTS
868
869
870
871
872 7/ Top module uvm
873
874
875 module top);
876
uvm file
877 // including the
878
879 import uvm_pkg :: *:
880 71 include "uvm macros.svh"
881
882 1/ importing the th files
883
884 import router pkg :: *;
885
886
887 7/ generating clock
888
=
889 bit clk 1'b0;
= ~clk;
890 always #10 clk
891
892 1/ instantiating interace
893
894 router source if VIF (Clk) ;

895 router destin if VIFO (clk);

896 router destin if VIF1 (clk) :
897 router_destin_if VIF2 (clk) ;
898
899
900
901 /| instantiating DUT
902 // top nodule
903 1/module
route top (clk, reset, read enb 0, read enb 1,read enb 2, data in, pkt valid, data out 0, data o
ut_1,data_out_2, valid _out_0,valid_out_1, valid_out_2,error, busy) ;
904
905
906 router top DUT (

907 .clk (clk),

908 .reset (VIF.reset), .
909 .read enb (VIF0 read enb),
0
,
910 .read enb 1(VIF1. read enb)
911 .read enb 2 (VIF2. read enb),
912 .data_in (VIF. data_in),
913 -pkt valid (vIF.pkt valid)
. .
914 data out 0(VIF0 . data out),
915 .data out 1(VIF1 data out),
916 .data out 2 (vIF2. . data out),
.
917 valid out 0 (VIF0 valid out),
918 .valid out (VIFl.valid 1
out),
919 .valid out 2 (VIF2.valid
,
out),
920 .error (VIF. error)
921 .busy (VIF. busy)
922
<br>

923
924
925
926 initial begin
927
928 ifdef VCS
929 $fsdbDumpvars (0,top):
930 endif
931
932 // setting the virtual interface for source agent and 3 destination agents
,
933 uvm confiq db # (virtual router source if) set (null, "*" "vif",VIF) ;
934 uvm config db # (virtual router destin if) set (null, "*","vif0",VIFO)
;

935 uvm config db # (virtual router destin if) :: set (null,"* ", "vifl" ,VIF1) ;
936 uvm config db # (virtual router destin if) :: set (null, "*", "vif2" , VIF2) ;
937 1/ calling the runtest ()
938
939 run test () ;

940 end
941
942
943 endmodule
944
945
946
947 7
class for destinationj agetn configratoion data base object
948
949
950 class destin_agent config extends uvn object;
951
952
953 / factory reqistration
954
955 uvm object _utils (destin agent config)
956
957 // declare the varible required
958
959 uvm active passive enum is active = UVM ACTIVE;
960 7/ declare the virtual inteface handle
961
962 virtual router destin if vif;
963
964
965 // fucntion new construction
966
967 function new (string name = "destin agent config") ;

968
969 super. new (name),
970
971 endfunction
972
973
974
975 endclass
976
977
978
979 // source agent config
980
981 class source_agent_config extends uvm object;
982
983
984 7/ factory registration
985
uvm object (source_agent
986 utils config)
987
988
989 uvm active passive enum is active = UVM ACTIVE;
990
991
<br>

992 /7 declare virtual interfae handle

993
994 virtual router sOurce if vif;
995
996 17 function new constructor
997
998
999 function new (string name = "source agent config" );
1000
;
1001 Super.new (name)
1002
1003 endfunction
1004
1005
1006
1007
1008
1009 endclass
1010
1011
1012
1013
1014
1015 //dest ination driver class
1016
1017 class destin driver extends uvm driver # (destin xtn) ;

1018
1019 7/ factory registration
1020
1021 uvm component utils (destin driver)
1022
1023 7/ declare the virtual interface handle
1024
1025 agent m
destin config cfg;
1026
1027 virtual router destin if.D DRV vif;
1028
1029 7/ funcion new constructor
1030
1031 , uvm
1032 function new (string name = "destin driver" component parent = null );
1033
1034
1035 super. new (name, parent) ;

1036
1037 endfunction
1038
1039 1/ build phase
1040
;
1041 function void build phase (uvm phase phase)
1042
;
1043 super.build phase (phase)
1044 // `uvm
info full(get name (),
"this is driver destin", UVM , NONE)
1045 if (!uvm config db #(destin agent config) :: get (this, "n
"destin agent config" ,m cfg) )
1046 uvm fatal (get full name (), "cannot get the destin agetn config
handle driver m_cfg from desti agetn top")
1047
1048 endfunction
1049 // connect phase connect the virtual interface to local interface
1050
1051 function void connect phase (uvm phase phase) ;
1052
= m_
1053 vif cfg.vif;
1054
1055 endfunction
l056
1057
1058 1/ task run phase here we send req and and then data req sended to new method for
<br>

driving
1059
1060 task run phase (uvm phase phase) ;

1061
1062 forever
1063 begin
1064 super. run phase (phase) ;

1065
1066 seq item port.get next item (req) ;
1067
1068
1069 send to dut ; ():
1070 req.print ()
1071
1072 seq_ item port.item_done () :

1073
1074 end
1075 endtask
1076
1077
1078 // task send to dut
1079
1080 task send to dut (0;
1081
1082 while (vif.destin drv.valid out !== 1'bl)
1083 begin
1084
@
(vif.destin drv) ;

1085 end
1086
1087 repeat (req. delay)
1088 begin
@
1089 (vif.destin drv);
1090 end
1091 Vif.destin drv.read enb <= 1'bl;
1092
1093 .
1094 while (vif destin drv. valid out !== 1'b0)
1095 begin
1096 @
(vif.destin drv) ;
1097 end
1098
1099
@
vif.destin drv.read enb <= 1'b0;
1100 (vif. destin drv);
1101
1102
1103 endtask
1104
1105
1106
1107
1108 endclass
1109
1110
1111
1112 1/ destination monitor class
1113
1114 class destin monitor extends uvm monitor;
1115
1116 7/ factory registration
1117
1118 `uvm component utils (destin monitor)
1119
7
1120 declare virtual interface handle
1121
1122 agent m
destin config cfg;
1123 virtual router destin if.D MON
vif;
1124 7/ declaring the destin transaction
1125
1126 destin xtn dmon;
<br>

1127
1128 / tlm port for write to score board
1129
1130 uvm_analysis_ port #
(destin _xtn) dmon port;
1131
1132 1
funct.ion new constructor
1133
1134
1135 function new (string name "destin monitor uvm component parent = null );
1136
1137 super. new (name, parent) ;
dmon port = new ("dmon
;
1138 port", this)
1139
1140 endfunction
1141
1142 / build phase
1143 function void build phase (uvm phase phase) ;
1144
1145 super. build phase (phase):
1146 //uvm info (get full name(),"this is monitor destin", UVM NONE)
1147 if (!uvn config db # (destin agent config) :: get (this,"",
"destin agent config" ,m cfg))
1148 uvm fatal (get full name (),"cannot get the destin agetn config
cfg from desti agetn top")
m
handle monitor
1149
1150 endfunction
1151
1152 1/ connect phase connecting the virtual interfcce to local interface handle
1153
;
1154 function void connect phase (uvm phase phase)
1155
1156 vif = m cfg.vif;
1157
1158 endfunction
1159
1160 // run phase
1161
1162
1163 task run phase (uvm phase phase) ;
1164
1165 forever
1166 begin
1167
1168 collect data(0:
1169 dmon.print ();
1170 dmon port.write (dmon);
1171 end
1172
1173 endtask
1174
1175 7/ collect the data from interface
1176
1177 task collect data ();
1178
1179 dmon = destin xtn :: type id :: create (" dmon");
1180
1181 while( vif.destin mon.read enb !== 1'bl)
1182 begin
1183 @(vif. destin mon) :
1184 end
1185
@
(vif.destin mon);
1186 dmon.header byte = vif.destin mon.data out;
1187
1188 @
(vif. destin mon) ;
1189 dmon.payload = new [dmon.header byte[7:21]:
1190 foreach (dmon.payload[i])
1191 begin
1192 while ( vif.destin mon.valid out !== 1'bl)
1193 begin
<br>

1194 @
(vif. destin mon);
1195 end
1196 dmon.payload[i] = vif.destin mon.data out;
;
1197 @
(vif.destin mon)
1198
1199 end
1200 dmon.parity byte = vif.destin mon.data out;
1201
@
(vif. destin mon) ;
1202
1203 endtask
1204
1205
1206 endclass
1207
1208
1209 // destin seq class
1210
1211 class destin seq extends uvm sequence #(destin xtn) ;

1212
1213 // factory registation
1214
1215 uvm object utils (destin seg)
1216
1217 1/ function new constructor
1218
1219 function new (string name = "destin seq") ;
1220
1221 Super. new (name) ;

L22
1223 endfunction
1224 //build phase
1225
1226
1227
1228 1/ task body for ganerate stimulus
1229
;
1230 task body ()
1231 req = destin xtn:: type id ::
create ("req");
1232 start item (req) ;
1233
12 34
1235 assert(req.randomize () with {
(req.delay >0) && (reg.delay < 30) :})
1236 else
1237 begin
1238 uvm fatal (get full name ()," randomization not happend in
destinaion Seguence check it")
1239 end
1240 finish_item (req) ;
1241
1242 endtask
1243
1244
1245
1246 endclss
1247
1248
1249 1/destination sequencer class
1250
1251 class destin_seqr extends uvm sequencer #(destin_xtn) ;
125
1253 1/ factory registration
1254
1255 uvm component_utils (destin_seqr)
1256
1257 // fuinction new Constructor
1258
1259 function new (string name="destin seqr" uvm component parent= null) ;
1260
1261 super. new (name,parent);
<br>

1262
1263
1264 endfunction
1265
1266 // build phase
1267
1268 /* (uvm phase phase) ;
function void build phase
1269
1270 super.build phase (phase) ;
1271
1272 endfunction
1273 */
1274
1275 endclass
1276
1277
1278
1279 7/ class deriver for source
1280
1281 class source driver extends uvm driver #(source xtn);
1282
1283
1284 / factory registration
1285
1286 uvm component utils (source driver)
1287
1288
1289 1/ declare the virtual interface
1290
1291 virtual router source if.S DRV vif;
1292 source agent config m cfg;
1293
1294 1/ function new constructor
1295
1296 function new (string name = "source driver" uvm component parent = null) ;
1297
1298
1299 super.new (name,parent) ;

1300
1301
1302 endfunction: new
1303
1304 71 build phase
1305
1306 function void build phase (uvm phase phase);
1307
1308 super. build phase (phase) ;

1309 //`uvm info (get full name (), "this is driver soruce", UVM NONE)
1310 if uvm
(! config_db #(source_agent config) :: get (this, "" ,
"source agent config" ,m cfg))
1311 uvm fatal (get full name (),"cannot get the source agent config
handle driver m cfg from source agent top")
1312
1313 endfunction
1314
1315 7/ connect phase
1316
1317 function void connect phase (uvm phase phase);
1318
1319 vif = m cfg.vif;
1320
1321 endfunction
1322
1323 7
task run phase and send to dut method calling
1324
1325 task run phase (uvm phase phase) ;
1326 super. run phase (phase) ;
@
1327 (vif. source_drv);
1328 vif.source drv.reset <= 1'b0;
<br>

1329
@
(vif.source drv);
1330 vif.source drv.reset <= 1'bl;
1331
1332
1333 forever begin
1334
1335 seq item port.get next item (reg) :

1336
1337 ;
send to dut (req)
1338 seq item port.item done () ;
1339 req.print ();
1340 end
1341 endtask
1342
1343 1/ send to dut
1344
:
1345 task send to dut (source xtn req)
1346
1347 while (vif.source drv.busy != 1'b0)
1348 begin
1349 @
(vif.source drv) i
1350 end
1351 vif.source drv.pkt valid <= 1'bl;
1352 vif.source drv.data in <= req.header_byte;
@ ;
1353 (vif. source_drv)
1354 foreach (req.payload [i])
1355 begin
1356 while (vif. source drv.busy != 1'b0)
1357 begin
1358
@
(vif.Source drv);
1359 end
1360 vif.source drv.data in <= reg.payload[i];
1361 @
(vif. source_drv) ;
1362 end
1363
1364 vif.source drv.pkt valid <= 1
'b0;
1365 vif.source drv.data_in <= req.parity byte;
1366 repeat(2)
1367
@
(vif. source drv);
1368 endtask
1369
1370
1371
1372
1373 endclass
1374
1375
1376
1377 // class source monitor
1378
1379 class Source monitor extends uvm monitor;
1380
1381 1/ factory registration
1382
1383 uvm component utils (source monitor)
1384
1385 1/ dfeclare virtual interface
1386
MON
1387 virtual router_source_if.s vif;
1388 source_ agent config m cfg;
1389 SOurce xtn smon;
1390
1391 7/ declaring the anlysis port
1392
1393 uvm analysis port # (source xtn) smon port;
1394
1395
1396 1/ function new constructor
1397
<br>

1398 function new (string name "source monitor", uvm component parent = null );
1399
1400 super.new (name,parent);
1401 smon port = new ("smon port",this) ;
1402
1403 endfunction
1404
1405 1/ build phase
1406
1407 function void build phase (uvm phase phase);
1408
1409 ;
super.build phase (phase)
1410 //uVm info (get name (), "this is monior
full soruce", UVM NONE )
1411 if(!uVm config db #(source agent config) :: get (this, "",
"source agent config" ,m cfg))
1412 uvm fatal (get full name (),"cannot get the sOurce agent config
handle monitor m cfg from soure agent top")
1413
1414
1415 endfunction
1416
1417 11 connect phase
1418
1419 function void connect phase (uvm phase phase) ;
1420
1421 vif = m cfg.vif;
1422
1423 endfunction
1424
1425 / run phase
1426
1427 task run phase (uvm phase phase):
1428
1429 forever
1430 begin
1431
;
1432 Super.run phase (phase)
1433 collect data () ;
1434 Smon.print ():
1435 Smon port.rite (smon) ;

1436
1437 end
1438 endtask
1439
1440 7/ collect task for from interace to monnitor
1441
1442 task collect data );
1443 smon = source xtn :: type id :: create ("sIMon");
1444 while (vif.source mon.busy != 1'b0)
1445 @
(vif. source mon) ;
1446 while (vif.source mon.pkt valid != 1
'bl)
1447 (vif.source
C
mon);
= mon.
1448 smon.header byte vif.source data in;
1449 @
(vif. source mon) ;
1450 smon.pàyload = new [smon.header byte [7:21]:
1451 foreach (smon.payload[i])
1452 begin
1453 while (vif.source mon.busy != 1'b0)
1454 begin
1455 @
(vif.source mon) i

1456 end
1457 smon.payload [i] = vif.source mon.data in;
1458 @
(vif. source_mon) ;
1459 end
1460 smon.parity byte = vif.sOurce mon.data in;
1461
1462 @
(vif.SOurce mon)
;

1463 @
(vif.source mon) ;

1464 SmOn.error = Vif.source mon.error;

<br>

= 0b",smon.error) ;
1465 $display ("Signal Error From Source Monitor
1466
1467 endtask
1468
1469
1470 endclass
1471
1472
1473 7
source sequence class
1474
1475 class Source seq extends uvm sequence #
(source xtn);
1476
1477 1/ factory registration
1478
1479 uvm_object_utils (source_seq)
1480
1481 1/ addres declaration
1482
1483 bit [1:0] addr;
1484
1485 1/ function new constructor
1486
1487 function new (string name = "source seq") ;

1488
1489 super.new (name) ;

1490 /uvm info (get full name (), "

this is sequence soruce", UVM NONE)
1491
1492 endfunction
1493
1494 endclass
1495
1496 Extended class Small packets --//
1497
1498 ClasS Sma1l seq extends SOurce seg;
1499
1500 7/ factory registration
1501
1502 uvm object utils (small seq)
1503
1504 / function new constructor
1505
1506 function new (string name = "small seq");
1507
1508 super. new (name) ;
1509
1510 endfunction
1511
1512 1/ body task =generate 1 to 20 packets payload generates
1513
1514 task body () ;
1515 if (!uvIn config db # (bit[2] )::get (null, get full name (), "bit",addr) )

1516 uvm fatal (get full name (),"cannot get the address from test class are
set it check")
1517
1518 req = source_xtn :: type_id :: create ("req") ;
1519 start item (reg);
1520 assert (reg.randomize () with {req. header byte [l:0] == addr;req.header byte[7:2]
inside{[l:21]};} )
1521 else
1522 begin
1523 uvm info (get full name (), "!!!!!!!!!!!randomization is failed in
source seqs at small seq!!! !!!!!!" , UVM LOW)
1524 end
1525
1526
1527 finishitem(req):
1528
1529 endtask
1530
<br>

1531 endclass
1532
1533
1534 Extended clas of Medium packets
1535
1536
1537 class medium seq extends source seq;
1538
1539 1/ factory registration
1540 `uvm object utils (medium seg)
1541
1542 7/ function new constructor
1543
1544 function new (string name = "medium seq") ;
1545
1546 super. new (name)
1547
1548 endfunction
1549
1550 1/ task body for packets stimulus 22 to 41
1551
1552 task body () ;
1553 if (!uvm config db # (bit[2]):get (null,get full name (), "bit", addr) )

1554 uvm fatal (get full name (), "cannot get the address from test class are
set it check")
1555
1556 req = Source xtn :: type id:: create (req") :
1557 start item (req) ;
assert (req.randomize () with {req.header byte[7:2] {[22 : 41] ;
=inside
1558
1559 reg.header byte [l:0] addr; ) )
1560 else
1561 begin
1562 uvm info (get full name (),"!!!!!!!! randomization is failed in
source segs at medium seq!!!!!!!!!!!",UVM LOW)
1563 end
;
1564 finish_item (req)
1565
1566 endtask
1567
1568 endclass
1569
1570
1571 7
large sequnce for generating the from 42 to 63
1572
1573 class large seg extends source seg;
1574
1575 71 factory registration
1576
uvm object seq)
1577 utils (large
1578
1579 7
function new constructor
1580
1581 function new (string name = "large seq" );
1582
1583 super. new (name);
1584
1585 endfunction
1586 1/ task body for 42 to 63
1587
1588
1589 task body () ;
name (), ,
1590 if(!uvm config db #
(bit[2])::get (null, get full "bit" addr) )
1591 uvm fatal (get full name (),"cannot get the address from test class are
set it check")
1592
1593 req =
Source xtn:: type id:: create (" req") ;
;
1594 start item (reg)
assert(req.randomize() with {reg.header byte[7:2] {[42 : 63]};
=inside
1595
1596 req.header byte [1:0] addr; } )
<br>

1597 else
1598 begin
1599 uvm info (get full name (),"!!!!!!!!randomization is failed in
source segs at medium se!!!!!!!!!!!", UVM LOW)
1600 end
;
1601 finish item (reg)
1602 endtask
l603
1604 endclass
l605
l606
607
l608 /source sequnce class
1609
1610 class source_seqr extends uvn_sequencer #(source_xtn) :
l611
1612
1613 // factory registration
1614
1615 uvm_component _utils (source_seqr)
1616
1617
1618 1/ fcuntion new constructor
1619
1620
1621 function new (string name ="source seqr", uvm component parent = null) ;

1622
1623 super.new (name, parent) ;

1624
1625
1626 endfunction:new
1627
l628
1629
1630
1631
l632 endclass
1633
1634
1635 /| virtual sequnce class
1636
1637 class virtual seq extends uvm sequence # (uvm sequence item) ;

L638
1639 11 factory registration
1640
1641 uvm object_utils (virtual_seq)
1642
1643 // declaring the handle for sequnces
1644
1645 small seg S_Segi
1646 medium seg m seg;
1647 large seg 1_seq;
1648
l649 7/ declaring the handle for virtual sequncer
1650
1651 Virtual seqr V Seqr;
1652
1653 11 declare dynamic handle for physical seqr
1654
1655 source seqr ps seqr [];
1656
1657 1/ declaring the hande for env config to getting
l658
1659 router env config m
cfg;
1660
1661 / function new constructor
1662
1663 function new (string name = "virtual seg") ;

1664
<br>

;
1665 Super.new (name)
l666
1667 endfunction: new
1668
1669 7 task body for assqing the v sequncer to m sequncer and assingn the these handle to
env config class
1670
:
1671 task body ()
1672
1673 if (! uvm config db #(router
env config" ,m cfg)
env config) :: get (null, get full name
),"router )
uvm_ (get_ full_name (), "canot get
l674 fatal the
router env config handle m cdfg from test in
virtual sequence")
1675
1676
1677 ps_seqr = new [m cfg.no of_source] ;
1678
1679 1/ assiging the m sequncer to physical virtual sequncer through $cast
1680
1681 assert($cast (v_seqr,n_sequencer))
1682 else
l683 begin
1684 uvm error (get_ full_name (),"error becuase of
cast not working in the virtual sequence check
that")
1685 end
1686 foreach (ps_seqr [i])
1687 begin
1688 ps seqr [i] = v seqr.s seqr [i] ;
1689 end
1690
l691 endtask:body
1692
1693 endclass
1694
l695
1696 77 Extended class from virtual_ seq to small seq sequnce clàss
1697
1698 class virtual small seg extends virtual seq;
1699
1700
1701 7/ factory registration
1702
1703 uvm object utils (virtual small seg)
1704
1705 7
function new constructor
1706
1707 function new ( string name "virtual small seq");
1708
1709 super. new (name) ;

1710
1711 endfunction
1712
1713
1714 7/ task body
1715
1716 task body () :
1717
1718 s seq = small seq :: type id:: create ("s seq");
1719 super.body ():
1720 of source ; it+)
m

for (int i=0; i< cfg.no

1721 begin
1722
1723 s seq.start(ps seqr [i]) ;
1724
1725 end
1726
1727 endtask
<br>

1728
1729
1730 endclass
1731
1732
1733 1 Extended class for medium seq
1734
1735 class virtual medium seq extends virtual seq;
1736
1737 // factory registration
1738
1739 uvm object utils (virtual medium seq)
1740
1741 // function new constructor
1742
1743 function new (string name ="virtual medium seq" )
1744
1745 super. new (name) ;
1746
1747 endfunction
1748 task body
1749
1750 task body () ;
1751
1752
m seq
super.body ();
=
medium seq :: type id :: create ("m seq");

1753 for (int i=0; i<m cfg.no of source ; itt)

1754 begin
1755
1756 m_seq.start (ps_seqr [i]);
1757
1758 end.
1759 endtask
1760
1761 endclass
1762
1763
1764 1/ Extended class for large seq
1765
1766 class virtual large seq extends virtual seq;
1767
1768 // factory registration
1769
1770 uvn object utils (virtual large seq)
1771
1772 7/ function new constructor
1773
function new (string name ;
1774 ="virtual large seq")
1775
1776 super. new (name) ;

1777
1778 endfunction
1779
1780
1781 task body
1782
1783
1784 task body () ;
1785 1 seq = large seq :: type id :: create ("1 seq") ;

1786 super. body ();

1787 for (int i=0; i< m cfg.no of source ; i++)
1788 begin
1789
1790 1_seq.start (ps_seqr[i]):
1791
1792 end
1793 endtask
1794
1795 endclass
1796
<br>

1797
1798 1/ virtual sequncer class
1799
1800 class virtual seqr extends uvm sequencer #(uvm sequence item) ;
L801
1802 1/ factory registration
1803
uvm component
1804 utils (virtual_seqr)
1805
1806
1807 /1 declaring the handle for source and destination sequencer
l808 router env config m cfg;
1809 source seqr s seqr [];
1810
1811
1812 // fuunction new construction
1813
new (string name= , uvm = null);
1814 function virtual seqr" component parent
1815
1816 Super.new (name, parent) ;
1817
1818 endfunction
1819
1820 1/ build phase
1821
;
1822 function void build phase (uvn phase phase)
1823
;
1824 super.build phase (phase)
1825 if (!uvm_config_db #(router_env_config) :: get (this, "",
"router env config" ,m cfg) )
1826 uvm fatal (get full name () ," cannot get the router env config
handle mcfg from tesdt class in virtual sequncerr")
1827
1828 s
seqr = new [m cfg.no of_source];
1829 endfunction
1830
1831
1832
1833
1834 endclass:virtual seqr
1835
1836
1837
1838
1839
1840 class tb scoreboard extends uvm scoreboard;
1841
1842
1843 1/ factory registration
844
1845 uvm component utils (tb_scoreboard)
1846
1847 1/ declaring the handle for env confiq
1848
1849 router_env_config m_cfg;
1850
1851 7/ declaring the handle for tlm ports
1852
1853 uvm
uvm
tlm analysis fifo #(source xtn) source fifo []: ;
1854 tlm analysis fifo #(destin xtn) destin fifo []
1855
1856 // declaring the source and destination transaction class
1857
1858 SOurce xtn s xtn;
1859 Source xtn source cov xtn;
1860
1861 destin xtn d xtn;
1862 destin_xtn destin_cov_xtn;
1863
<br>

1864
1865 1/ write fucntion covrage cover group
1866
1867 cOvergroup source cg;
1868
1869 ADDER :
coverpoint s_xtn.header_byte[l:01{
1870
1871 bins b1 = {2'b00) ;
= {2 'b01}:
1872 bins b2
1873 bins b3 = {2'bl0) ;

1874
1875
s
1876 DATA IN: coverpoint xtn.header byte[7:21{
1877
= {[1:21] } ;
1878 bins bl = ([22 : 41]}:
1879 bins b2
1880 bins b3 = ([42:63]}:
1881
1882
1883 ERROR: cOverpoint s xtn.error {

1884
1885 bins bl = {
1'bl );
1886 bins b2 = {
1'b0 );
1887
1888
1889
1890 |* BUSY: coverpoint s xtn.busy {

1891
1892 = {
}:
bins bl 1'bl
1893 =
bins b2 {
1'b0

1894
1895 }*/
1896
1897 // CROSS ALL: cross
ADDER, DATA IN, ERROR, BUSY;
1898
1899 endgroup
1900
1901 covergroup destin cg;
1902
1903 VALID_OUT: coverpoint d_xtn.valid _out{
L904
= {1'bl} ;
1905 bins bl = {1 'b0};
1906 bins b2
1907
1908
1909 DATA OUT: coverpoint d xtn.header byte[7:2]{
1910
1911 bins bl = {[l:21]}:
1912 bins b2 = {22 : 41]}:
1913 bins b3 = {[42:63]}:
1914
1915

1916
1917 endgroup
1918
1919
1920 / we have to implement check method for comparing the data
1921
1922
1923 / function new constructor
<br>

1924
, uvm
1925 function new (string name= "tb scoreboard" component parent= null );
1926
1927 super.new (name, parent) ;
1928 source cg = new ();
1929 destin cg = new () ;

1930
1931 endfunction: new
1932
1933
1934 // build phase
1935
;
1936 function void build phase (uvm phase phase)
1937
1938 super.build phase (phase):
1939
1940 if (!uvm config db # (router env config) :: get (this, "" ,
"router env config" ,m cfg) )
1941 begin
1942 uvm fatal (get full name (), "cannot get he router env config
handle m cq in scoreboard ")
1943 end
1944
1945
1946 source fifo = new [m cfg.no of source] ;
1947
1948 foreach (source fifo [i])
1949 begin
1950 source_fifo [i] = new ("source_fifo", this) ;
L951 end
1952
1953 destin fifo = new [m cfg.no of destin];
1954
1955 foreach (destin fifo[i])
1956 begin
= new , ;
L957 destin fifo [i] (Ssformatf (" destin fifo [$0d] " ,i) this)
1958 end
1959 endfunction
1960
1961
1962 task run phase (uvm phase phase) ;

1963 super. run phase (phase) ;

1964 forever
1965 begin
1966 fork
1967 begin
L968
1969 source fifo[O].get (s xtn);
1970 source cg.sample () ;

1971
1972 end
1973 fork
1974 begin
1975
1976 destin_fifo[0] .get (d_xtn);
1977 destin cg.sample () ;
1978
1979 end
1980 begin
1981
1982 destin fifo [1].get (d_xtn);
1983 destin cg.sample ();
1984
1985 end
1986 begin
1987
1988 .get (d xtn) ;
destin fifo[2]
1989 destin_cg.sample () :
1990
<br>

1991 end
1992 join any
1993 disable fork;
1994 join
995 compare (s_xtn,d xtn) ;
1996 $display (

\n====
======\n");
1997 $display ("\n source side functional coverage =
i.3f \n" ,source cg.
get_ coverage );
,
1998 display ("\n destin side functional coverage =
.3f \n" destin cg.
get coverage) :
(
1999 display
n====
=====\n");
2000 end
2001
2002 endtask:run phase
2003
2004
2005 1/task for comparing the source and destination packets
2006
2007 task compare (source xtn s_xtn,destin xtn d
xtn) ;
2008
2009 bit check;
2010
2011 if (s xtn.header byte == d xtn. header byte)
2012 begin
2013 display ("\n=: == Header Byte Matched
SuccessFull =====================\n ");
2014 check = 1'bl;
2015 end
2016 else
2017 begin
$display ("\n===: ==
2018 Header Byte Not Matched
=====================\n");
2019 check = 1'b0;
2020 end
2021
=
2022 if(s xtn.payload d xtn.payload)
2023 begin
2024 $display ("\n===== === Payload Matched SuccessFull
==========E========== "),

2025 check = 1'bl;

2026 end
2027 else
2028 begin
2029 $display ("\n= === Payload Not Matched
\n");
2030 check = 1'b0
2031 end
2032 if (s_xtn.parity byte = d
xtn.parity byte)
2033 begin
2034 $display ("\n======= ========== Parity Byte Matched
SuccessFull \n");
2035 check = 1'bl;
2036 end
2037 else
2038 begin
2039 $display ("\n= Parity Byte Not Matched
=====================\n "):
2040 check = 1'b0:
2041 end
2042
=
2043 if (check 1'b1)
2044 begin
2045
2046 $display (

\n======================== ===E==============
<br>

==========\n");
2047 $display ("\n SUCCESSFULLY MATCHED \n");
2048 $display (
n==========
==========\n");
2049
2050 end
2051 else
2052 begin
2053
2054 $display (

===E====: \n");
2055 $display (" \n PACKETS NOT MATCHED \n");
2056 display (

========\n"):
2057 end
2058
2059
2060
2061 endtask
2062
2063
2064
2065
2066 endclass:t scoreboard
2067
2068
2069
2070
2071 // environment class
2072
2073 class tb env extends uvm env;
2074
2075 7/ factory registration
2076
uvm component env)
2077 utils (tb
2078
2079 1/ declaring the handle for vritual segr and source agent top and destin agent top i
dont know
2080
2081 source agent top source agth;
2082 destin agent top destin agth;
2083 tb scoreboard sb;
2084
2085
2086 7/ declaring the int varialbles for no of wr agent and no of read agent - idont know
2087
2088
2089 // declaring for the scoreboard and virtual sequencer no i dont know
2090
2091 virtual seqr v seqr;
2092
2093 7/ declaring the handle for the env_config class to get and
2094
2095 router_env_config m_cfgi
2096
2097 / construction new function
2098
2099 function new (string name = "tb env", uvm component parent = null):
2100
2101 super. new (name,parent) ;
2102
2103 endfunction:new
2104
2105 // build phase
2106
2107 function void build phase (uvm phase phase) ;
<br>

2108 super.build phase (phase) :

2109 if(! uvm config db # (router env config) :: get (this, "","router env config"
)
,m_cfg)
2110 uvm fatal (get full name (), "cannot get the router env config handle
Im cfg from test in env tb ")
2111 source agth = source agent top :: type id :: create ("source agth" ,this) ;
,
2112 destin agth == destin agent top :: type id :: create (" destin agth" this);
2113 sb tb scoreboard type id :: create ("sb", this);
2114 V_seqI
= virtual seqr ::type id :: create ("v seqr", this) ;

2115
2116 endfunction
2117
2118
2119 / connect phase
2120
;
2121 function void connect phase (uvm phase phase)
2122
2123 foreach (v_seqr.s_seqr [il)
2124 begin .
2125 v_seqr.s_seqr [i] = source _agth.agth [i] seqr;
2126 end
2127
2128 for (int j = 0; j< m_cfg.no _of_source;j++)
2129 begin
2130 source agth. agth[j].monh.smon port.connect (sb.source fifo[i].
:
analysis_export)
2131 end
2132
2133 for (int i = 0; i < m_cfg.no_of_destin ;
it+)
2134 begin
.
2135 destin agth. agth [i].monh. dmon port.connect (sb. destin fifo [i]
analysis export);
2136 end
2137
2138 endfunction: connect phase
2139
2140
2141
2142 endclass:tb env
2143
2144
2145
2146
2147
2148 7/ test class
2149
2150 class base test extends uvm test;
2151
2152 1/ factory registration
2153
2154 uvm component utils (base test)
2155
2156 7/ declaring the test bench env class handle and env config handles
2157
2158 tb env envh ;
2159 router env Config m cfg;
2160
2161 SOurce agent config m_source_agth [1:
2162 destin_agent_config m_destin_agth [] :
2163
2164 int no of source =
2165 int no of destin =
2166
7
2167 header byte destination address setting
2168
2169 bit [2] addr;
2170
2171 1/ funciton new constructor
2172
<br>

2173 function new (string name = "base test",uvm component parent = nul1 );
2174
2175 Super.new (name, parent);
2176
2177 endfunction
2178 1/ config function
2179
2180 function void config_data () ;
2181
2182 m_source_agth = new [no of source] ;
m = new [no
2183 destin agth of destin]:
2184
2185 foreach (m source agth [i])
2186 begin
2187 m_source agth [i] = source_agent config:: type id
::source
create ($s formatf source agth[%0d]", i));
("m
2188 m
agth [i].is active = UVM ACTIVE;
2189 if (!uvm config db ,m#(virtual router source if) ::
get (this, "", "vif" source agth [i].vif) )

2190 uvm fatal (get full name (),"cannot get the

interface handle from source are set in top"

2191
2192 end
2193 foreach (m destin agth [i])
2194 begin
2195 m
destin agth [i] = destin agent config :: type id
:: create ($sformat.f ("m destin agth (%0d] ",i) );
m = UVM ACTIVE;
2196 destin agth [i]. is active
2197 if (! uvm config db # (virtual router,m destin if) ::
get (this, "", $sformatf ("vifi0d" ,i) destin agth [i
J.vif) )
2198 uvm fatal (get full name (),"cannot get the
interface handle from destination are set
in top")
2199
2200 end
2201 Im cfg.no of source = no of source;
of destin = no of_destin;
m
2202 cfg.no
2203
2204
2205 endfunction
2206
2207 // fucniton build phase
2208
2209
2210 function void build phase (uvm phase phase) ;
2211
2212 super.build phase (phase) ;
2213 m_cfg = router_env_config :: type_id :: create("m_cfg") ;

2214
2215 m cfg.M sour ce agth = new [no of source] ;
2216 m cfg.In destin agth = new [no of destin];
2217
2218 config_data ()
2219
2220 foreach (m source agth [i] )
=
2221 m cfg.m source agth [i] m source agth [i];
2222
2223 foreach (m destin
m
agth [i]) m
= m :
2224 cfg. destin agth [i] destin agth [il
2225
2226 uvm config db #(router env config) :: set (this, "*", "router env config"
m
cfg);
2227 envh= tb env :: type id:: create ("envh", this) ;
2228
2229
2230 endfunction: build phase
2231
<br>

2232 // function void end o elaboration

2233
;
2234 function void end of elaboration phase (uvm phase phase)
2235
2236
2237 :
uvm_top.print_topology ()
2238
2239
2240
2241 endfunction
2242
2243
2244
2245 endclass
2246
2247 7/-- --Extended base test class to small test class -//
2248
2249 class small seq test extends base test;
2250
2251 7
factory regisdtration
2252
2253 uvm component utils (small seq test)
2254
2255 7/ declaring the virtual smal seg class handle
2256
2257 /small seq seqh;
2258 virtual small seg s seqh;
2259 destin_seg dseg:
2260 1/ function new constructor
2261
2262 function new (string name = "small seq test",uvm component parent);
2263
2264 super. new (nane,parent) ;

2265 addr = 2'd0:

2266
uvm config # , ;
2267 db (bit[2])::set (this, "*", "bit" addr)
2268
2269 endfunction
2270
2271 1/ build phase
2272
2273 function void build phase (uvm phase phase) ;
2274
2275 super.build_phase (phase) ;
2276
2277 endfunction
2278
2279 11 run phase of small test seq
2280
2281 // task run phase
2282
2283 task run phase (uvm phase phase);
2284 phase. ;
raise objection (this)
2285 super. run phase (phase) ;

2286 s_seqh = virtual_small_seq :: type_id :: create ("s_ segh") ;

2287 dseq = destin eq :: type id :: create ("dseq");

2288 repeat (5)
2289 begin
2290 fork
2291 s seqh.start (envh.v seqr);
;
2292 dseq.start (envh.destin agth. agth [addr]. seqr)
2293 join
2294 end
2295 phase. drop objection (this);
2296
2297 endtask
2298
2299 endclass
2300
<br>

2301 --Extended base test class to medium tet class

2302
2303 Class medium seq test extends base test;
2304
2305 7/ factory registration
2306
2307 uvm _component_utils (medium_seq_test)
2308
2309
2310 // declaring the handle for medum sdeq generater
2311
2312 /7 medium seq seqh;
2313
2314 virtual medium seq m seqh;
2315 destin_seq dseq;
2316
2317
2318 1/ build phase
2319
2320 phase (uvm phase phase) ;
function void build
2321
2322 super.build phase (phase);
2323
2324 endfunction
2325
2326 1/ function new constructor
2327
2328 function new (string name = "medium seq test", uvm component parent );
2329
2330 super.new (name,parent):
=
2331 addr 2'dl;
2332
2333 uvm config db #
(bit[2])::set (this, "
*", "bit",addr):
2334
2335
2336 endfunction
2337
2338 1/ run phase of medium test seq
2339
2340
2341 task run phase (uvm phase phase);
2342 phase. raise objection (this);
2343 super.run phase (phase) ;
2344 m seqh =
virtual medium seg :: type id :: create ("m seqh");
2345 dseg = destin seq :: type id :: create ("dseg"):
2346 repeat(5)
2347 begin
2348 fork
m
2349 segh.start (envh.v seqr);
2350 dseq.start (envh.destin_agth.agth [addr] .seqr):
2351 join
2352 end
2353 phase.drop objection (this) ;

2354 endtask
2355
2356 endclass
2357
2358
2359 Extended base test class to Large test class
2360
2361 class large seg test extends base test;
2362
2363 // factory registration
2364
2365 uvm component utils (large seq test)
2366
2367 7/ declare the handle of large seq
2368
2369 //large seq seqh;
<br>

2370
2371 virtual_large_3eg 1_seqh;
2372 destin seq dseg;
2373
2374
2375 1/ build phase
2376
2377 function void build phase (uvm phase phase):
2378
2379 super.build phase (phase) ;
2380
2381 endfunction
2382
2383
2384 11 function new constructor
2385 ,
2386 function new (string name = "large seq test" uvm component parent);
2387
2388 super. new (name
=
,parent) ;
2389 addr 2'd2;
2390
2391 uvIn config db #
(bit [2])::set (this,"*", "bit", addr);
2392
2393
2394 endfunction
2395
2396 7/ run phase of large test seq
2397
2398
2399 task run phase (uvm phase phase) ;
2400 phase. raise objection (this) ;
2401 super. run phase (phase) ;

2402
2403
seqh = virtual large
dseq
1

= destin seq
seq :: type id :: create("l seqh");
:: type id :: create (" dseg");
2404 repeat(5)
2405 begin
2406 fork
;
2407 1_seqh.start (envh.v_seqr) . ;
2408 dseq.start (envh.destin agth.agth [addr] seqr)
2409 join
2410 end
2411
phase.drop objection ;
2412 (this)
2413 endtask
2414
2415
2416
2417 endclass
2418
2419
2420 7/ packaGES files
2421
2422
2423 package router pkg:
2424
2425 7/ including the all ruoter file
2426
2427 import uvm pkg ::*;
2428
2429 include "uvVn macros.svh"
2430
2431 include "destin agent config. sv"
2432 include "source agent config.sv"
2433 include "router env config. sv"
2434
2435
2436 include "destin xtn.sv"
2437
2438 include "source xtn.sv"
<br>

2439
2440 include "
sourCe seg.sv"
2441 include "source seqr.sv"
2442 include "source driver.sv"
2443 include "source monitor.sv"
2444 include "source agent.sv"
2445 include "sOurce agent top.Sv"
2446
2447 include "destin seq.sv" .
2448 'include "destin driver sv"
2449 include "destin monitor.sv"
2450 'include "destin _seqr. sv"
2451 include "destin agent.sv"
2452 include "destin agent top.sv"
2453
2454
2455 'include "virtual seqr.s"
2456 include "virtual seq.sv"
2457 include "tb scoreboard. sv"
2458 include "tb env.sv"
2459 'include "base test.sv"
2460
2461 //include "top.sv"
2462
2463 endpackage
2464
2465
2466 1/ MAKE files
2467
2468 /*
2469
2470 #Makefile for UVM Testbench - Lab 10
2471
2472 # SIMULATOR = Questà for Mentor's Questasim
2473 # SIMULATOR = VCS for Synopsys's VCs
2474
2475 SIMULATOR = VCS
2476
2477
2478 ESDB PATH=/home/cad/eda/ SYNOPSYS /VERDI 2022/verdi/T-2022.06-SP1/share/ PLI/VCS/LINUX64
2479
2480
2481 RTL= ../rtl/*
2482 work= work #1ibrary name
2483 SVTBl= ./tb/top. sv
2484 INC = +incdirt. ./tb tincdirt../test +incdirt. ./source_agent_top
+incdirt../destin agent top
2485 SVTB2 =../test/router pkg.sv
2486 VSIMOPT= -vopt -voptargs=tacc
2487 VSIMCOV= -COverage -Sva
2488 VSIMBATCH1= -c -do log -r /* ;coverage save -onexit mem covl;run -all; exit"
2489 VSIMBATCH2= -C -do " log -r /* ;coverage save -onexit mem cov2 ; run -all; exit"
2490 VSIMBATCH3= -c -do " log -r /* coverage save -onexit
; mem cov3; run -all; exit"
2491 VSIMBATCH4= -c -do " log -r /* ;COverage save -onexit mem cov4;run -all; exit"
2492
2493
2494 help:
2495 @echo

=====:
2496 @echo "
USAGE Imake target

2497 @echo "! clean clean the earlier log and intermediate
files.
2498 @echo "! sV cmp Create library and compile the
Code.
2499 @echo "! run test => clean, compile & run the simu latiOn for small packets in
batch mode.
2500 @echo "! run test1 clean, compile &
run the simulation for medium packets in
<br>

batch mode.
2501 @echo "! run test2 => clean, compile &
run the simulation for large packets in
batch mode.
2502 @echo "! run test3 => clean, compile &
run the simulation for ram even addr test
in batch mode.
2503 @echo "! view wave1 => To view the waveform of small
packets |

2504 @echo "! view wave2 => To view the waveform of medium
packets
2505 @echo"! view wave3 => To view the waveform of large
packets
2506 @echo "! view wave4 => To view the waveform of
ram even addr test
2507 @echo "!
.
reqress =) clean, compile and run all testcases in batch
mode
2508 @echo "! report => To merge coverage reports for all testcases and Convert to
html format.
2509 @echo "! cov =) To open merged coverage report in html
format.
2510 @echo

2511
:
2512 clean (SIMULATOR)
clean $
2513 SV_cmp :
SV cmp
$ (SIMULATOR)
2514 run test run test $ (SIMULATOR)
:

2515 run test1: run testl $ (SIMULATOR)

2516 run test2: run test2 $ (SIMULATOR)
2517 run test3 : run test3 $ (SIMULATOR)
2518 view wavel: view wavel $ (SIMULATOR)
2519 view wave2: view wave2 $ (SIMULATOR)
2520 view wave3: : view wave3 $ (SIMULATOR)
2521 view wave 4 view wave4 $ (SIMULATOR)
2522 regress : regress_$ (SIMULATOR)
2523 report: report $ (SIMULATOR)
2524 cov : cov $ (SIMULATOR)
2525
2526 Start of Definitions for Mentor's Questa Specific
Targets ---4
2527
2528 SV_cmp Questa:
2529 vlib $ (work)
2530 vmap work $ (work)
2531 vlog -work $(work) $ (RTL) $ (INC) $ (SVTB2 ) $ (SVTB1)
2532
2533 run test Questa: SV cmp
.
2534 vsim -cvgperinstance $ (VS IMOPT) $ (VS IMCOV) $ (VSI MBATCH1) -wlf wave filel wlf -l
test1.log -SV seed random work.top +UVM TESTNAME=small seg test
2535 vcover report -CVg -details -nocompactcrossbins -codeAll -assert -directive -html
mem COvl
2536
2537 run testl Questa: .
2538 vsim -cvgperinstance $ (VS IMOPT) $ (VSIMCOV) $ (VSIMBATCH2) -wlf wave file2 wlf -l
test2.log -Sv seed random work.top +UVM TESTNAME=medium seq test
2539 VCover repOrt -CVg -details -nocompactcrossbins -codeAll -assert -directive -html
mem cov2
2540
2541 run test2 Questa:
2542 vsim -cvgperinstance $ (VS IMOPT) $ (VSIMCOV) $ (VSIMBATCH3) -wlf wave file3. wlf -l
test3.log -SV seed random work.top +UVM TESTNAME=large_seq test
2543 VCover report -CVg -details -nocompactcrossbins -codeAll -assert -directive -html
mem COv3
2544
2545 run test3 Questa:
.
2546 vsim -cvgperinstance $ (VS IMOPT) $ (VSIMCOV) (VSIMBATCH4 )
$ -wlf wave file4 wlf -l
test4.log -SV Seed random work.top +UVM TESTNAME=ram even addr test
2547 VCover report -CVg -details -nocompactcrossbins -codeAll -assert -directive -html
mem cov4
2548
<br>

2549 view wave1 Questa:

2550 vsim -view wave filel .wlf
2551
2552 view wave2 Questa: .
2553 vsim -view wave file2 wlf
2554
2555 view wave3 Questa: .
2556 vsim -view wave file3 wlf
2557
2558 view wave Questa: 4

2559 vsim -view wave file4. wlf

2560
2561 report Questa:
2562 vCover merge mem cov mem covl mem cov2 mem cov3 mem cov4
2563 vcover report -cvg -details -nocompactcros sbins -codeAll -assert -directive -html
mem COV
2564
2565 regress Questa: clean Questa run test Questa run test1 Questa run test2 Questa
run test3 Questa report Questa cov Questa
2566
2567 cov Questa:
2568 firefox covhtmlreport/index.html&
2569
2570 clean Questa:
2571 rm -rf transcript *
*log* fcover* covhtml * mem cov* *.wlf modelsim. ini work
2572 clear
2573
2574 End of Definitions for Mentor's Questa Specific Targets

2575
2576 Start of Definitions for Synopsys's VCS Specific Targets

2577
2578 SV cmp VCs:
2579 vcs -l vcs.log -timescale-1ns/ 1ps -sverilog -ntb opts uvm -debug access+all -full64
-kdb -lca -P $ (FSDB PATH) /novas.tab $ (FSDB PATH)
/pli.a $ (RTL) $ (INC) $ (SVTB2)
$
(SVTB1)
2580
2581 run test VCS:
2582 ./simv -a vcs.log +fsdbfiletwave1. fsdb -cm dir ./mem covl +ntb random seed automatic
+UVM TESTNAME-small seq test
2583 urg -dir mem covl1.vdb -format both -report urgReportl
2584
2585 run test1 VCS:
2586 ./simv -a vcs.log +fsdbfiletwave2.fsdb -cm dir ./mem cov2 tntb random seed automatic
+UVM TESTNAME=medium seq test
2587 urg -dir mem cov2.vdb -format both -report urgReport2
2588
2589 run test2 vCS:
.
2590 ./simv -a vcs.log +fsdbfiletwave3.fs db -cm dir /mem cov3 +ntb random seed automatic
+UVM TESTNAME=large seq test
2591 urg -dir mem cov3.vdb -format both -report urgReport3
2592
2593 run test3 VCS:
.
2594 ./simv -a vcs.log +fsdbfile+wave4.fs db -cm dir /mem cov4 +ntb random seed automatic
+UVM TESTNAME-ram even addr test
2595 urg -dir mem cov4. vdb -format both -report urgReport4
2596
2597 view wave 1
VCS:
2598 verdi -ssf wavel. fsdb
2599
2600 view wave2VCS:
2601 verdi -ssf wave2.fsdb
2602
2603 view wave3 VCS:
2604 verdi -ssf wave3.fsdb
2605
2606 view wave 4 VCS:
2607 verdi -ssf wave4.fsdb
<br>

2608
2609 report VCs:
2610 urg -dir mem covl.vdb mem cov2. vdb mem cov3. vdb mem cov4.vdb -dbname
merged dir/merged test -format both -report urgReport
2611
2612 regress_VCS: clean VCS sv cmp VCS run test VCS run test1 vCS run test2_ VCS run test3_ VCS
report VCS
2613
2614 COV VCS:
2615 verdi -cov -covdir merged dir.vdb
2616
2617 clean VCS:
2618 rm -rf simv* csrc* *.tmp *.vpd *.vdb *.key *.log *hdrs.h urgReport* *.fsdb novas*
verdi *
2619 clear
2620
2621 # END of Definitions for Synopsys's VCS Specific Targets
-

2622
2623 */
2624
2625
2626 // OUTPUT ::: FOR 3 TEST CASES Small, Medium, Large
2627
2628 // Small PACKETS
2629
2630
2631 UVM INFO @
0: reporter [RNTST] Running test small seg test...
2632 UVM
INFO @
0: reporter [UVMTOP] UVM
testbench topology :
2633
2634 Name Type Size Value
2635
2636 uvm test_top small seq_test @474
2637 envh tb env @499
2638 destin agth destin agent_top @516
2639 agth [0] destin agent @660
2640 drvh destin driver @708
2641 rsp port uvm analysis port @725
2642 seq item port uvm seq item pull port @716
2643 monh destin monitor @691
2644 dmon port uvm analysis port a699
2645 seqr destin seqr @734
2646 rsp export uvm analysis export @742
2647 seq item export uvm_seq_ item pull_imp @848
2648 arbitration queue array
2649 lock queue array
2650 num last regs integral 32 d1
2651 num last rsps integral 32 'dl
2652 agth 1] [
destin agent @669
2653 drvh destin driver @886
2654 rsp port uvm analysis port @903
2655 seq item port uvm seq_ item pull port @894
2656 monh destin monitor @869
2657 dmon port uvm analysis port @877
2658 Seqr destin seqr @912
2659 rsp_ eXport uvm analysis export @920
2660 seq item export uvm seq item pull imp @1026
2661 arbitration queue array
2662 lock queue array
2663 num last_reqs integral 32 dl
2664 num last rsps integral 32 d1
2665 agth[21 destin agent @678
2666 drvh destin driver @1064
2667 rsp_port uvm analysis port @1081
2668 seg item port uvm seq item pull port @1072
2669 monh destin monitor @1047
2670 dmon port uvm analysis port @1055
2671 seqr destin seqr @1090
2672 rsp export uvm analysis export @1098
<br>

2673 seq item export uvm seq item pull imp @1204
2674 arbitration queue array
2675 lock queue array
2676 num last reqs integral 32 'dl
2677 num last rsps integral 32 'dl
2678 sb tb scoreboard @524
2679 destin fifo[O] uvm tlm analysis fifo # (T) @1274
2680 analysis export uvm analysis imp @1318
2681 get ap uvm analysis port @1309
2682 get_peek_export uvm get _peek_imp @1291
2683 put ap uvm analysis port @1300
2684 put export uvm put imp @1282
2685 destin fifo[l] uvm tlm analysis fifo # (T) @1327
2686 analysis_export uvm analysis_imp @1371
2687 get_ap uvm analysis port @1362
2688 get peek export uvm get peek imp @1344
2689 put_ap Uvm analysis_ port @1353
2690 put export uvm put imp @1335
2691 destin fifo[21 uvm tlm analysis fifo # (T) @1380
2692 analysis export uvm analysiS imp @1424
2693 get_ ap uvm_analysis_port @1415
2694 get peek export uvm_get peek_imp @1397
2695 put ap uvm analysis port @1406
2696 put export uvm put imp @1388
2697 Source fifo uvm tlm analysis fifo # (T) @1221
2698 analysis export uvm analysis imp @1265
2699 get ap uvm analysis port @1256
2700 get peek export uvm get peek imp @1238
2701 put ap uvm analysis port @1247
2702 put export uvm put imp @1229
2703 source agth Source_agent_top @508
2704 agth [0] Source agent @1438
2705 drvh SOurce driver @1468
2706 rsp port uvm analysis port @1485
2707 seq item port uvm seq item pull port @1476
2708 monh Source monitor @1451
2709 Smon port uvm analysis port @1459
2710 seqr SOurce seqr @1494
2711 rsp export uvm analysis export @1502
2712 seq item export uvm seq item pull_ imp @1608
2713 arbitration queue array
2714 lock queue array
2715 num last reqs integral 32 'd1
2716 num last rsps integral 32 'dl
2717 V_seqr virtual seqr @532
2718 rsp export uvm_analysis_export @540
2719 seg item export uvm seq item pull_imp C646
2720 arbitration queue array
2721 lock queue array
2722 num 1ast reqs integral 32 dl
2723 num last rsps integral 32 dl
2724
2725
2726 Signal ErrOr From Source Monitor = 1

2727
2728 Name Type Size Value
2729
2730 SOurce mon SOurCe xtn @1648
2731 destin address integral d0
2732 pay_ lenth integral 6 'd20
2733 header byte integral 8 'd80
2734 payload[0] integral 157
2735 payload [1] integral 'd15
2736 payload [2] integral 8 'd66
2737 payload[3] integral 8 'd39
2738 payload [4] integral 8 d13
2739 payload[5] integral 207
2740 payload [6] integral 173
2741 payload[7] integral 8 158
<br>

2742 payload [8] integral 'd91

2743 payload[9] integral
2744 payload[10] integral 220
2745 payload [11] integral 3 230
2746 payload[12] integral 8 'd113
2747 payload[13] integral 'd40
2748 payload[14] integral 130
2749 payload[15] integral 8 'd93
2750 payload [16] inteqral 'd55
2751 payload[17] integral 3 'dl8
2752 payload [18] integral 'd78
2753 payload[19] integral 188
2754 parity_byte integral 'd102
2755
2756
2757 Name Type Size Value
2758
2759 destin mon destin xtn @1630
2760 des address integral
2761 pay lenth integral 'd20
2762 header byte integral 'd80
2763 payload [0] integral 157
2764 payload [1] integral 'd15
2765 payload[2] integral 8 'd66
2766 payload[3] integral 'd39
2767 payload [4] integral d13
2768 payload [5] integral 207
2769 payload [6] integral 173
2770 payload[7] integral 158
2771 payload[8] integral 'd91
2772 payload[9] integral 8 'd0
2773 payload[10] integral 220
2774 payload[11] integral 230
2775 payload[12] integral 'd113
2776 payload [13] integral 'd40
2777 payload[14] integral 130
2778 payload[15] integal 'd93
2779 payload[16] integral 'd55
2780 payload [17] integral 'dl8
2781 payload[18 integral 8 d78
2782 payload [19] integral 188
2783 parity_byte integral 8 'dl02
2784 delay integral
2785
2786
2787 = Header_Byte Matched SuccessFull
2788
2789
2790 Payload Matched SuccessFull
2791
2792
2793 Parity Byte Matched SuccesSFull
2794
2795
2796
2797
2798
2799 SUCCESSFULLY MATCHED
2800
2801
2802
2803
2804
2805
2806
2807
2808 S0urCe Side functional COverage = 38.889
2809
2810
<br>

2811 destin side functional coverage =

41.667
2812
2813
2814
2815
2816 Signal Error From Source Monitor =
2817
2818 Name Type Size Value
2819
2820 Source mon SOurce xtn @1803
2821 destin address integral
2822 pay lenth integral 6 'd8
2823 header byte integral 'd32
2824 payload [o] integral 205
2825 payload[1] integral 'd57
2826 payload[2] integral 3 251
2827 payload[3] integral 251
2828 payload [4] integral 3 232
2829 payload[5] integral 8 147
2830 payload [6] integral 8 'd78
2831 payload[7] integral 188
2832 parity_byte integral 'd93
2833
2834
2835 Name Type Size Value
2836
2837 destin mon destin xtn @1807
2838 des address integral
2839 pay_ lenth integral d8
2840 header byte integral 'd32
2841 payload[0] integral 8 205
2842 payload[1] integral 'd57
2843 payload[2] integral 251
2844 payload[3] integral 251
2845 payload [4] integral 232
2846 payload [5] integral 147
2847 payload[6] integral 'd78
2848 payload[7] integral 188
2849 parity_byte integral 'd93
2850 delay integral d0
2851
2852
2853 == Header Byte Matched SuccessFul1
2854
2855
2856 = Payload Matched SuccessFull
2857
2858
2859 Parity Byte Matched SuccessFull
2860
2861
2862
2863
2864
2865 SUCCESSFULLY MATCHED
2866
2867
2868
2869
2870
2871
2872
2873
2874 SOurce side functional coverage = 38.889
2875
2876
2877 destin side functional COverage = 41.667
2878
2879
<br>

2880
2881
2882 Signal Error From Source Monitor =
2883
2884 Name Type Size Value
2885
2886 SOurce mon SOurce xtn @1826
2887 destin address integral
2888 pay lenth inteqral 'd2
2889 header byte integral 8 'd8
2890 payload [0] integral 129
2891 payload[l] integral 186
2892 parity_byte integral 'd51
2893
2894
2895 Name Type Size Value
2896
2897 destin mon destin xth @1830
2898 des address integral 'd0
2899 pay lenth integral 'd2
2900 header byte integral 'd8
2901 payload [0] integral 129
2902 payload [1] integral 8 186
2903 parity_ byte integral 'd51
2904 delay integral 'd0
2905
2906
2907 Header Byte Matched SuccessFull
2908
2909
2910 Payload Matched SuccessFull
2911
2912
2913
=
Parity Byte Matched SuccessFull ==
2914
2915
2916
2917
2918
2919 SUCCESSFULLY MATCHED
2920
2921
2922
2923
2924
2925
2926
2927
2928 SOurce side functional coverage 38.889
2929
2930
2931 destin side functional coverage =
41.667
2932
2933
2934
2935
2936 Signal Error From Source Monitor =
2937
2938 Name Type Size Value
2939
2940 SOurce mon SOurce xtn @1848
2941 destin address integral 2 'd0
2942 pay_lenth integral 'di8
2943 header byte integral 8 'd72
2944 payload [0] integral 203
]
2945 payload[1 integral 191
2946 payload[2] integral 'd123
2947 payload[3] integral 8 182
2948 payload[4] inteqral 8 174
<br>

2949 payload [5] integral 158

2950 payload[6] integral 'd92
2951 payload[7] integral 138
2952 payload[8] integral 3 'dl16
2953 payload[9] integral 8 'd90
2954 payload[10] integral 8 'd95
2955 payload[11] integral 159
2956 payload[12] integIal 8 190
2957 payload [13] integral 3 189
2958 payload[14] inteqral d66
2959 payload [1 5] integral 'di01
2960 payload[l6] integral 'd6
2961 payload [17] integral 136
2962 parity byte integral 8 'd83
2963
2964
2965 Name Type Size Value
2966
2967 destin mon destin xtn @1852
2968 des address integral
2969 pay lenth integral d18
2970 header byte integral 'd72
2971 payload[oj integral 203
2972 payload[1] integral 8 191
2973 payload[2] integral 'd123
2974 payload[3] integral 182
2975 payload [4] integral 174
2976 payload[5] integral 158
2977 payload[6] integral 8 d92
2978 payload [7] integral 138
2979 payload [8] integral 8 'd1l6
2980 payload[9] integral 'd90
2981 payload[10] integral 'd95
2982 payload[11] integral 159
2983 payload [12] integral 190
2984 payload [13] integral 189
2985 payload[14] integral 'd66
2986 payload[15] integral 'di01
2987 payload [16] integral 'd6
2988 payload[17] integral 8 136
2989 parity_byte integral 'd83
2990 delay integral
2991
2992
2993 Header Byte Matched SuccessFull
2994
2995
2996 Payload Matched SuccessFull
2997
2998
2999 Parity Byte Matched SuccessFull
3000
3001
3002
3003
3004
3005 SUCCESSFULLY MATCHED
3006
3007
3008
3009
3010
3011
3012
3013
3014 SOurce side functional coverage = 38.889
3015
3016
coverage =
3017 destin side functional 41,667
<br>

3018
3019
3020 ===E=======E====================

3021
3022 Siqnal Error From Source Monitor =
3023
3024 Name Type Size Value
3025
3026 SOuce mon SOurce xtn @1870
3027 destin address integral 2 'd0
3028 pay lenth integral 'dll
3029 header byte integral 'd44
3030 payload [0] integral 128
3031 payload[1] integral 'd61
3032 payload[2] integral 'd12
3033 payload[31 integral 3 'd90
3034 payload[4] integral 193
3035 payload[5] integral 'd56
3036 payload[6] integral 8 131
3037 payload [ integral 8 255
3038 payloa[8] integral 229
3039 payload [9] integral 8 139
3040 payload [10] integral 'dl4
3041 parity_byte integral 8 'd34
3042
3043
3044 Name Type Size Value
3045
3046 destin mon destin xtn @1874
3047 des address integral
3048 pay lenth integral d1l
3049 header byte integral 'd44
3050 payload[0] integral 128
3051 payload[1] integral 'd61
3052 payload[2] integral 'dl2
3053 payload [3] integral 'd90
3054 payload[4] integal 193
3055 payload [5] integral d56
3056 payload[6] integral 131
3057 payload [7] integral 255
3058 payload[8] integral 229
3059 payload [9] integral 8 139
3060 payload[10] integral d14
3061 parity_byte integral 'd34
3062 delay integral 'd0
3063
3064
3065 Header Byte Matched SuccessFull
3066
3067
3068 Payload Matched SuccessFull =*== EEEEEESEESE
3069
3070
=
3071 Parity Byte Matched SuccessFul1
3072
3073
3074
3075
3076
3077 SUCCESSFULLY MATCHED
3078
3079
3080
3081
3082
3083
3084
3085
3086 SOurce side functional coverage = 38.889
<br>

3087
3088
3089 destin side functional coverage = 41.667
3090
3091
3092
3093 .
3094 UVM INFO /home/cad/eda/SYNOPsYS/VCS/vcs /T-2022 06-SP1/etc/uvm/base/uvm objection. svh (1274
)@ 3650000 : reporter [TEST DONE] 'run' phase is ready to proceed to the 'extract' phase
3095
3096 --- UVM Report Summary
3097
3098 ** Report counts by severity
:
3099 UVM INFO 3
3100 UVM WARNING:
:
3101 UVM ERROR
:
3102 UVM FATAL
3103 ** Report counts by id
3104 [RNTST]
3105 [TEST DONE] 1
3106 [UVMTOP] 1

3107 $finish called from file .

"/home/cad/eda/SYNOPSYS/VCS/vcs/T-2022 06-SP1/etc/uvm/base/uvm root.svh", line 437.
3108 $finish at simulation time 3650000
l a ti o n p o r t
m u
3109 VCS Si Re
3110 Time: 3650000 ps
3111
3112
3113 // Medium PACKETS
3114
3115 UVM INFO @
0: reporter [RNTST] Running test medium seq test...
3116 UVM INFO @
0: reporter [UVMTOP] UVM testbench topology:
3117
3118 Name Type Size Value
3119
3120 uvm test top medium seq test @474
3121 envh tb env @499
3122 destin agth destin agent top @516
3123 agth[0] destin agent @660
3124 drvh destin driver @708
3125 rsp port uvm analysis port @725
3126 seq item port uvm seq item pull port @716
3127 monh destin monitor @691
3128 dmon port Uvm_analysis port @699
3129 seqr destin seqr @734
3130 rsp export uvm analysis export @742
3131 seq item export uvm seq item pull_ imp @848
3132 arbitration queue array
3133 lock queue array
3134 num last reqs integral 32 dl
3135 num last rsps integral 32 d1
3136 agth[1] destin agent @669
3137 drvh destin driver @886
3138 rsp port uvm analysis port @903
3139 seq item port uvm seq item pull port @894
3140 monh destin monitor a869
3141 dmon port uvm analysis port @877
3142 seqr destin seqr @912
3143 rsp export uvm analysis export @920
3144 seq_ item export uvm_seq_ item pull_imp @1026
3145 arbitration queue array
3146 lock queue array
3147 num last regs integral 32 dl
3148 num last rsps integral 32 'd1
3149 agth[2] destin agent @678
3150 drvh destin driver @1064
3151 rsp pOrt uvm analysis port @1081
3152 seq_item port uvm_seq_ item pull port @1072
3153 monh destin monitor @1047
<br>

3154 dmon port uvm analysis port @1055

3155 seqr destin seqr @1090
3156 rsp export uvm analysis export @1098
3157 seq item export uvm_seq_ item pull_imp @1204
3158 arbitration queue array
3159 lock queue array 0
3160 num 1last reqs integral 32
3161 num 1ast rsps integral 32 'd1
3162 sb tb scoreboard @524
3163 destin fifo[0] uvm tlm analysis fifo # (T) @1274
3164 analysis export uvm_analysis_ imp @1318
3165 get ap uvm analysis port @1309
3166 get peek export uvm get peek imp @1291
3167 put ap uvm_analysis_port @1300
3168 put export uvm put imp @1282
3169 destin fifo [1] uvm tlm analysis fifo # (T) @1327
3170 analysis export uvm analysis_ imp @1371
3171 get _aP uvm analysis port @1362
3172 get peek export uvm get peek imp @1344
3173 put_ap uvm analysis port @1353
3174 put export uvm put imp @1335
3175 destin fifo[2] uvm tlm analysis fifo # (T) C1380
3176 analysis export uvm analysis imp @1424
3177 get ap uvm analysis port @1415
3178 get peek export uvm_get peek_imp @1397
3179 put_ap uvm analysis port @1406
3180 put export uvm put imp @1388
3181 SOurce fifo uvm tlm analysis fifo # (T) @1221
3182 analysis export uvm analysis_ imp @1265
3183 get_aP uvm analysis port @1256
3184 get peek export uvm get peek imp @1238
3185 put ap uvm analysis port @1247
3186 put export uvm put imp @1229
3187 Source agth source agent top @508
3188 agth [0] sOurce agent @1438
3189 drvh Source driver @1468
3190 rsp port uvm analysis port @1485
3191 seq item port uvm seq item pull port @1476
3192 monh SOurce monitor @1451
3193 smon port uvm analysis port @1459
3194 seqr source seqr @1494
3195 rsp export uvm analysis export @1502
3196 seq item export uvm seq item pull_ imp @1608
3197 arbitration queue array
3198 lock queue array
3199 num last regs integral 32 'd1
3200 num last rsps integral 32 'dl
3201 V_seqr virtual seqr @532
3202 rsp export uvm analysis export @540
3203 seq item export uvm seq item pull imp @646
3204 arbitration queue array
3205 lock queue array
3206 num last regs integral 32 dl
3207 num last rsps integral 32 'd1
3208
3209
3210 Signal Error From Source Monitor = 1

3211
3212 Name Type Size Value
3213
3214 Source mon Source xtn @1648
3215 destin address integral 2 'd1
3216 pay_ lenth integral 'd27
3217 header byte integral 'd109
3218 payload[0] integral 8 195
3219 payload [1] integral 8 218
3220 payload[2] integral 227
3221 payload[3] integral 'd122
3222 payload[4] integral 8 d64
<br>

3223 payload [5] integral 191

3224 payload[6] integral 'd24
3225 payload[7] integral 138
3226 payload [8] integral 8 'd22
3227 payload [9] integral 8 235
3228 payload[10] integral 139
3229 payload[11] integral 3
'd42
3230 payload[12] integral 3 197
3231 payload [13] integral 'd44
3232 payload[14] integral 3 249
3233 payload [15] integral 141
3234 payload[16] integral 198
3235 payload[17] integral 220
3236 payload[18] inteqral 'd93
3237 payload [19] integral 224
3238 payload[20] integral 235
3239 payload[21] integral 'd45
3240 payload [221 integral 'd42
3241 payload[23] integral 8 214
3242 payload [2 4] integral 8 149
3243 payload[25] integral 196
3244 payload [2 6] integral 8 'd31
3245 parity_byte integral 8 146
3246
3247
3248 Name Type Size Value
3249
3250 destin mon destin xtn @1636
3251 des address integral 'dl
3252 pay lenth integral 'd27
3253 header byte integral 8 d109
3254 payload [0] integral 195
3255 payload[i] integral 218
3256 payload[2] integral 227
3257 payload[3] integral 'd122
3258 payload[4] integral 'd64
3259 payload[5] integral 191
3260 payload[6] integral 'd24
3261 payload[7] integral 138
3262 payload [8] integral d22
3263 payload[9] integral 235
3264 payload[10] integral 8 139
3265 payload [11] integral 'd42
3266 payload [12] integral 197
3267 payload[13] integral 8 'd44
3268 payload[14] integral 249
3269 payload[15] integral 141
3270 payload[16] integral 198
3271 payload[17] integral 220
3272 payload [18] integral 'd93
3273 payload[19] integral 8 224
3274 payload [2 0] integral 235
3275 payload [2 1] integral 'd45
3276 payload[22] integral 'd42
3277 payload[23] integral 214
3278 payload[24] integral 149
3279 payload [25] integral 196
3280 payload [2 6] integral 'd31
3281 parity byte integral 146
3282 delay integral
3283
3284
3285 == Header Byte Matched SuccessFull
3286
3287
3288 Payload Matched SuccessFull
3289
3290
3291 Parity Byte Matched SuccessFull
<br>

3292
3293
3294 ========E=========E=======E========

3295
3296
3297 SUCCESSFULLY MATCHED
3298
3299
3300
3301
3302
3303
3304
3305
side functional coverage
=
3306 SOurce 38.889
3307
3308
3309 destin side functional coverage =E
41.667
3310
3311
3312
3313
3314 Signal Error From Source Monitor = 1

3315
3316 Name Type Size Value
3317
3318 SOurce mon Source xtn @1803
3319 destin address integral 'dl
3320 pay lenth integral 'd29
3321 header byte integral 8 'dl17
3322 payload [0] integral 'di07
3323 payload[1] integral 'd22
3324 payload[21 integral 8 250
3325 payload[3] integral 133
3326 payload [4] integral ' dl06
3327 payload [5] lntegral 8 'd88
3328 payload[6] integral 'd61
3329 payload[7] integral 'dl6
3330 payload [8] integral 3 194
3331 payload[9] integral 'd56
3332 payload [10] integal 8 237
3333 payload[11] integral 8 'd37
3334 payload [12] integral 156
3335 payload[13] integral 'd34
3336 payload[14] integral 194
3337 payload[15] integral 3 210
3338 payload [1 6] integral 3 'dl15
3339 payload[17] integral 152
3340 payload[18] integral 242
3341 payload[19] integral 'di05
3342 payload[20] integral 8 237
3343 payload [21] integral 246
3344 payload[22] integral 8 175
3345 payload[23] integral 'd14
3346 payload[24] integral 8 249
3347 payload[25] integral 8 'd44
3348 payload [2 6] integral 3
'dl04
3349 payload[27] integral 186
3350 payload [28] integral 8 162
3351 parity_ byte integral 8 155
3352
3353
3354 Name Type Size Value
3355
3356 destin mon destin xtn @1807
3357 des address integral 'd1
3358 pay lenth integral 'd29
3359 header byte integral 8 'dll7
3360 payload[0] integral 'd107
<br>

3361 payload[1] integral 'd22

3362 payload[2] integral 250
3363 payload[3] integral 8 133
3364 payload[4] integral 'di06
3365 payload[5] integral 'd88
3366 payload [6] integral 'd61
3367 payload[7] integral 'd16
3368 payload[8] integral 194
3369 payload[9] integral 8 d56
3370 payload[10] integral 237
3371 payload[11] integral 'd37
3372 payload[12] integral 8 156
3373 payload[13] integqral 8 'd34
3374 payload[14] integral 8 194
3375 payload[15] integral 210
3376 payload[16] integral 'd115
3377 payload[17] integral 152
3378 payload [18] integral 242
3379 payload[19] integral 'd105
3380 payload[20] integral 8 237
3381 payload [21] integral 246
3382 payload[22] integral 175
3383 payload[23] integral 'd14
3384 payload[24] integral 8 249
3385 payload[25] integral 'd44
3386 payload [2 6] integral 'd104
3387 payload [27] integral 186
3388 payload [2 8] integral 162
3389 parity_byte integral 155
3390 delay integral
3391
3392
3393 Header Byte Matched Success Full
3394
3395
3396 Payload Matched SuccessFull
3397
3398
3399 Parity Byte Matched SuccessFull
3400
3401
3402
3403
3404
3405 SUCCESSFULLY MATCHED
3406
3407
3408
3409
3410
3411
3412
3413
=
3414 Source side functional cOverage 38.889
3415
3416
3417 destin side functional coverage =
41.667
3418
3419
3420
3421
3422 Signal Error From Source Monitor =
3423
3424 Name Type Size Value
3425
3426 Soure mon Source xtn @1826
3427 destin address integral 'dl
3428 pay lenth integral 'd25
3429 header byte integral 'di01
<br>

3430 payload [0] integral 'd76

3431 payload[1] integral 238
3432 payload[2] integral 216
3433 payload[3] integral 3 'd123
3434 payload [4] integral 8 'd86
3435 payload [5] integral 'd7
3436 payload[6] integral 243
3437 payload[7] integral 3 220
3438 payload[8] inteqral 130
3439 payload [9] integral 156
3440 payload[10] integral 142
3441 payload[11] integral 132
3442 payload[12] integral B
150
3443 payload[13] integral 8 'd13
3444 payload[14] integral 142
3445 payload[15] integral 3 195
3446 payload[16] integral 'd5
3447 payload[17] integral 239
3448 payload [18] integral 8 'dl19
3449 payload [19] integral 8 159
3450 payload [2 0] integral 'd69
3451 payload[21] integral 8 l62
3452 payload [22] integral 8 235
3453 payload[23] integral 8 'd74
3454 payload [2 4] integral 8 202
3455 parity byte integral 'd86
3456
3457
3458 Name Type Size Value
3459
3460 destin mon destin xtn @1830
3461 des address integral
3462 pay lenth integral 6 'd25
3463 header byte integral 'dl01
3464 payload [0] integral 'd76
3465 payload [ 1] integral 238
3466 payload[2] integral 216
3467 payload[3] integral 'd123
3468 payload [4] integral 'd86
3469 payload [5] integral
3470 payload [6] integral 243
3471 payload[7] integral 8 220
3472 payload [8] integral 130
3473 payload[9] integral 8 156
3474 payload[10] integral 142
3475 payload[11] integral 132
3476 payload [12] integral 150
3477 payload [13] integral 'd13
3478 payload[14] integral 142
3479 payload [15] integral 195
3480 payload[l6] integral 8 d5
3481 payload [17] integral 239
3482 payload [18] integral 'dl19
3483 payload[19] integral 159
3484 payload[20] integral 8 'd69
3485 payload[21] integral 162
3486 payload [22] integral 235
3487 payload[23] integral 'd74
3488 payload[2 4] integral 202
3489 parity byte integral 'd86
3490 delay integral
3491
3492
3493 = Header Byte Matched SuccessFull
3494
3495
3496 Payload Matched SuccessFull
3497
3498
<br>

3499 Parity Byte Matched SuccessFull

3500
3501
3502
3503
3504
3505 SUCCESSFULLY MATCHED
3506
3507
3508
3509
3510
3511
3512
3513
3514 SOurce Side functional COveraqe = 38.889
3515
3516
3517 destin side functional coverage =
41.667
3518
3519
3520
3521
3522 Signal Error From Source Monitor =
3523
3524 Name Type Size Value
3525
3526 SOurce mon SOurce xtn @1848
3527 destin address integral
3528 pay lenth integral 6 'd25
3529 header byte integal 8 'd101
3530 payload [0] integral 205
3531 payload[1] integral 8 215
3532 payload[2] integral 185
3533 payload[3] integral 8 'd37
3534 payload [4] lntegral 8 229
3535 payload[5] integral 3 'd89
3536 payload [6] integral 148
3537 payload [7] integral 'dl18
3538 payload [8] integral 151
3539 payload[9] integral 8 182
3540 payload[10] integral 8 'd76
3541 payload [11] integral 'd54
3542 payload [12] integral 'd48
3543 payload[13] integral 177
3544 payload[14] integral 3 'd26
3545 payload[15] integral 211
3546 payload [16] integral 'd39
3547 payload[17] integral 3
'd43
3548 payload[18] integral 8 'd26
3549 payload[19] integral 8 'd5
3550 payload [20] integral 'd17
3551 payload [2 1] integral 8 l81
3552 payload [22] integral 'd99
3553 payload[23] integral 8 196
3554 payload [2 4] integral 8 244
3555 parity_byte integral 'd74
3556
3557
3558 Name Type Size Value
3559
3560 destin mon destin xtn @1852
3561 des _address integral
3562 pay lenth integral d25
3563 header byte integral 'd101
3564 payload [0] integral 205
3565 payload [1] integral 8 215
3566 payload [2] integral 185
3567 payload[3] integral d37
<br>

3568 payload [4] integral 229

3569 payload[5] integral 'd89
3570 payload[6] integral 148
3571 payload[7] integral 'dl18
3572 payload [8] integral 151
3573 payload [9] integral 182
3574 payload[i0] integral 'd76
3575 payload[11] integral 'd54
3576 payload [12] integral 8 'd48
3577 payload[13] integral 177
3578 payload [14] integral 'd26
3579 payload[15] integral 8 211
3580 payload[16] interal 8 'd39
3581 payload[17] integral 8 'd43
3582 payload[18] integral 'd26
3583 payload[19] integral 'd5
3584 payload [20] integral 'dl7
3585 payload [21] integral 181
3586 payload[22] integral 'd99
3587 payload[23] integral 8 196
3588 payload[24] integral 244
3589 parity_byte integral 'd74
3590 delay integral 6 'd0
3591
3592
3593 Heade Byte Matched SuccessFull
3594
3595
3596 Payload Matched SuccessFull
3597
3598
3599 = Parity Byte Matched SuccessFull
3600
3601
3602
3603
3604
3605 SUCCESSFULLY MATCHED
3606
3607
3608
3609
3610
3611
3612
3613
3614 SOurCe side functional COverage = 38.889
3615
3616
3617 destin side functional coverage = 41.667
3618
3619
3620
3621
3622 Signal Error From Source Monitor =
3623
3624 Name Type Size Value
3625
3626 SOurCe mon SOurce xtn @1870
3627 destin address integral
3628 pay lenth integral 6 'd22
3629 header byte integral 8 'd89
3630 payload[0] integral 254
3631 payload[1] integral 8 184
3632 payload[2] integral 226
3633 payload [3] integral 3 'd56
3634 payload[4] integral 8 254
3635 payload[5] integral 'd69
3636 payload[6] inteqral 'di09
<br>

3637 payload[7] integral 232

3638 payload [8] integral 232
3639 payload[9] integral 'd57
3640 payload[10] integral 3 139
3641 payload [11] integral 8 185
3642 payload[12] integral 230
3643 payload[131 integral 3
175
3644 payload[14] integral 8 'a85
3645 payload[15] integral 'd123
3646 payload [16] integral 240
3647 payload[17] integral 8 l66
3648 payload[18] integral 'dl04
3649 payload[19] integral 3 167
0]
3650 payload[2 integral 240
1 ]
3651 payload[2 integral 8 'd27
3652 parity_byte integral 8 'd13
3653
3654
3655 Name IVpe Size Value
3656
3657 destin mon destin xtn @1874
3658 des address integral dl
3659 pay_lenth integral 6 'd22
3660 header byte integral 'd89
3661 payload [0] integral 254
3662 payload [ 1] integral 184
3663 payload [2] integral 226
3664 payload [3] integral 'd56
3665 payload[4] integral 254
3666 payload [5] integral 'd69
3667 payload [6] integral di09
3668 payload[7] integral 232
3669 payload[8] integral 232
3670 payload[9] integral 'd57
3671 payload [10] integral 139
3672 payload [11] integral 185
3673 payload [12] integral 230
3674 payload[13] integral 175
3675 payload[14] integral 'd85
3676 payload[15] integral 'd123
3677 payload[l6] integral 240
3678 payload[l7] integral 8 166
3679 payload [18] integral 'dl04
3680 payload [19] integral 167
3681 payload[2 0] integral 240
3682 payload [21] integral 'd27
3683 parity_ byte integral 'di3
3684 delay integral
3685
3686
3687 ==*===* Header Byte Matched SuccessFull
3688
3689
3690 ==== Payload Matched SuccessFull =*=
3691
3692
3693 Parity Byte Matched SuccessFull
3694
3695
3696
3697
3698
3699 SUCCESSFULLY MATCHED
3700
3701
3702
3703
3704
3705
<br>

3706
3707
3708 SOurce side functional COverage = 38. 889
3709
3710
3711 destin side functional coverage = 41.667
3712
3713
3714
3715 .
3716 UVM INFO /home/cad/eda/SYNOPSYS/VCs/vcs/T-2022 0 6-SPl/etc/uvm/base/uvm objection.svh (1274
) @
4850000: reporter [TEST DONE] 'run' phase is ready to proceed to the 'extract' phase
3717
3718 UVM Report Summary
3719
3720 ** Report :
COunts by Severity
3721 UVM INFO
:
3722 UVM WARNING
3723 UVM ERROR :
UVM
3724 FATAL:
3725 ** Report counts by id
3726 [RNTST]
3727 [TEST DONE]
3728 [UVMTOP]
3729 $finish called from file
"/home/cad/eda/SYNOPSYS/VCS/vcs/T-2022. 06-SP1/etc/uvn/base/uvm rot.svh", line 437.
3730 $finish at simulation time 4850000
3731 VCS S i m u l a t i o n Rep o rt
3732 Time: 4850000 ps
3733
3734
3735
3736 1/ Large PACKETS
3737
3738
3739 UVM INFO @
0: reporter [RNTST] Running test large seq test...
3740 UVM INFO @
0: reporter [UVMTOP] UVM testbench topology:
3741
3742 Name Type Size Value
3743
3744 uvm test_ tOp lrge seq test @474
3745 envh tb env @499
3746 destin agth destin agent top @516
3747 agth[0] destin agent @660
3748 drvh destin driver @708
3749 rsp_port uvm_analysis_port C725
3750 seq item port uvm seq item pull port @716
3751 monh destin monitor @691
3752 dmon port. uvm_ analysis_ port @699
3753 seqr destin seqr @734
3754 rsp export uvm analysis export @742
3755 seq item export uvn seq item pull imp @848
3756 arbitration queue array
3757 lock_queue array 0
3758 num_last reqs integral 32
3759 num 1ast rsps integral 32
3760 agth[1] destin agent @669
3761 drvh destin driver @886
3762 rsp_port uvm_analysis _port @903
3763 seq item port uvm_seq item pull port @894
3764 monh destin monitor @869
3765 dmon port uvn analys is port @877
3766 seqr destin seqr @912
3767 rsp export uvm analysis export @920
3768 seq item exXport uvm seq item pull imp @1026
3769 arbitration queue array
3770 lock queue array
3771 num_last_ reqs integral 3?
3772 num last rsps integral 32 'dl
<br>

3773 agth [2] destin agent @678

3774 drvh destin driver @1064
3775 rsp port uvm analysis port @1081
3776 seq item port uvm seq item pull port @1072
3777 monh destin monitor @1047
3778 dmon port uvm analysis port @1055
3779 seqr destin seqr @1090
3780 rsp export uvm analysis export @1098
3781 seq item export uvm seq item pull_imp @1204
3782 arbitration queue array
3783 lock queue array
3784 num last regs integral 32 'd1
3785 num
last rsps integral 32 'dl
3786 sb tb scoreboard @524
3787 destin fifo[0] uvm tlm analysis fifo # (T) @1274
3788 analysis_export uvm analysis imp @1318
3789 get ap uvm_analysis port @1309
3790 get peek export uvm get peek imp @1291
3791 put ap uvm analysis port @1300
3792 put export uvm put imp @1282
3793 destin_ fifo[1] uvm tlm analysis fifo # (T) @1327
3794 analysis export uvm analysis imp C1371
3795 get ap uvm analysiS port @1362
3796 get peek export uvm get peek imp @1344
3797 put ap uvm analysis port @1353
3798 put export uvm put_ imp @1335
3799 destin fifo[21 uvm tlm analysis fifo # (T) @1380
3800 analysis export uvm analysis imp @1424
3801 get_ ap uvm analysis port @1415
3802 get peek export uvm get peek imp @1397
3803 put_ap uvm analysis port @1406
3804 put export uvm put imp @1388
3805 Source fifo uvm tlmanalysis fifo # (T) @1221
3806 analysis export uvm analysis imp @1265
3807 get_ap uvm analysis port @1256
3808 get peek export uvm get peek_imp @1238
3809 put ap uvm_analysis port @1247
3810 put export uvm put imp @1229
3811 SOurce agth source_agent top @508
3812 agth [0] SOurce agent @1438
3813 drvh Source driver @1468
3814 rsp p0rt uvm analysis port @1485
3815 seq item port uvm_seq item pull port @1476
3816 monh Source monitor @1451
3817 Smon port uvm_analysis port @1459
3818 seqr Source seqr @1494
3819 rsp export uvm analysis export @1502
seq item export uvm_ seq_ @1608
3820 item pull_ imp
3821 arbitration queue array
3822 lock queue array
3823 num last reqs integral 32 'd1
3824 num last rsps integral 32
3825 V_seqr virtual seqr @532
3826 rsp export uvm analysis export @540
3827 seq item export uvm seq item pull imp @646
3828 arbitration queue array
3829 lock queue array
3830 num 1last reqs integral 32
3831 num last rsps integral 32
3832
3833
3834 Signal Error From Source Monitor = 1

3835
3836 Name Type Size Value
3837
3838 SOurce mon SOurce xtn @1648
3839 destin address integral 2
3840 pay_ lenth integral 6 57
3841 header byte integral 8 230
<br>

3842 payload[0] integral 'dl6

3843 payload [1] integral 8 161
3844 payload [2] integral 8 'd50
3845 payload [3] integral 8 245
3846 payload[4] integral 8 d74
3847 payload [5] integral 8 'd71
3848 payload[6] integral 202
3849 payload[7] integral 8 'd23
3850 payload[8] integral 8 'd73
3851 payload [9] integral 241
3852 payload [10] integral 8 'd80
3853 payload[11] integral 'd8
3854 payload [12] integral 8 'd79
3855 payload[13] integral 199
3856 payload [14] integral 'd54
3857 payload[15] integral 'd103
3858 payload [16] integral 192
3859 payload[17] integral 138
3860 payload [18] integral ' d125
3861 payload[19] integral 8 'd104
3862 payload [20] integral 8 157
3863 payload [21] integral 'd86
3864 payload[22] integral 'dl12
3865 payload[23] integral 'd11
3866 payload[24] integral 'd118
3867 payload[25] integral 133
3868 payload[2 6]
integral 'd24
3869 payload[27] integral 8 171
3870 payload [28] integral 8 133
3871 payload[29] integral 8 'd120
3872 payload[30] integral 8 d9
3873 payload [31] integral
3874 payload[32] integral 8 ' d83
3875 payload [33] integral 8 210
3876 payload [34] integral 224
3877 payload[35] integral 8 204
3878 payload [36] integral 'd14
3879 payload [37] integral 8 'di06
3880 payload [38] integral 'd122
3881 payload[39] integral 8 'd5
3882 payload [40] integral 'd119
3883 payload [41] integral 'd116
3884 payload[42] integral 'd23
3885 payload[43] integral 8 'd43
3886 payload[44] integral 8 'd91
3887 payload [45] integral 'd60
3888 payload [46] integral 'd91
3889 payload[47] integral 252
3890 payload [48] integral 'd42
3891 payload[49] integral 'd94
3892 payload [50] integral 154
3893 payload[51] integral 'd71
3894 payload [52] integral 8 'd67
3895 payload[53] integral 251
3896 payload[54] integral 8 'd75
3897 payload[55] integral 8 214
3898 payload [56] integral 8 'd117
3899 parity byte integral 146
3900
3901
3902 Name Type Size Value
3903
3904 destin mon destin xtn @1642
3905 des address integral 2
3906 pay lenth integral 57
3907 header byte integral 230
3908 payload [0] integral ' d16
3909 payload[1] integral 161
3910 payload[2] integral 'd50
<br>

3911 payload [3] integral 245

3912 payload [4] integral 'd74
3913 payload [51 integral 'd71
3914 payload[6] integral 202
3915 payload [7] integral 'd23
3916 payload [8] integral 'd73
3917 payload[9] integral 241
3918 payload[10] integral 'd80
3919 payload[11] integral 'd8
3920 payload[12] integral 'd79
3921 payload [13] integral 8 199
3922 payload[14] integral 8 'd54
3923 payload[15] integral 8 'd103
3924 payload [16] integral 192
3925 payload[17] integral 138
3926 payload[18] integral 'd125
3927 payload [19] integral 'di04
3928 payload [20] integral 157
3929 payload [21] integral 'd86
3930 payload[22] inteqral 8 'd112
3931 payload [23] integral 'dll
3932 payload [2 4] integral 'dll8
3933 payload [25] integral 133
3934 payload [2 6] integral 'd24
3935 payload[27] integral 171
3936 payload [28] integral 133
3937 payload [29] integral 'd120
3938 payload[30] integral d9
3939 payload[31] integral 'd0
3940 payload[32] integral 'd83
3941 payload[33] integral 210
3942 payload[34] integral 224
3943 payload[35] integral 204
3944 payload[36] integral 'd14
3945 payload [37] integral 'di06
3946 payload [38] integral 'd122
3947 payload[39] integral 'd5
3948 payload [40] integral 'd119
3949 payload[41] integral 'dl16
3950 payload[42] integral 'd23
3951 payload [43] integral 'd43
3952 payload[44] integral 8 'd91
3953 payload[45] integral 'd60
3954 payload [4 6] integral 'd91
3955 payload[47] integral 8 252
3956 payload [48] integral 'd42
3957 payload [49] integral 'd94
3958 payload [50] integral 154
3959 payload[51] inteqral 'd71
3960 payload[52] integral 'd67
3961 payload[53] integral 8 251
B962 payload [54] integral 8 'd75
3963 payload [55] integral 214
3964 payload [56] integral 'd1l7
3965 parity_byte integral 8 146
3966 delay integral d0
3967
3968
3969 Header Byte Matched SuccessFull
3970
3971
3972 Payload Matched SuccessFull
3973
3974
3975 = Parity Byte Matched SuccessFull
3976
3977
3978
3979
<br>

3980
3981 SUCCESSFULLY MATCHED
3982
3983
3984
3985
3986
3987
3988
3989
3990 Source side functional Coverage = 38.889
3991
3992
3993 destin side functional coverage = 41.667
3994
3995
3996
3997
3998 Signal Error From Source Monitor = 1

3999
4000 Name Type Size Value
4001
4002 SOurce mon Source xtn @1803
4003 destin address integral
4004 pay lenth integral 6 56
4005 header byte integral 226
4006 payload [0] inteqral 167
4007 payload [1] integral 212
4008 payload[2] integral 3
211
4009 payload[31 integral 8 'a71
4010 payload [4] integral 227
4011 payload [5] integral 'd91
4012 payload[6] integral 188
4013 payload[7] integral 207
4014 payload [8] integral 'd47
4015 payload[9] integral 8 'd0
4016 payload [10] integral 'dll7
4017 payload[11] integral 148
4018 payload[12] integral 206
4019 payload[13] integral 190
4020 payload [14] integral 8 d39
4021 payload[l5] integral 8 173
4022 payload [16] integral 206
4023 payload [17] integral 205
4024 payload [18] integral 'd76
4025 payload[19] integral 3 'd58
4026 payload [20] integral 3 143
4027 payload [21] integral 'd20
4028 payload[22] integral B
128
4029 payload [23] integral 195
4030 payload[24] integral 8 'd50
4031 payload[25] integral 'd79
4032 payload [2 6] integral 8 'd29
4033 payload[27] integral 'd31
4034 payload[28] integral 8 236
4035 payload [29] integral 8 137
4036 payload [30] integral 245
4037 payload[31] integral 185
4038 payload[32] integral 152
4039 payload[33] integral 3
'dl10
4040 payload [34] integral 8 239
4041 payload [35] integral 8 205
4042 payload[36] integral 234
4043 payload[37] integral 8 'd69
4044 payload [38] integral 8 171
4045 payload[39] integral 3 172
4046 payload [401 integral 8 212
4047 payload [41] integral 8 134
4048 payload[42] inteqral 194
<br>

4049 payload [43] integral 'd121

4050 payload [44] integral 8 231
4051 payload[45] integral 8 231
4052 payload[46] integral d21
4053 payload[47] integral 8 d50
4054 payload [48] integral 8 ' d41
4055 payload[49] integral d89
4056 payload [50] integral 8 'd24
4057 payload[51] integral 8 'd6
4058 payload [52] integral 'd103
4059 payload [53] integral 8 143
4060 payload [54] integral 208
4061 payload[55] integral 8 'd91
4062 parity_byte integral 190
4063
4064
4065 Name Type Size Value
4066
4067 destin mon destin xtn @1807
4068 des address integral 2
4069 pay lenth integral 56
4070 header byte integral 8 226
4071 payload [0] integral 8 167
4072 payload[1] integral 212
4073 payload[2] integral 211
4074 payload[3] integral 8 'd71
4075 payload[4] integral 227
4076 payload[5] integral 'd91
4077 payload[6] integral 8 188
4078 payload[7] integral 8 207
4079 payload [8] integral 'd47
4080 payload[9] integral
4081 payload [10] integral 8 'd117
4082 payload[11] integral 148
4083 payload [12] integral 206
4084 payload[13] integral 190
4085 payload [14] integral 'd39
4086 payload [15] integral 173
4087 payload [16] integral 206
4088 payload[17] integral 8 205
4089 payload[18] integral 'd76
4090 payload[19] integral 8 'd58
4091 payload [20] integral 143
4092 payload [21] integral 8 ' d20
4093 payload [22] integral 128
4094 payload[23] integral 8 195
4095 payload [24] integral 'd50
4096 payload[25] integral 8 'd79
4097 payload [2 6] integral 8 'd29
4098 payload [27] integral 8 'd31
4099 payload [28] integral 236
4100 payload [29] integral 8 137
4101 payload [30] integral 8 245
4102 payload[31] integral 8 185
4103 payload [32] integral 152
4104 payload[33] integral 8 dl10
4105 payload [34] integral 8 239
4106 payload[35] integral 205
4107 payload [36] integral 234
4108 payload [37] integral 'd69
4109 payload [38] integral 8 171
4110 payload [39] integral 8 172
4111 payload [40] integral 212
4112 payload[41] integral 8 134
4113 payload[42] integral 8 194
4114 payload [43] integral 'd121
4115 payload [44] integral 231
4116 payload [45] integral 8 231
4117 payload[46] integral 8 'd21
<br>

4118 payload [47] integral 'd50

4119 payload[48] inteqral d41
4120 payload [49] integral d89
4121 payload [50] integral 'd24
4122 payload[51] integral 'd6
4123 payload[52] integral ' di03
4124 payload[531 integral 143
4125 payload[54] integral 208
4126 payload[55] integral 'd91
4127 parity byte integral 190
4128 delay integral
4129
4130
4131 Header Byte Matched SuccesSFull
4132
4133
4134 Payload Matched SuccessFull
4135
4136
4137 Parity Byte Matched SuccessFull
4138
4139
4140
4141
4142
4143 SUCCESSFULLY MATCHED
4144
4145
4146
4147
4148
4149
4150
4151
4152 SOurce side functional coverage = 38.889
4153
4154
4155 destin side functional cOverage = 41.667
4156
4157
4158
4159
4160 Signal Error From Source Monitor = 1

4161
4162 Name Type Size Value
4163
4164 Source mon source xtn @1826
4165 destin address integral
4166 pay lenth integral 44
4167 header byte integral 8 178
4168 payload[0] integral 8 'd39
4169 payload [1 ] integral 'd125
4170 payload[2] integral 8 216
4171 payload[3] integral 8 215
4172 payload[41 integral 8
4173 payload[5] integral 8 'd125
4174 payload [6] integral 'd42
4175 payload[7] integral 3 173
4176 payload[8] integral 'd0
4177 payload[9] integral 'dl
4178 payload [10] integral 8 'd63
4179 payload[11] integral 8 'd89
4180 payload[12] integral 149
4181 payload[131] integral 8 200
4182 payload[14] integral 203
4183 payload[15] integral 3 'd43
4184 payload[16] integral 8 212
4185 payload[17] integral 8 'd113
4186 payload[18] inteqral 8 215
<br>

4187 payload [19] integral 134

4188 payload [20] integral 'di06
4189 payload [21] integral 8 215
4190 payload[22] integral 3 241
4191 payload[23] integral 8 'd2
4192 payload[24] integral 8 'd113
4193 payload[25] integral 135
4194 payload[26] integral 3 'dll5
4195 payload[27] integral 225
8]
4196 payload [2 integral 'd27
4197 payload [2 9] integral 190
4198 payload[30] integral 255
4199 payload[31] integral 171
4200 payload[32] integral 181
4201 payload [33] integral 3 247
4202 payload[34] integral 208
4203 payload [35] integral 'd120
4204 payload [36] integral 'd56
4205 payload[37] integral 8 147
4206 payload[38] integral 8 191
4207 payload[39] integral 225
4208 payload [40] integral 8 'dl4
4209 payload[41] integral 8 'd43
4210 payload[42] integral 8 158
4211 payload [43] integral 8 221
4212 parity_byte integal 145
4213
4214
4215 Name Type Size Value
4216
4217 destin mon destin xtn @1830
4218 des address integral 2
4219 pay lenth integral 6 44
4220 header byte integral 178
4221 payload [0] integral 'd39
4222 payload [ 1] integral 'd125
4223 payload[2] integral 216
4224 payload[3] integral 215
4225 payload[4] integral
4226 payload [5] integral 'dl25
4227 payload[6] integral d42
4228 payload[7] integral 8 173
4229 payload[8] integral d0
4230 payload[9] integral
4231 payload [10] integral d63
4232 payload[l1] integral 'd89
4233 payload[12] integral 149
4234 payload [13] integral 200
4235 payload[14] integral 203
4236 payload[15] integral 'd43
4237 payload[l61] integral 8 212
4238 payload [17] integral 'dl13
4239 payload [18] integral 215
4240 payload[19] integral 134
4241 payload[20] integral 'di06
4242 payload[21] integral 215
4243 payload [22] integral 241
4244 payload[23] integral 'd2
4245 payload[24] integral 'd113
4246 payload[25] integral 135
4247 payload [2 6] integral 'dl15
4248 payload [27] integral 8 225
4249 payload [28] integral 8 'd27
4250 payload[29] integral 190
4251 payload [30] integral 255
4252 payload [31] integral 171
4253 payload[32] integral 8 181
4254 payload[33] integral 247
4255 payload [34] integral 208
<br>

4256 payload [35] integral 'd120

4257 payload[36] integral 'd56
4258 payload [37] integral 147
4259 payload[38] integral 191
4260 payload[39] integral 225
4261 payload[40] integral 'd14
4262 payload[41] integral 'd43
4263 payload[42] integral 158
4264 payload [43] integral 221
4265 parity byte integral 145
4266 delay integral
4267
4268
4269 Header Byte Matched uccessFull
4270
4271
4272 Payload Matched SuccessFull
4273
4274
4275 Parity Byte Matched SuccessFull
4276
4277
4278
4279
4280
4281 SUCCESSFULLY MATCHED
4282
4283
4284
4285
4286
4287
4288
4289
4290 SOurce side functional coverage = 38.889
4291
4292
4293 destin side functional Coverage = 41.667
4294
4295
4296
4297
4298 Signal Error From Source Monitor = 1

4299
4300 Name Type Size Value
4301
4302 Source mon source xtn @1848
4303 destin address integral
4304 pay lenth integral 61
4305 header_byte integral 8 246
4306 payload[0] integral 8 'd81
4307 payload [1] integral d100
4308 payload[2] integral 8 'd82
4309 payload[3] integral 169
4310 payload [4] integral 8 203
4311 payload[5] integral 8 'd49
4312 payload [6] integral 201
4313 payload[7] integral 3 244
4314 payload[8] integral 'di3
4315 payload [9] integral d5
4316 payload [10] integral 8 'dl12
4317 payload [11] integral 8 'di05
4318 payload[12] integral 'd32
4319 payload[13] integral 8 216
4320 payload [14] integral 158
4321 payload [15] integral 3 'd68
4322 payload[16] integral 8 156
4323 payload[17] integral 8 179
4324 payload[18] inteqral 'd69
<br>

4325 payload [19] integral 'd64

4326 payload [20] integral 8 'd109
4327 payload[21] integral 8 130
4328 payload [22] integral 'd13
4329 payload [23] integral 8 d14
4330 payload [24] integral 8 172
4331 payload [25] integral 153
4332 payload [2 6] integral 8 'd65
4333 payload[27] integral 8 207
4334 payload [28] integral 'd57
4335 payload [29] integral 8 'd71
4336 payload[30] integral 251
4337 payload[31] integral 8 'd59
4338 payload [32] integral 'd21
4339 payload [33] integral 'd88
4340 payload[34] integral 255
4341 payload[35] integral 'd55
4342 payload [36] integral 'd53
4343 payload[37] integral 135
4344 payload [38] integral 203
4345 payload[39] integral 8 189
4346 payload [40] integral 170
4347 payload[41] integral 226
4348 payload[42] integral 243
4349 payload [43] integral 'd111
4350 payload [44] integral 180
4351 payload[45] integral 8 168
4352 payload [46] integral 8
4353 payload [47] integral 8 141
4354 payload[48] integral 8 'd92
4355 payload [49] integral 8 'd90
4356 payload [50] integral 'd57
4357 payload[51] integral 8 'd4
4358 payload [52] integral 8 'd18
4359 payload [53] integral 'd76
4360 payload[54] integral 8 176
4361 payload[55] integral 8 'dl08
4362 payload [56] integral 8 215
4363 payload [57] integral 'd86
4364 payload[58] integral 8 235
4365 payload[59] integral 'd98
4366 payload[60] integral 8 175
4367 parity_ byte integral 8 'd23
4368
4369
4370 Name Type Size Value
4371
4372 destin mon destin xtn @1852
4373 des address integral 2
4374 pay lenth integral 61
4375 header byte integral 8 246
4376 payload [0] integral 8 'd81
4377 payload[1] integral 8 dl00
4378 payload [2] integral 8 ' d82
4379 payload[3] integral 169
4380 payload [4] integral 8 203
4381 payload[5] integral 'd49
4382 payload[6] integral 201
4383 payload[7] integral 244
4384 payload[8] integral 'd13
4385 payload [9] integral 'd5
4386 payload[10] integral 8 'd112
4387 payload[11] integral 'd105
4388 payload[12] integral 'd32
4389 payload[13] integral 8 216
4390 payload [14] integral 158
4391 payload[15] integral 'd68
4392 payload[16] integral 8 156
4393 payload[17] integral 179
<br>

4394 payload[18] integral 'd69

4395 payload[19] integral 'd64
4396 payload [20] integral 'di09
4397 payload [2 1] integral 130
4398 payload[22] integral 'd13
4399 payload[23] integral 'd14
4400 payload[241 integral 172
4401 payload[25] integral 153
4402 payload[26] integral 8 'd65
4403 payload[27] integral 207
4404 payload [2 8] integral 8 'd57
4405 payload[29] integral 'd71
4406 payload[30] integral 251
4407 payload[31] integral 8 'd59
4408 payload[32] integral 'd21
4409 payload[331 integral 'd88
4410 payload [34] integral 255
4411 payload [35] integral 'd55
4412 payload[36] integral 'd53
4413 payload[37] integral 8 135
4414 payload [38] integral 203
4415 payload [39] integral 189
4416 payload[40] integral 170
4417 payload [41] integral 8 226
4418 payload[42] integral 243
4419 payload[43] integral 'd1l1
4420 payload[44] integral 180
4421 payload[45] integral 168
4422 payload[46] integral 8 'd2
4423 payload [47] integral 141
4424 payload [48] integral d92
4425 payload [49] integral 'd90
4426 payload[50] integral d57
4427 payload [51] integral 'd4
4428 payload [52] integral 'd18
4429 payload [53] integral d76
4430 payload [54] integal 176
4431 payload[55] integral 'd108
4432 payload[56] integral 215
4433 payload[57] integral d86
4434 payload[58] integral 235
4435 payload [59] integral 8 d98
4436 payload [ 60] integral 175
4437 parity byte inteqral 'd23
4438 delay integral 'd0
4439
4440
4441 Header Byte Matched SuccessFull
4442
4443
4444 Payload Matched SuccessFull =*== EEEEEESEESE
4445
4446
=
4447 Parity Byte Matched SuccessFul1
4448
4449
4450
4451
4452
4453 SUCCESSFULLY MATCHED
4454
4455
4456
4457
4458
4459
4460
4461
4462 SOurce side functional coverage = 38.889
<br>

4463
4464
4465 destin side functional coverage = 41.667
4466
4467
4468
4469
4470 Signal Error From Source Mornitor =
4471
4472 Name Type Size Value
4473
4474 SOurce mon SOurce xtn @1870
4475 destin address integral
4476 pay lenth integral 53
4477 header byte integral 214
4478 payload[0] integral 3 'd87
4479 payload [1] integral 247
4480 payload [2] integral 228
4481 payload[3] integral 8 210
4482 payload [4] integral 8 248
4483 payload[5] integral 168
4484 payload [ 6] integral 8 'dl8
4485 payload[7] integral 'd71
4486 payload [8] integral 'd83
4487 payload [9] integral 8 'di04
4488 payload[10] integral 184
4489 payload [11] integral 243
4490 payload[12] integral 'd25
4491 payload[13] integral 247
4492 payload[14] integral 8 'd24
4493 payload[15] integral 8 'd19
4494 payload [16] integral 'd57
4495 payload[17] integral 8 'd52
4496 payload[18] integral 136
4497 payload [19] integral 182
4498 payload [2 0]
integral 8 'd42
4499 payload [21] integral 3 191
4500 payload [22] integral 150
4501 payload[23] integral 'd94
4502 payload[24] integral 186
4503 payload[25] integral 'd126
4504 payload [2 6] integral 8 'd78
4505 payload[27] integral 'd126
4506 payload [2 8]
integral 252
4507 payload [2 9] integral 'd28
4508 payload[30] integral 3 'd8
4509 payload[31] integral 'd113
4510 payload [32] integral 242
4511 payload[33] integral 'd74
4512 payload[34] integral 251
4513 payload[35] integral 8 'd39
4514 payload [36] integral 3 '
d92
4515 payload [37] integral 8 201
4516 payload[38] integral 151
4517 payload[39] integral 8 195
4518 payload [4 0] integral 8 192
4519 payload [41] integral 132
4520 payload [421 integral 198
4521 payload[43] integral 'd52
4522 payload [44] integral 3
252
4523 payload [451 integral 8 dll6
4524 payload[46] integral 8 233
4525 payload [47] integral 'd46
4526 payload[48] integral 8 dl09
4527 payload [49] integral 8 'd57
4528 payload [50] integral 3 'd46
4529 payload [51] integral 8 'd86
4530 payload [52] integral 8 189
4531 parity byte integral 'd30
<br>

4532
4533
4534 Name Type Size Value
4535
4536 destin mon destin xth @1874
4537 des address integral 2
4538 pay_lenth integral 53
4539 header byte integral 214
4540 payload[o] integral 8 'd87
4541 payload [1] integral 8 247
4542 payload [2] integral 228
4543 payload[3] integral 210
4544 payload [4] integral 248
4545 payload [5] integral 168
4546 payload[6] integral 8 'd18
4547 payload[7] integral 'd71
4548 payload[8] integral 8 'd83
4549 payload [9] integral 8 'd104
4550 payload[10] integral 8 184
4551 payload [11] integral 243
4552 payload [12] integral 8 'd25
4553 payload [13] integral 247
4554 payload[14] integral 8 'd24
4555 payload[15] integral 'd19
4556 payload [16] integral 'd57
4557 payload[17] integral 8 'd52
4558 payload[18] integral 136
4559 payload [19] integral 182
4560 payload [20] integral 8 'd42
4561 payload[21] integral 8 191
4562 payload [22] integral 150
4563 payload[23] integral 'd94
4564 payload [24] integral 186
4565 payload [25] integral ' d126
4566 payload [2 6] integral 'd78
4567 payload[27] integral 'd126
4568 payload [28] integral 252
4569 payload [2 9] integral 'd28
4570 payload [30] integral 'd8
4571 payload[31] integral 8 d1l3
4572 payload [32] integral 242
4573 payload [33] integral 8 'd74
4574 payload[34] integral 251
4575 payload [35] integral 8 'd39
4576 payload[36] integral 'd92
4577 payload[37] integral 8 201
4578 payload[38] integral 151
4579 payload[39] integral 195
4580 payload [40] integral 192
4581 payload[41] integral 8 132
4582 payload [42] integral 198
4583 payload[43] integral 8 'd52
4584 payload [44] integral 8 252
4585 payload [45] integral 8 'd116
4586 payload [46] integral 233
4587 payload [47] integral 8 'd46
4588 payload [48] integral dl09
4589 payload[49] integral 'd57
4590 payload[50] integral 'd46
4591 payload[51] integral 'd86
4592 payload[52] integral 8 189
4593 parity_ byte integral 8 'd30
4594 delay integral
4595
4596
4597 Header Byte Matched SuccessFull
4598
4599
4600 Payload Matched SuccessFull
<br>

4601
4602
4603 ======***=*=== Parity Byte Matched SuccessFull
4604
4605
4606
4607
4608
4609 SUCCESSFULLY MATCHED
4610
4611
4612
4613
4614
4615
4616
4617
4618 SOurce side functional coverage = 38.889
4619
4620
4621 destin side functional coverage = 41.667
4622
4623
4624
4625 .
4626 UVM INFO /home/cad/eda/sYNOPsYS/VCS/vcs/T-2022 0 6-SP1/etc/uvm/base/uvm objection.svh(12 74
) @
8110000 : reporter [TEST DONE] 'run' phase is ready to proceed to the extract' phase
4627
4628 UVM Report Summary
4629
4630 ** Report counts by severity
4631 UVM INFO :
:
4632 UVM WARNING
4633 UVM ERROR :
4634 UVM FATAL :
4635 ** Report Counts by id
4636 [RNTST] 1
4637 [TEST DONE]
4638 [UVMTOP]
4639 $finish called from file
"/home /cad/eda/SYNOPSYS/VCS/vcs/T-2022.06-SPl/etc/uvn/base/uvm root.svh", line 437.
4640 $finish at simulation time 8110000
4641 VCS m u l a t i o n Re p Or t
4642 Time: 8110000 ps
4643