Chinese Journal of Electronics

vol. 33, no. 5, pp. 1137–1146, September 2024

https://doi.org/10.23919/cje.2023.00.091

RESEARCH ARTICLE

Realization of Complete Boolean Logic and

Combinational Logic Functionalities on a
Memristor-Based Universal Logic Circuit
Xiaojuan LIAN, Chuanyang SUN, Zeheng TAO, Xiang WAN, Xiaoyan LIU, Zhikuang CAI,
and Lei WANG
College of Integrated Circuit Science and Engineering, Nanjing University of Posts and Telecommunications,
Nanjing 210023, China

Corresponding author: Lei WANG, Email: [email protected]

Manuscript Received March 24, 2023; Accepted November 13, 2023
Copyright © 2024 Chinese Institute of Electronics

Abstract — Memristors are a promising solution for building an advanced computing system due to their excellent
characteristics, including small energy consumption, high integration density, fast write/read speed, great endurance
and so on. In this work, we firstly design three basis logic XNOR1, XNOR2 and XOR gates by virtue of memristor
ratioed logic (MRL), and further construct 1-bit numerical comparators, 2-bit numerical comparators and full adder 1
based on the above XNOR1, XNOR2 and XOR gates. Furthermore, we propose and design a universal logic circuit
that can realize four different kinds of logic functions (AND, OR, XOR, XNOR) at the same time. Subsequently, a
full adder 2 is built using XOR function of this universal logic circuit. Compared with the traditional CMOS circuits,
the universal logic circuit designed in this work exhibits several merits such as fewer components, less power, and
lower delay. This work demonstrates that memristors can be used as a potential solution for building a novel com-
puting architecture.
Keywords — Memristor, Universal logic circuit, Memristor ratioed logic, Numerical comparator, Full adder.
Citation — Xiaojuan LIAN, Chuanyang SUN, Zeheng TAO, et al., “Realization of Complete Boolean Logic and
Combinational Logic Functionalities on a Memristor-Based Universal Logic Circuit,” Chinese Journal of Electronics,
vol. 33, no. 5, pp. 1137–1146, 2024. doi: 10.23919/cje.2023.00.091.

I. Introduction tecture requires frequent data transfer between comput-

ing units and storage units, which seriously affects the
Since the invention of the transistor, it has been power consumption and speed of the system [4]. In order
widely used in various electronic devices [1]. With the to address such challenges, many strategies have been
appearance of integrated circuits, the volume and power proposed in the post-Moore era, including optimizing the
consumption of traditional circuits are greatly reduced, preparation process of device circuits or exploring a novel
which promotes the rapid development of the field of logical computing architecture [5].
microelectronics, and the size of transistors is gradually Among various solutions, the use of memristors to
reduced to the nanometer level. This allows hundreds of build a novel logical computing architectures is considered
millions of transistors to be integrated into a chip of unit as one of the best means. Memristor, originally proposed
area. Gordon Moore came up with what is known as by Leon O. Chua in 1971 [6], was first physically imple-
Moore’s Law, which predicts that the number of transis- mented by Williams team of Hewlett-Packard (HP) La-
tors on a chip doubles every 18 months [2]. However, up boratory in 2008 [7]. It is considered to be the fourth basic
to now, Moore’s Law is being challenged in terms of mul- electronic component in addition to resistance, capaci-
tiple aspects such as materials, processes and costs [3]. tance and inductance. Nowadays, memristors are con-
Similarly, the traditional von Neumann structure is con- sidered to be one of the most competitive candidates for
strained by Moore’s Law. This kind of computing archi- the next generation of low-power and high-density stor-

Associate Editor: Prof. Yaxin ZHANG, University of Electronic Science and Technology of China.
 1138 Chinese Journal of Electronics, vol. 33, no. 5

age devices because of their simple structure, ultra-low the domain of associative memory. They offer enhanced
switching speed, low power consumption, continuously capabilities for tasks such as pattern recognition, infor-
adjustable conductance state and compatibility with ex- mation retrieval, and cognitive computing, thereby driv-
isting complementary metal oxide semiconductor (CMOS) ing innovation in memory-dependent fields [22]–[24].
processes [8]–[10]. The storage function of memristors de-
pends on their electronic properties, and under external II. Logic Circuit Modelling Strategies
excitation, they can switch reversibly between two differ-
1. Electrical characteristics of the memristor
ent resistance states. The two resistance states correspond
model
to the 0 and 1 states in a digital circuit, respectively [11].
At present, two types of memristors categories can Here the well-known HP memristor model is adopted.
be directly applied for logic circuits applications, i.e., In 2008, Strukov et al. [7] at HP Laboratories designed
state logic circuit and level logic circuit. The state logic and fabricated a memory device based on Pt/TiO2/Pt
is represented by the high resistance Roff and low resis- sandwich stack structure. The conduction mechanism of
tance Ron of the memristor, which are considered as logics Pt/TiO2/Pt devices can be explained by the motion of
“0” and “1”, respectively. The state logic circuit mainly TiO2/TiO2–x interface caused by oxygen vacancy migra-
includes the material implication logic operation (IMP), tion under external electric field [7]. Under the action of
memristor-aided logic (MAGIC) and memristor-as-driver voltage excitation, the thickness of TiO2 and TiO2–x
gates (MAD) [12]. The IMP requires multiple steps to changes, that is, the proportion in the functional layer
implement the required logic, including operations such changes [25]. The mathematical expression is
as set 0, set 1, and clear, which increases the time for ( ( ))
logical calculations during the process [13], [14]. MAGIC w (t) w (t)
M (t) = Ron + Roff 1 − (1)
and MAD logics, on the other hand, require a write to D D
the memristor before each operation, and their circuit
structures are not conducive to large-scale integration where w (t) is the thickness of the TiO2−x film; Ron is
[15]–[17]. In contrast, the level logic is represented by the equivalent to the resistance of the doped layer; Roff is
voltage level, where the high voltage Vhigh and low volt- equivalent to the resistance of the undoped layer; D is
age Vlow are considered as logics “1” and “0”, respectively. total thickness of the film. The differential equation sat-
The memristor ratioed logic (MRL) is mainly the level isfied by w (t) is
logic that is compatible with current CMOS technol-
dw (t) Ron
ogies because its logic states are defined as all voltage = µv i (t) f (w) (2)
levels [18]. Compared with traditional CMOS circuits, dt D
the MRL-based circuits have many advantages, such as where µv is the average ion mobility. Since the memris-
lower power consumption, higher integration density, tor is a nano device, when a small voltage is applied into
and fewer devices [19]. Compared with the state logic cir- the memristor externally, a large electric field will be
cuits, the MRL-based circuits also have great advan- generated in the resistance switching layer, resulting in
tages, which can complete the combinational logic func- the nonlinear movement of the storage ions. To more ac-
tionalities without complex peripheral circuits and more curately simulate ion migration, we can simulate the
operation steps [20], [21]. nonlinear motion of ions by multiplying the right side of
In this work, we leverage the computational prin- (2) by a Strukov window function f (w) = 1 − 4(w/D−
ciples of MRL to harness the unique advantages offered 0.5)2 [12], and thus the pinch hysteresis loop of the
by memristors as fundamental computational logic ele- oblique “8” is obtained after simulating the nonlinear
ments. We integrate these advantages with the voltage- transition model constructed above. In the context of our
controlled characteristics of metal oxide semiconductor proposed logic operation method, it is imperative to
(MOS) technology to conceive the hybrid circuit. Firstly, highlight that the most substantial factor influencing the
we proposed three basic logic XNOR1, XNOR2 and accuracy of logic operations is the OFF/ON ratio exhib-
XOR gates on the basis of the MRL design, and further ited by the memristor. Through extensive simulation and
built 1-bit numerical comparators, 2-bit numerical com- analysis, we can obtain that when Ron = 1 kΩ, the logic
parators and full adder 1 based on the above XNOR1, circuit can guarantee the correct logic output as long as
XNOR2 and XOR gates. In addition, we designed a uni- Roff varies between 30 kΩ and 120 kΩ. Therefore, the pa-
versal logic circuit that can realize four different kinds of rameters of HP memristor model used in this work are
logic functions (AND, OR, XOR, XNOR) at the same Ron = 1 kΩ, Roff = 100 kΩ and D = 2 nm respectively.
time, and then a full adder 2 was further built using The parameters of the NMOS transistor in the simula-
XOR function of this universal logic circuit. Compared tion are L = 180 nm and W = 220 nm respectively.
with traditional CMOS circuits, the logic circuits de-
signed in this paper exhibit fewer devices, less power, 2. Design principles of the MRL
and lower delay. These innovative logic circuits hold im- The concept of MRL was proposed by Kvatinsky et
mense potential for emerging technologies, particularly in al. in 2012 arising from the nonlinear property of the
Realization of Complete Boolean Logic and Combinational Logic Functionalities on a Memristor-Based... 1139

memristor that is similar to the transistor operated in (a) Vcc (b) Vcc (c)
the triode region [18]. One of the standout features of M1
XNOR1 XNOR2 XOR
MRL logic lies in its ability to achieve AND and OR op- T1 T2 M2
M1 M2 A A T1
erations with just two components, leading to a substan-
B M1 B T2
tial reduction in the overall device counts compared to A T1
traditional CMOS logic gates, especially for simple logic T2 M2
B
operations. Consequently, when tasked with the design of
complex combinatorial logic circuits, the advantages of Figure 2 (a) XNOR1, (b) XNOR2, and (c) XOR gates.
reduced device count become increasingly evident, direct-
ple is introduced in detail below.
ly resulting in a reduction in circuit area.
For XNOR1 shown in Figure 2(a), i) when A = B =
Figure 1(a) represents AND gate. When Vin1 = Vin2 =
“0”, transistors T1 and T2 are both turned off, and the
“1”/“0”, Vout = “1”/“0”; when Vin1 = “1”, Vin2 = “0”, the
level of the output point is pulled to Vcc , resulting in
current flows from M1 to M2. In this case, M1 shows
XNOR1 = “1”; ii) when A = B = “1”, the whole circuit is
Roff , while M2 exhibits Ron . The output voltage is there-
in a high-level environment, making XNOR1 = “1”; iii)
fore calculated according to the voltage division princi-
when A = “1”, B = “0”, transistor T1 is turned off, and
ple [18]:
transistor T2 is turned on. The resistance state of M1 re-
Ron mains unchanged, and the resistance state of M2 is set to
Vout = Vhigh ≈ 0 (3)
Ron + Roff Ron , leading to XNOR1=“0”; iv) when A = “0”, B = “1”,
transistor T2 is turned off, while transistor T1 is turned
Figure 1(b) represents OR gate. When Vin1 = Vin2 = on. The resistance state of M2 remains unchanged, and
“1”/“0”, Vout = “1”/“0”; when Vin1 = “1”, Vin2 = “0”, the M1 resistance state is set to Ron , resulting in XNOR1 =
current flows from M3 to M4. In this case, M3 shows Ron , “0”.
while M4 exhibits Roff . The output voltage is therefore The working principle of XNOR2 gate illustrated in
calculated according to the voltage division principle [18]: Figure 2(b) is completely different from the XNOR1. For
Roff XNOR2, M1 and M2 form an AND gate. Only when
Vout = Vhigh ≈ 1 (4) A = B = “1”, the drain terminal of the transistor shows a
Ron + Roff
high level, otherwise it is a low level. At this time the
Since MRL achieves its logic function based on volt- circuit is in a high-level environment, thus XNOR2=“1”.
age calculation, this feature makes MRL circuits have Besides, the two parallel transistors are turned off at the
good compatibility with CMOS circuits. Based on this, same time only when A = B = “0”, blocking the path be-
Kvatinsky et al. further implemented NAND and NOR tween the output and the OR gate. This makes the out-
logics by adding a CMOS inverter in [18], as shown in put point level pulled to Vcc at this time, causing
Figure 1(c) and 1(d). XNOR2 = “1”. When A = “1”, B = “0” or A = “0”, B =
“1”, there is a conductive path connecting OR gate at
≥1 the output point, then XNOR2 = “0”.
Vin1 Vin1
M1 Vout M3 Vout The XOR gate shown in Figure 2(c) is designed ac-
Vin2 Vin2 cording to the dual structure of XNOR2. The OR gate
M2 M4 composed of M1 and M2 is in low level only when
(a) (b)
A = B = “0”, or it is in high level. At this time the cir-
≥1 cuit is in a low-level environment and XOR=“0”. In ad-
X1 X1
Y=X1+X2
dition, the two transistors connected in series are turned
Y=X1X2
X2 X2 on at the same time only when A = B = “1”, thus form-
ing a path between the output point and ground, and re-
(c) (d) sulting in XOR=“0”; when A = “1”, B = “0” or A = “0”,
Figure 1 (a) AND, (b) OR, (c) NAND, and (d) NOR gates. B = “1”, there is no conduction path, consequently mak-
ing XOR = “1”.
Compared with the XNOR and XOR logic gates
III. Memristor-Based Universal Logic
proposed in the previous literatures [26]–[30], aforemen-
Circuit tioned logic gates XNOR1, XNOR2 and XOR designed
Using memristors to construct the basic digital logic in this work use fewer memristors and transistors, as
gates is the basis of realizing complex combinatorial log- shown in Table 1 and Table 2. In addition, we conduct-
ic gates, and it is also one of the solutions to building in- ed power and area consumption calculations for XNOR1,
memory computing devices. In this part, we further de- XNOR2, and XOR gates. For the circuit simulations per-
signed three basic logic gates to achieve XNOR and formed in Cadence Virtuoso, calculating power consump-
XOR functions, named as XNOR1, XNOR2 and XOR tion for transistors or resistors is a straightforward pro-
respectively, as shown in Figure 2. The working princi- cess. This involved exporting transient power waveform
 1140 Chinese Journal of Electronics, vol. 33, no. 5

Table 1 Quantity comparison of transistors and memristors of dif- 22.64 μW; XNOR2: 36.28 μW; XOR: 25.77 μW.
ferent XNORs
Concerning the device area calculations, the individ-
Device type [27] [29] [30] XNOR1 XNOR2 ual memristor occupies an area of 0.0011 μm2 [31], while
Transistor 6 3 3 2 2 transistors, determined by their W /L ratio, have an area
Memristor 2 4 3 2 2 of 0.0396 μm2. Additionally, the resistors of 50 kΩ used
in the work encompass an area of 0.4 μm2. Therefore,
Table 2 Quantity comparison of transistors and memristors of dif- XNOR1, XNOR2, and XOR gates that employ an equal
ferent XORs number of components have an approximate device area
size of 0.5 μm2.
Device type [26] [28] [29] XOR
Furthermore, we simulated the waveforms of the
Transistor 4 2 3 2
three basic logic gates, as shown in Figure 3. It is worth
Memristor 2 6 4 2
noting that there exist some unwanted spikes in XNOR1
gate when the resistance state is changed, but not ob-
data directly from Cadence and subsequently computing
the average power using the “average” function. How- served in XNOR2 gate. This can be explained by differ-
ever, the retrieval of power waveform data for modeled ent switching speed between memristors and transistors.
memristors proves to be less straightforward. In these in- For the XNOR1 gate, when A = “0”, B = “1”, R(M1) =
stances, we calculated the average power consumption Ron , R(M2) = Roff . When A = B = “0”, M1 maintains
for each memristor by determining the voltage difference the previous low-impedance state unchanged, while M2
across its terminals and multiplying it by the transient switches to a low resistance state due to the faster switch
current flowing through the memristor, as per the formu- speed of memristor. Accordingly, the output voltage is
la Paverage = average (∆U tran × Itran ) . Then, we summed first briefly reduced to lower voltage level, and then re-
up the power consumption for each module. As a result, turns to a high voltage level as the transistor is com-
the power consumption values are as follows: XNOR1: pletely turned off.

A A A
1.8 1.8 1.8
V (V)

V (V)

V (V)
0.9 0.9 0.9

0 0 0
B B B
1.8 1.8 1.8
V (V)

V (V)

V (V)

0.9 0.9 0.9

0 0 0
XNOR1 XNOR2 XOR
1.8 1.8 1.8
V (V)

V (V)

V (V)

0.9 0.9 0.9

0 0 0
0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8
Time (ms) Time (ms) Time (ms)
(a) (b) (c)

Figure 3 The simulation waveforms of (a) XNOR1 gate; (b) XNOR2 gate and (c) XOR gate.

IV. Combinational Logic Circuit Based on 1. Numerical comparator based on

XNOR1/XNOR2/XOR Design XNOR1/XNOR2 design
In digital circuits, two binary inputs ( A, B ) are usu-
Combinational logic circuits are one of the key com-
ally compared to determine their output. A circuit with
ponents to realize any digital logic circuits. Among them,
this logic function is called a numerical comparator. The
adder and numerical comparator play a key role in com-
expression of input and output for a 1-bit numeric com-
binational logic circuits [32]. In this section, we designed parator is
a memristor-based logic circuit using XNOR and XOR
gates proposed in Section III. Two kinds of 1-bit numeri- Y0 (A > B) = AB (5)
cal comparators based on XNOR1 and XNOR2 gates
have been designed respectively. We further extended to Y1 (A = B) = AB + AB (6)
2-bit numerical comparators on the basis of the designed
1-bit numerical comparators. In addition, we designed a Y2 (A < B) = AB (7)
2-bit full adder using XOR logic gate. Through (6), it is noticed that when A = B , the
Realization of Complete Boolean Logic and Combinational Logic Functionalities on a Memristor-Based... 1141

output logic is consistent with the logic expressed by (a)

A ⊙ B . Therefore, based on the XNOR1/XNOR2 pro- A1 Y0 (A>B)
posed in Section III, two kinds of 1-bit numerical com-
B1
parators were built, as shown in Figure 4.
Y1 (A<B)
(a) (b)
Y0 (A>B) Y0 (A>B)

A A A0 Y2 (A=B)
Y1 (A=B) Y1 (A=B)
B B0
B
Y2 (A<B) Y2 (A<B)

Figure 4 (a) 1-bit numerical comparator built by XNOR1 gate;

(b) 1-bit numerical comparator built by XNOR2 gate. (b)
Y0 (A>B)
A1
Similarly, a 2-bit numerical comparator that can
B1
compare 2-bit binary numbers has two 2-bit inputs, i.e.,
A1 A0 and B1 B0 , respectively. The truth table is shown Y1 (A<B)
in Table 3, and the logic expression is as follows:

Y0 (A > B) = A1 B1 (A1 ⊙ B1 ) A0 B0 (8) A0 Y2 (A=B)

B0
Y1 (A > B) = A1 B1 + (A1 ⊙ B1 ) A0 B0 (9)

Y2 (A = B) = (A1 ⊙ B1 )(A0 ⊙ B0 ) (10)

Figure 5 (a) 2-bit numerical comparator built using XNOR1 gate;
(b) 2-bit numerical comparator built using XNOR2 gate.
Table 3 2-bit numeric comparator truth table
tion III, as shown in Figure 6. Compared with the full
Input Output
adder made by CMOS process [34], a full adder circuit
A1 B1 A0 B0 Y0 (A > B) Y1 (A < B) Y2 (A = B)
(named as full adder 1) proposed in this section uses on-
A1 > B 1 Random 1 0 0 ly 10 memristors, 16 transistors and 2 resistors to realize
A1 < B 1 Random 0 1 0 the function of full addition of binary numbers. There
A1 = B1 A0 > B 0 1 0 0 has been a noticeable decrease in the number of transis-
A1 = B1 A0 < B 0 0 1 0 tors used. Furthermore, we summed up the power con-
A1 = B1 A0 = B0 0 0 1
sumption for each module, and the resulting data is pre-
sented in Figure 6.
The extended 2-bit numerical comparators are illus-
trated in Figure 5. Due to the inevitable voltage division
effect of the MRL, the original signal level of the output
terminal also causes the presence of unwanted spikes, S
and thus two additional NOT gates have been added to A 7.33 μW 0.0116 μW
mitigate the output signal. Compared to traditional
CMOS logic circuits [33], both 2-bit numerical compara- B 47.27 μW 36.23 μW
tor circuits use fewer devices (only 22 memristors, 28 Ci−1
transistors and 2 resistors) and consume less power (0.135
mW for the circuit of Figure 5(a) and 0.146 mW for the 14.72 μW
Ci
1.40 μW
circuit of Figure 5(b)).
20.46 μW 6.69 μW
Full adder is a basic combinational logic circuit that
uses gate circuit to realize the addition of two binary Ptotal=134.11 μW Txor=16.74 ps; Tinv=52.52 ps; Ttotal=69.26 ps
numbers and generate the sum. It is also one of the most
popular circuits based on memristor designs. Its logical Figure 6 Full adder 1 on the basis of proposed XOR gate.
expression is as follows: When calculating circuit timing relationships, we de-
fined the delay time as the time interval between the
S = A ⊕ B ⊕ Ci−1 (11)
moments when the input and output signals transi-
Ci = AB + Ci−1 (A ⊕ B) = AB + Ci−1 (A + B) (12) tioned to their 50% states. This delay time calculation
specifically pertained to the path from Ci−1 to S , which
According to above expressions, we designed a full included the first-level XOR gate and a pair of inverters.
adder 1 combined with the XOR gate proposed in Sec- Consequently, the total delay time was the sum of the
 1142 Chinese Journal of Electronics, vol. 33, no. 5

delay times associated with these two segments. De- in Figures 7(a) and (b). Due to the voltage division, the
tailed delay time data for individual segments within this simulation waveforms of two 1-bit numerical compara-
path is provided in Figure 6. tors show a “staircase” shape when the output Y0 and Y2
2. Simulation results and analysis are at low level. However, such signal fluctuation is still
In addition, we simulated and analyzed the proposed far smaller than the defined low logic level, and would
combinational logic circuits in Section IV by Cadence not cause logic errors. Figures 7(c) and (d) show the sim-
simulation software. The simulation results show that ulation results of two 2-bit numerical comparators that
two 1-bit numerical comparators can correctly realize the can correctly realize the comparison function of 2-bit
comparison function of two 1-bit binary inputs, as shown binary numbers.

(a) (b)
A B A B
1.8 1.8
V (V)

V (V)
0.9 0.9
0 Y0 (A>B)
0 Y0 (A>B)
1.8 1.8
V (V)

V (V)
0.9 0.9
0 Y1 (A=B) 0 Y1 (A=B)
1.8 1.8
V (V)

V (V)
0.9 0.9
0 Y2 (A B) 0 Y2 (A B)
1.8 1.8
V (V)

V (V)
0.9 0.9
0 0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Time (ms) Time (ms)

(c) (d)
1.8 A1 B1 A1 B1
1.8
V (V)

V (V)

0.9 0.9
0 A0 B1 0 A0 B1
1.8 1.8
V (V)

V (V)

0.9 0.9
0 Y0 (A>B)
0
1.8 1.8 Y0 (A>B)
V (V)

V (V)

0.9 0.9
0 Y1 (A B)
0 Y1 (A B)
1.8 1.8
V (V)

V (V)

0.9 0.9
0 Y2 (A B)
0
1.8 1.8 Y2 (A B)
V (V)

V (V)

0.9 0.9
0 0
0 2 4 6 8 10 12 14 16 0 2 4 6 8 10 12 14 16
Time (ms) Time (ms)

Figure 7 Simulation results of 1-bit numerical comparators built by (a) XNOR1 gate and (b) XNOR2 gate; Simulation results of 2-bit nu-
merical comparators designed by (c) XNOR1 gate and (d) XNOR2 gate.

We further calculated the power consumption of the signed in this section exhibits lower power consumption
2-bit numerical comparators by solving the formula of and delay, as shown in the table of next section.
average circuit power consumption Paverage = Presistance +
Ptransistor +Pmemristor , and obtained the power consumption
V. Memristor-Based Universal Logic
of 0.135 mW for the circuit of Figure 5(a) and 0.146 mW Circuit
for the circuit of Figure 5(b). At present, the proposed digital circuits based on
Figure 8 shows the simulation waveform of full memristors can only achieve one or two logic functions
adder 1 designed in this section. The output sum bit S [36]–[38]. Realization of more logic functions usually re-
and the carry bit Ci are in the correct logical relation- quires more devices and circuit modules, which con-
ship, realizing the function of a full adder. Compared to sumes more energy. Therefore, in this section we pro-
the MRL-based 1-bit full adder [35], the full adder 1 de- pose a universal logic circuit that can realize four differ-
Realization of Complete Boolean Logic and Combinational Logic Functionalities on a Memristor-Based... 1143

1.8 A VTH ; the transistor T1 is thus in the on state, Y3 = “0”;

iii) when A = “0”, B = “1”, then Y1 = “1”, Y2 = “0” is
V (V)

0.9
similar to ii), causing Y3 = “0”; iv) when A = B = “1”,
0
1.8 B Y1 = Y2 = “1”, and VGS ≈ “0” < VTH . T1 in this case is
turned off, and Y3 = “1”.
V (V)

0.9
0 Similarly, above design also endows the output Y4
1.8 Ci–1 with XOR function (green frame): i) when A = B = “0”,
Y1 = Y2 = “0”, and VGS ≈ “0” < VTH ; the transistor T2 is
V (V)

0.9
0 therefore in the off state, driving Y4 = “0”; ii) when A =
1.8 S
“1”, B = “0”, Y1 = “1”, and Y2 = “0”, while VGS ≈ “0” <
V (V)

0.9 VTH . Accordingly, the transistor T2 is cut off, making

0 Y3 = “1”; iii) when A = “0”, B = “1”, the output case is
1.8 Ci
the same as ii), Y3 = “1”; iv) when A = B = “1”, Y1 =
V (V)

0.9 Y2 = “1”, and VGS ≈ “1” > VTH ; the transistor T2 is thus
0 turned on, making Y3 = “0”.
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
The simulation waveform of this universal logic cir-
Time (ms)
cuit is shown in Figure 10. As can be clearly seen from
Figure 8 The simulation waveform of full adder 1 built by XOR gate. Figure 10, the waveform shows the correct logic relation-
ent kinds of logic outputs (AND, OR, XOR, XNOR) at ship. Our universal logic circuit enables multiple logic
functions secured in the same circuit structure, which
the same time. Such designed circuit enables much high-
significantly improves the integrated density of the logic
er integration density and much lower power consump-
circuit and reduces the power consumption. Furthermore,
tion than previously reported counterparts, as shown in
we constructed another full adder circuit (named as full
Figure 9.
adder 2) using XOR function of the universal logic cir-
Vcc
cuit (the green frame part), as shown in Figure 11, and
its simulation waveform is given in Figure 12.
R1 A
1.8
V (V) V (V) V (V) V (V) V (V) V (V)

Y3 0.9
XNOR
0
1.8 B
T1 0.9
M1 Y1 Y2 0
AND AND
1.8
OR
A Y1 0.9
M2 0
R2 1.8 OR
B Y4 0.9
XOR 0 XNOR
1.8
M3 T2 0.9
Y2
0 XOR
1.8
M4 0.9
GND 0
0 0.4 0.8 1.2 1.6 2.0 2.4 2.8
Figure 9 A memristor based universal logic circuit. Time (ms)

The working principle of this universal logic circuit Figure 10 The simulation waveform of the general logic circuit.
is described below. After inputting signals to terminal A
and terminal B, M1 and M2 first realize the function of
OR, and M3 and M4 realize the function of AND. Then A
the OR signal is input to the gate terminal of the T1 B S
3.34 μW 1.26 μW
transistor and the source terminal of the T2 transistor
respectively, whereas the AND signal is input to the 51.34 μW 42.57 μW
source terminal of the T1 transistor and the gate termi- Ci−1
nal of the T2 transistor respectively. Such connections Ci
15.99 μW 1.59 μW
assign the output Y3 with XNOR function (red frame): i)
5.69 μW
when A = B = “0”, Y1 = Y2 = “0”, and VGS ≈ “0” < VTH ( VTH
Ptotal=121.78 μW Txor=21.06 ps; Tinv=41.49 ps; Ttotal=62.55 ps
is the threshold voltage of the transistor); the transistor
T1 is therefore in the off state, making Y3 = “1”; ii) when Figure 11 A full adder 2 using XOR function of the universal logic
A = “1”, B = “0”, then Y1 = “1”, Y2 = “0”, and VGS ≈ “1” > circuit.
 1144 Chinese Journal of Electronics, vol. 33, no. 5

1.8 A adder 1 and full adder 2 proposed in this work and the
V (V)

0.9 other full adder in CMOS processes, as shown in Table 4.

0
The full adder 2 uses fewer devices and has lower delay
1.8 B than the full adder 1, whereas the full adder 1 consumes
V (V)

0.9 less power than the full adder 2. Because the amount
0 of the memristor is much smaller than the traditional
Ci−1
1.8 MOSFET transistor, two full adders proposed in this
V (V)

0.9 work have obvious advantages in terms of power con-

0
S
sumption and delay compared with CMOS-based full
1.8
adder [39]. Besides, the lower delay could be due to the
V (V)

0.9 lower boundary mobility between the doped and un-

0 doped regions of the memristor, which is much smaller
1.8 Ci
than the mobility of electron and hole in the MOS tube
V (V)

0.9
[40]. Compared to the MRL-based 1-bit full adder [35],
0
although our devices utilize more memristor cells, the
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
power consumptions of the full adder 1 and the full
Time (ms)
adder 2 are both tremendously reduced, and the delay is
Figure 12 The simulation waveform of full adder 2. reduced by 23% for the full adder 1 and 30.4% for the
Moreover, we compared the performances of the full full adder 2 respectively.

Table 4 Comparison of full adder parameters

Parameter CMOS-based 1-bit full adder [39] MRL-based 1-bit full adder [35] Full adder 1 Full adder 2
Number of devices 28 22 28 26
Power consumption (mW) 37.18 6.2 0.134 0.122
Delay (ps) 224 90 69.3 62.6

VI. Conclusion Program of China (Grant No. 2018YFB2202005), the Nat-

ural Science Foundation of Jiangsu Province (Grant Nos.
In conclusion, we leverage the computational princi- BK20211273 and BZ2021031), the Nanjing University of
ples of MRL to harness the unique advantages offered by Posts and Telecommunications (Grant No. NY220112),
memristors as fundamental computational logic elements, and the Foundation of Jiangxi Science and Technology
and thus three basic logic gates XNOR1, XNOR2 and
Department (Grant No. 20202ACBL21200).
XOR are firstly designed. Subsequently, some combinato-
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 1146 Chinese Journal of Electronics, vol. 33, no. 5
Xiaojuan LIAN received the B.S. degree in rated Circuit Science and Engineering, Nanjing University of
electronic science and technology and the M.S. Posts and Telecommunications, Nanjing, China. His current re-
degree in physical electronics from Xidian search interests are the design, fabrication and modeling of
University, Xi’an, China, in 2008 and 2011 re- electronic devices and systems for neuromorphic computation.
spectively. She received the Ph.D. degree in
electrical engineering from the Universitat Xiaoyan LIU received the Ph.D. degree in mi-
Autònoma de Barcelona, Spain, in 2014. She croelectronics and solid-sate electronics from
is currently an Associate Professor at the Col- Fudan University, Shanghai, China, in 2019.
lege of Integrated Circuit Science and Engin- She is currently an Associate Professor with
eering, Nanjing University of Posts and Telecommunications, Nanjing University of Posts and Telecommu-
Nanjing, China. Her research interests include memristive nications, Nanjing, China, working on the re-
devices (RRAM, PCRAM and so on), information storage tech- searches mainly including the micro-LED ar-
nology, and neuromorphic computing applications. ray devices for visible light communication in
(Email: [email protected]) free-space and underwater, memeristive devices
for neuromorphic computing and artificial synapse.
Chuanyang SUN received the B.E. degree in
electronic information engineering from the Zhikuang CAI received the B.S. degree in in-
Bengbu College, Bengbu, China, in 2021. He formation engineering from Nanjing Univer-
currently pursuing for the M.S. degree with sity of Posts and Telecommunications, Nanjing,
Nanjing University of Posts and Telecommu- China, in 2005, and the Ph.D. degree from
nications, Nanjing, China, engaged in the re- ASIC System Center at Southeast University,
search of memory-computing integration based Nanjing, China, in 2014. He is currently a
on memristor. Professor at the College of Integrated Circuit
Science and Engineering, Nanjing University
of Posts and Telecommunications, Nanjing,
Zeheng TAO received the B.E. degree in elec-
China. His research interests include low power SoC design and
tronic science and technology from Hunan
test, and chiplet package and test.
University of Technology, Zhuzhou, China, in
2021. He is currently working towards the
Lei WANG received the B.S. degree in elec-
M.S. degree at Nanjing University of Posts
trical engineering from Beijing University of
and Telecommunications, Nanjing, China, fo-
Science and Technology, Beijing, China, in
cusing on research related to the integration of
2003, the M.S. degree in electronic instrumen-
memory and computing using memristors.
tation systems from University of Manchester,
Manchester, UK, in 2004, and the Ph.D. de-
gree in 2009 at University of Exeter, Exeter,
Xiang WAN received the B.S. degree in ap-
UK. Between 2008 and 2011, he was employed
plied physics and the M.S. degree in materi-
as a Postdoctoral Research Fellow with Uni-
als engineering from University of Science and
Technology of China, Chengdu, China, in 2011 versity of Exeter, Exeter, UK, to work on a fellowship funded by
and 2014 respectively. He received the Ph.D. European Commission. In 2020, he joined Nanjing University
degree in electronic science and technology of Posts and Telecommunications, Nanjing, China, as a Full
from Nanjing University, Nanjing, China, in Professor. His research interests include phase-change memories,
2017. From 2019 to 2021, he held the Postdoc neural networks, and other phase-change based optoelectronic
Position at the National Institute for Materi- devices and their potential applications.
als Science. He is currently a Lecturer at the College of Integ- (Email: [email protected])