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3 views

vlsi-B

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Introduction:

In advanced VLSI design, pseudorandom number generation plays a critical role in various
applications such as built-in self-test (BIST), digital signal processing, and cryptography. A 64-
bit Linear Feedback Shift Register (LFSR) is a vital digital circuit for generating pseudorandom
binary sequences, making it indispensable in numerous AVLSI systems.
A Linear Feedback Shift Register (LFSR) is composed of a shift register and feedback logic. By
shifting the contents of the shift register and applying a linear combination of its values
through the feedback logic, the LFSR produces pseudorandom binary sequences. Specifically,
a 64-bit LFSR consists of a 64-bit shift register and associated feedback logic. The feedback
logic calculates a linear combination of the register's contents, which is then reintroduced into
the shift register. This configuration allows the 64-bit LFSR to generate pseudorandom binary
sequences with a maximum length of 264−12^{64} - 1264−1.
Applications of a 64-bit LFSR:
• Built-in Self-Test (BIST): Used to create pseudorandom test patterns for hardware
testing.
• Digital Signal Processing (DSP): Applied in noise generation and modulation tasks.
• Cryptography: Utilized in stream ciphers, hash functions, and other cryptographic
systems.
Advantages of a 64-bit LFSR:
• High-speed pseudorandom number generation: Capable of producing pseudorandom
sequences rapidly.
• Low area overhead: Achieves efficient implementation with minimal hardware
requirements.
• Improved randomness: Generates sequences with superior statistical properties.
Software Used: The Cadence Tool

Verilog code:

module lfsr_64 (
input clk,
input rst,
output [63:0] lfsr_out
);
reg [63:0] lfsr_reg;
wire [63:0] lfsr_next;
assign lfsr_next = (lfsr_reg >> 1) ^ (lfsr_reg[0] ? {lfsr_reg[62:0], 1'b0} : {lfsr_reg[62:0], 1'b1});
always @(posedge clk or posedge rst) begin
if (rst) begin
lfsr_reg <= 64'hFFFFFFFFFFFFFFFF;
end else begin
lfsr_reg <= lfsr_next;
end
end
assign lfsr_out = lfsr_reg;
endmodule
Test bench:

module tb_lfsr_64;
reg clk;
reg rst;
wire [63:0] lfsr_out;
lfsr_64 dut (
.clk(clk),
.rst(rst),
.lfsr_out(lfsr_out)
);
initial begin
clk = 0;
rst = 1;
#10 rst = 0;
end
always #10 clk = ~clk;
initial begin
$monitor("lfsr_out = %h", lfsr_out);
#1000 $finish;
end
endmodule

Simulation: Waveform Results of 64-bit LFSR Using Cadence Tool

Synthesis: Synthesis Result of 64-bit LFSR using Cadence Tool


Truth table

Conclusion:

The 64-bit Linear Feedback Shift Register (LFSR) implemented in Verilog effectively generates
pseudorandom binary sequences using a Galois configuration and a non-zero seed value for
initialization. Its 64-bit width makes it well-suited for diverse applications such as random
number generation, cryptography, and digital signal processing. The design offers flexibility for
optimization in terms of area, speed, and power consumption and can be scaled to meet
varying application requirements, establishing it as a versatile and efficient digital circuit
solution.

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