Last Updated: January 2024

Course Code: CSE 411 CIE Marks: 60

Course Title: Computer Architecture and Organization SEE Marks: 40
Credit: 3 Weekly: 2.5 Hours Total Week: 16

Course Content (from syllabus):

Introduction to computer architecture & organization, Difference between architecture &
organization, High-level structures & functions of computers, Evolution of computers
Performance evaluation of computing systems, Designing of Computing System, Design
methodology, structure Vs Behavior, Different design levels, sequential and combinational
circuits, Data representation, combinational logic design, Processor basics: basic CPU design,
Instruction set design, addressing modes, Data-path Design: The Arithmetic and Logic Unit:
Integer representation & arithmetic, floating-point representation & arithmetic, Coprocessor,
Pipeline processing, Basic structure, Hazards, Branch Prediction, Cache memory overview,
Cache mapping, multilevel Cache, unified/split cache, Virtual memory, mapping process,
Paging, Demand Paging, Page table, Advantages/ Disadvantages.

Course Description/Rationale:
The computer lies at the heart of computing. Without it most of the computing today would be a
branch of theoretical mathematics. To be a professional in any field of computing today, one
should not regard the computer as just a black box that executes programs by magic. All students
of computing should acquire some understanding and appreciation of a computer system’s
functional components, their characteristics, their performance, and their interactions. This
course can help the students in this regard.

Course objective:
 To learn the basic concepts of architecture & organization.
 To learn the performance evaluation of computing systems.
 To learn about the designing of Computing System.
 To learn about sequential and combinational circuit design.
 To learn the basic of CPU, instruction set, addressing modes, and Data-path design.
 To learn about pipeline processing and different types of hazards.
 To learn details about case and virtual memory mapping.
 To understand how computers are constructed out of a set of functional units
 To understand how these functional units operate, interact and communicate
 To understand the factors and trade-offs that affect computer performance
 To understand concrete representation of data at the machine level
 To understand how computations are actually performed at the machine level
 To understand how problems expressed by humans are expressed as binary strings in a
machine
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Course Learning Outcome (CO): (at the end of the course, students will be able to:)
CO1 Define the functional components in processor design, register sets, instruction
codes and execution, addressing modes, basic Verilog (HDL) and working of
Arithmetic and Logic Unit
CO2 Relate the knowledge of cache, virtual and main memory, I/O operations, bus
controls, I/O interrupts and interfaces, I/O devices and characteristics on the
design of a typical computer system
CO3 Apply the factors in the processor design to achieve performance in single
and multiprocessing systems and interpret the performance of different
pipelined processors.
CO4 Analyze combinational and sequential circuit design of ALU to get better
performance and power consumption

Content of the course:

Week Course Content (as summary) Hrs COs
Introduction to Computer Architecture and Organization.
Also elements of computer. Applications of Digital Logic
1 Circuits for architecture. Brief discussion of Computer 2.5 CO1
Generations on different Electrical Circuits and Components

Processor Level, Gate Level and Register level design

discussion in brief. Combinational and sequential circuit
2 2.5 CO1
discussion using different Logic gates.

Simplify the circuit discussion using Boolean Algebra (SOP,

3 POS) and K-Map. Discussion of binary operations: Addition, 2.5 CO1
Multiplication, Subtraction and Division.

Arithmetic Logic Implementation (Addition, Subtraction)

using open-source simulators using open-source simulators
4 2.5 CO1, CO3, CO4
(GHDL, DHCS, GEM5, etc.) by VHDL code.

Arithmetic Logic Implementation (Multiplication, Division)

using open-source simulators using open-source simulators
5 2.5 CO1, CO3, CO4
(GHDL, DHCS, GEM5, etc.) by VHDL code.

Half Adder, Full Adder, Half Sub Tractor, and Full Sub
Tractor Implementation Using Multiplexer and De-
6 Multiplexer for ALU Design using open-source simulators 2.5 CO1, CO3, CO4
(GHDL, DHCS, GEM5, etc.) by VHDL code.
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1-bit and 4-bit implementations using open-source simulators

7 (GHDL, DHCS, GEM5, etc.) by VHDL code. 2.5 CO1, CO3, CO4

Data-path Designing: The Arithmetic and Logic Unit: Integer

representation & arithmetic floating-point representation &
8 2.5 CO2, CO3
discussion of Coprocessor.

Addressing modes, Data Transfer and manipulations.

9 Introduction to RISC and CISC Architecture, Asynchronous 2.5 CO2, CO3
data transfer, Modes of Transfer and RISC, CISC.

Introduction to Instruction Pipelining. Different stage of

10 pipelines. Different Pipeline hazards using diagrams. Data, 2.5 CO2, CO3
Resource and control Hazards.

Measures against pipeline hazards, Pipelining strategy,

11 performance. Memory hierarchy. and introduction to cache 2.5 CO2, CO3
memory
Cache addressing and cache mapping functions. Direct
12 memory addressing or cache mapping functions 2.5 CO2, CO3

Associative and Set-Associative memory addressing or cache

13 mapping functions. 2.5 CO2, CO3

Introduction to Virtual memory and memory mapping

14 2.5 CO2, CO3
technique.
15 Demand Paging, Page table, Advantages/ Disadvantages. 2.5 CO2, CO3

16 Review class for Final Examination 2.5 CO2, CO3

Total 40

Mapping of Course Learning Outcomes to Program Learning Outcomes:

CO’s/PO’s PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1
CO2
CO3
CO4

PO Descriptions
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PO1 Engineering knowledge: Apply knowledge of mathematics, natural science, engineering

fundamentals and an engineering specialization as specified in K1 to K4 respectively to
the solution of complex engineering problems.
PO2 Problem analysis: Identify, formulate, research literature and analyses complex
engineering problems reaching substantiated conclusions using first principles of
mathematics, natural sciences and engineering sciences. (K1 to K4)
PO4 Conduct investigations of complex problems using research-based knowledge (K8) and
research methods including design of experiments, analysis and interpretation of data,
and synthesis of information to provide valid conclusions.
PO5 Modern tool usage: Create, select and apply appropriate techniques, resources, and
modern engineering and IT tools, including prediction and modelling, to complex
engineering problems, with an understanding of the limitations. (K6)

Justification: CO, PO Mapping

PO1 Engineering knowledge includes the application of foundational principles in
architectural design, which is explicitly addressed in CO1.
PO2 Understanding how to formulate cache and virtual memory mapping techniques in
problem analysis, which is explicitly addressed in CO2.
PO4 Analyzing the circuits to design ALU which needs research-based knowledge and
analysis to get better performance and power consumption, which is explicitly
addressed in CO4

PO5 CO3 involves applying architectural principles for RISC and CISC processor designs
described in Verilog HDL using modern tools. This closely aligns with PO5 (Modern
tool usage), which emphasizes the application of appropriate techniques and tools,
including programming tools, to solve complex engineering problems.

Teaching Learning Activity:

TLA Activity
Identify the basics organization of a computing system, find out the differentiate
TLA1 between the concept of architecture and organization, and can perform the evaluation
the true performance of a computer for the enhancements of computer performance.
Students will be able to understand how computer represent different types of data
and will able to learn how basic elements of a computer works with different level of
TLA2
processor design. Also learn about basic CPU design, instruction set design,
addressing modes
Realized the Arithmetic and Logic Unit, Integer representation & arithmetic,
TLA3 floating-point representation & arithmetic, Coprocessor. Also understand Pipeline
processing, Basic structure, Hazards, Branch Prediction.
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Understand the concept of cache mapping, multilevel Cache, unified/split cache.

TLA4 And realized virtual memory, mapping process, Paging, Demand Paging, Page table.

Mapping Course Learning Outcome (COs) with the Teaching-Learning and Assessment
Strategy:
Complex
Teaching Knowledge Complex
Assessment Learning Engineering
COs POs Learning Profile Engineering
Strategy Domains Problem
Activity (WK) Activity (EA)
(EP)

Quiz EP1 & EP2,

CO1 PO1 TLA1 C1 WK3 -
Midterm EP3
Quiz,
EP1 & EP2,
CO2 PO2 TLA4 Presentation C2 WK4 -
EP3
Final
Quiz, EP1 & EP3,
CO3 PO5 TLA3 C3 WK8 -
Final EP5
Quiz EP1 & EP2,
CO4 PO4 TLA2 C4 WK6 -
Midterm EP5

Justification: PO and Learning Domains Mapping

PO1 Remembering (Recalling information from memory)
PO2 Understanding (Comprehending the meaning of information)
PO4 Analyzing (Breaking down complex information and examining relationships)
PO5 Applying (Using learned information in new situations or contexts)

Justification: PO and Knowledge Profile (WK) Mapping

PO1 PO1 the systematic formulation of engineering fundamentals, which includes knowledge of computer
architecture and its application (WK3).
PO2 PO2 requires the specialist knowledge that provides theoretical frameworks and bodies of knowledge for
computer memory organization (WK4).
PO4 PO4 involves the Engagement with selected knowledge in the research literature of the circuits to design
and analyze ALU to get better performance and power consumption (WK8)
PO5 PO4 involves the application of engineering technology in the practical area of engineering science to
solve problems (WK6)

Justification: PO and Complex Engineering Problem (EP) Mapping

PO1 1. EP1: Aligns with PO1 as a deep understanding is vital for addressing the complexities of circuit
designing.
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2. EP2: Addresses conflicting needs, aligning with the problem-solving nature of engineering
knowledge.
3. EP3: Reflects the need for a profound analysis, harmonizing with the analytical aspect of
engineering knowledge.
PO2 1. Effective problem analysis requires in-depth knowledge, linking with the principles emphasized in
EP1.
2. Problem analysis often involves resolving conflicting needs, aligning with EP2.
3. The need for a thorough analysis resonates with both PO2 and EP3.
PO4 1. Effective design and development require a strong foundation, aligning with the depth of knowledge
in EP1.
2. Design necessitates a thorough analysis, aligning with the principles of EP3.
3. Using codes of practice for professional engineering, aligning with EP5.
PO5 1. Effective use of modern tools requires a deep understanding, aligning with the depth of knowledge
in EP1.
2. Modern tool usage involves addressing conflicting needs, aligning with EP2.
3. Using codes of practice for professional engineering, aligning with EP5.

Course Delivery Plan/Lesson Delivery Plan:

Student Activities
during Online
and Onsite Mappin
Week/Lesson Discussion Topic and [course teacher g with Assessment
(hour) Book Reference will decide based CO and Plan
on the type of the PO
contents]

Lesson 1:
Introduction to Computer
Architecture and Brainstorming
Organization. Also, sessions,
elements of computer. Classroom
discussion, Voice
Week-1
Lesson 2: over PPT, Lecture Class Test,
Lesson 1 & 2 CO1
Applications of Digital video, Lecture Assignment,
[2.5 Hours] PO1
Logic Circuits for note, Open Midterm
architecture. Brief discussion.
discussion of Computer
Generations on different
Electrical Circuits and
Components
 Last Updated: January 2024

Lesson 3: Brainstorming
Processor Level, Gate Level sessions,
Week-2
and Register level design Classroom
Lesson 3 & 4 CO1 Class Test,
discussion in brief discussion, Voice
[2.5 Hours] PO1 Assignment,
Lesson 4: over PPT, Lecture
Midterm
Combinational and video, Lecture
sequential circuit discussion note, Open
using different Logic gates. discussion.
Lesson 5: Brainstorming
Simplify the circuit sessions,
discussion using Boolean Classroom
Week-3 Algebra (SOP, POS) and K- discussion, Voice
Lesson 5 & 6 Map. over PPT, Lecture
CO1 Class Test,
[2.5 Hours] Lesson 6: video, Lecture
PO1 Assignment,
Discussion of binary note, Open
Midterm
operations: Addition, discussion.
Multiplication, Subtraction
and Division
Lesson 7: Brainstorming
Arithmetic Logic sessions,
Implementation (Addition) Classroom
using open-source discussion, Voice
simulators using open- over PPT, Lecture
source simulators (GHDL, video, Lecture
DHCS, GEM5, etc.) by note, Open CO1,
Week-4
VHDL code. discussion. CO3,
Lesson 7 & 8 Class Test,
CO4,
[2.5 Hours] Assignment,
Lesson 8: PO1,
Midterm
Arithmetic Logic PO2,
Implementation ( PO4
Subtraction) using open-
source simulators using
open-source simulators
(GHDL, DHCS, GEM5,
etc.) by VHDL code.

Lesson 9: Brainstorming
Arithmetic Logic sessions, CO1,
Week-5
Implementation Classroom CO3,
Lesson 9 & Class Test,
(Multiplication) using open- discussion, Voice CO4,
10 [2.5 Assignment,
source simulators using over PPT, Lecture PO1,
Hours] Midterm
open-source simulators video, Lecture PO2,
(GHDL, DHCS, GEM5, note, Open PO4
etc.) by VHDL code. discussion.
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Lesson 10:
Arithmetic Logic
Implementation (Division)
using open-source
simulators using open-
source simulators (GHDL,
DHCS, GEM5, etc.) by
VHDL code.

Lesson 11: Brainstorming

Half Adder, Full Adder sessions,
Implementation Using Classroom
Multiplexer and De- discussion, Voice
Multiplexer for ALU over PPT, Lecture
Design using open-source video, Lecture
Week-6 simulators (GHDL, DHCS, note, Open CO1,
Lesson 11 & GEM5, etc.) by VHDL code. discussion. CO3,
Class Test,
12 [2.5 CO4,
Assignment,
Hours] Lesson 12: PO1,
Midterm
Half Sub Tractor, and Full PO2,
Sub Tractor Implementation PO4
Using Multiplexer and De-
Multiplexer for ALU
Design using open-source
simulators (GHDL, DHCS,
GEM5, etc.) by VHDL code.

Lesson 13: Brainstorming

1-bit implementations using sessions,
open-source simulators Classroom
(GHDL, DHCS, GEM5, discussion, Voice CO1,
Week-7 etc.) by VHDL code. over PPT, Lecture CO3,
Class Test,
Lesson 13 & video, Lecture CO4,
Assignment,
14 [2.5 Lesson 14: note, Open PO1,
Midterm
Hours] 4-bit implementations using discussion. PO2,
open-source simulators PO4
(GHDL, DHCS, GEM5,
etc.) by VHDL code.

Midterm Examination
Syllabus: Week 1 – Week 7
Week-8 Lesson 15: Brainstorming CO2
Lesson 15 & Data-path Designing: The sessions, PO2 Class Test,
16 [2.5 Arithmetic and Logic Unit: Classroom CO3 Assignment,
Hours] Integer representation & discussion, Voice PO5 Final
arithmetic floating-point over PPT, Lecture
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representation video, Lecture

Lesson 16: note, Open
Discussion of Coprocessor discussion.

Lesson 17: Brainstorming

Addressing modes, Data sessions,
Week-9 Transfer and manipulations. Classroom CO2
Class Test,
Lesson 17 & Introduction to RISC and discussion, Voice PO2
Assignment,
18[2.5 Hours] CISC Architecture over PPT, Lecture CO3
Presentation
Lesson 18: video, Lecture PO5
, Final
Asynchronous data transfer, note, Open
Modes of Transfer and discussion.
RISC, CISC
Lesson 19: Brainstorming
Introduction to Instruction sessions,
Week-10
Pipelining. Different stage Classroom CO2
Lesson 19 & Class Test,
of pipelines. discussion, Voice PO2
20 [2.5 Assignment,
Lesson 20: over PPT, Lecture CO3
Hours] Presentation
Discussion on different video, Lecture PO5
, Final
Pipeline hazards using note, Open
diagrams. Data, Resource discussion.
and control Hazards.
Lesson 21: Brainstorming
Week-11 Measures against pipeline sessions,
hazards, Pipelining strategy, Classroom CO2
Lesson 21 & Class Test,
performance discussion, Voice PO2
22 [2.5 Assignment,
over PPT, Lecture CO3
Hours] Lesson 22: Presentation
video, Lecture PO5
Memory hierarchy. and , Final
note, Open
introduction to cache discussion.
memory
Lesson 23: Brainstorming
Week-12 Cache addressing and cache sessions,
CO2
Lesson 23 & mapping functions. Classroom Class Test,
PO2
24 [2.5 Lesson 24: discussion, Voice Assignment,
CO3
Hours] Direct memory addressing over PPT, Lecture Presentation
PO5
or cache mapping functions video, Lecture , Final
note, Open
discussion.
Lesson 25: Brainstorming
Week-13 Associative and Set- sessions, CO2
Class Test,
Associative memory Classroom PO2
Assignment,
Lesson 25 & addressing or cache discussion, Voice CO3
Presentation
25 [2.5 mapping functions. over PPT, Lecture PO5
, Final
Hours] video, Lecture
Lesson 26: note, Open
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Associative and Set- discussion.

Associative memory
addressing or cache
mapping functions.
Lesson 27: Brainstorming
Week-14
Introduction to Virtual sessions,
CO2
memory and memory Classroom Class Test,
Lesson 27 & PO2
mapping technique. discussion, Voice Assignment,
28 [2.5 CO3
Lesson 28: over PPT, Lecture Presentation
Hours] PO5
Virtual memory and video, Lecture , Final
memory mapping technique. note, Open
discussion.
Lesson 29: Brainstorming
Demand Paging, Page table, sessions,
Week-15 Advantages/ Disadvantages. Classroom CO2
Class Test,
discussion, Voice PO2
Assignment,
Lesson 29 & Lesson 30: over PPT, Lecture CO3
Presentation
30 [2.5 Demand Paging, Page table, video, Lecture PO5
, Final
Hours] Advantages/ Disadvantages. note, Open
discussion.

Lesson 31: Brainstorming

Week-16 Review Class – 1: for sessions,
preparing for the final exam Classroom CO2 Class Test,
Lesson 31 & discussion, Voice PO2 Assignment,
32 [2.5 Lesson 32: over PPT, Lecture CO3 Presentation
Hours] Review Class – 2: for video, Lecture PO5 , Final
preparing for the final exam note, Open
discussion.
Final Examination
Syllabus: Week 8 – Week 16

Assessment Pattern:
Mark
CO’s
Assessment Task (Total=100)
CO1 CO2 CO3 CO4
Attendance -- -- -- -- 7
Class Test -- -- -- -- 15
Assignment -- -- -- -- 5
Presentation -- -- -- -- 8
Midterm Examination 5 5 5 10 25
Final Examination 5 10 10 15 40
 Last Updated: January 2024

Total Marks 10 15 15 25 100

CIE – Breakup [60 marks]

Bloom’s Attendance Class Assignment Presentation Mid Exam
Criteria (07) Test (05) (08) (25)
(15)
Remember 02 2.5
Understand 05 02 02 7.5
Apply 05 03 12.5
Analyze 03 03 03 2.5
Evaluate
Create

SEE – Semester End Examination [40 marks]

Bloom Criteria Score for the Test
Remember 5
Understand 10
Apply 20
Analyze 5
Evaluate
Create

Learning Materials:
Textbook/Recommended Readings:
1. Computer Architecture and Organization, Author: John P. Hayes, Third edition
2. COMPUTER ORGANIZATION AND ARCHITECTURE, University of Mumbai
3. Computer Organization and Architecture, Author: William Stallings, 9th edition

Reference Books/Supplementary Readings:

1. Online materials
2. Online resources using Google search engine, YouTube, etc.

Other Readings:
1. Powerpoint Lecture Slide Prepared by course teacher