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Unit V

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Unit V

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sridevi ramaraj
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The use of other macrooperation system, and can be used to d to check its intended operation. The internal is best described by a set of control functions and st that describe the organiza. from which the system i i ter The set of instructions for a given compu! when defined with macrooperation i init ambiguity. cisely and with a minimum of a eas organization of a digital system | microoperations. The list of register-trans! tion of the system can be used to derive th can be designed. | | The next section shows by example how the register-transfer method is used in each of the four tasks listed above. This is done by defining and designing a very simple computer. 8-12 DESIGN OF A SIMPLE COMPUTER The block diagram of a simple computer is shown in Fig. 8-14. The system consists of a memory unit, seven registers, and two decoders. The memory unit has 256 words of 8 bits each, which is very small for a real computer, but sufficient for demonstrating the basic operations found in most computers. Instructions and data are stored in the memory unit, but all information processing is done in the registers. The registers are listed in Table 8-4, together with a brief description of their function and the number of bits they contain. The memory address register, MAR, holds the address for the memory. The memory buffer register, MBR, holds the contents of the memory word read from or written into memory. Registers A and R are general-purpose processor registers. The program counter PC, the instruction register JR, and the timing counter T are part of the control unit. The /R receives the operation code of instructions. The decoder associated with this register supplies one output for each operation code encountered. Thus q, = 1 if the operation code is binary 1, q, = 1 if the operation code is binary 2, and so on. The T counter is also decoded to supply eight timing variables, to through t (see Section 7-6). This counter is increment rh . ry clock pulse, but it can be cleared at any time to start a new sequence coaplie FE ge ough # serbysep counting sequence and nue Siumbuter to read successive instructions previously stored in memory. The PC ¢ address of the next instruction in memory. To read an instruc~ Scanned with CamScanner 256 wordo Memory unit & pith, 2oct— 25608 DB remedy SY 2) Seven augis B Tuc clecoe Figure 8-14 Block diagram of a simple computer tion, the contents of PC are transferred into MAR and a memory-read cycle is initiated. The PC is then incremented by | so it holds the next address in the Sequence of instructions. An operation code read from memory into MBR is then transferred into /R. If the memory-address part of an instruction is read into MBR, this address is transferred into MAR to read the operand. Thus, MAR can receive addresses either from PC or from MBR. Tame 8-4 List of registers for the simple computer Number Symbol of bits Name of register Funetion MAR 8 Memory address register Holds address for memory MBR @ Memory bufler register Holds contents of memory word A 8 A sepster Processor register R 8 R reister Processor register °C 8 1m counter Molds address of instruction IR 8 register Holds current operation code r 3 Timing counter quence generat 345 ~ ~ Scanned with CamScanner ee instructions for a simple computer tions f¢ r Tame 85 Thr Description Function Operation code Mnemonic . _— 00000 Move Rio A ack eon mov 5 Load OPRD into A . iA potty tps DRS Load operand specified by 4 TADRS] eA "ADRS into A i fous section are specified again in tructions defined in the previot re spi ae eee naire ae eight bits in the operation code, it is possible to specify op ose aiferent operat entation, we consider here only i implify the pres 3 r ifferent operations. To simplify the pr¢ i weaves sted instructions ‘The mnemonic associated with each instruction can be ; i ith symbolic names, used by programmers to specify the instructions with symbolic | The y ding binary operation code and sym. mnemonic MOV stands for the corresponding bin ‘OV indicates th bolizes a “move” instruction, The R symbol following the MOV indicates that the contents of R are moved to register A. The mnemonic LDI symbolizes a “load immediate” instruction. The OPRD following LDI stands for an actual operand that the programmer must specify with this instruction. LDA is an abbreviation for “load into A,” and the ADRS following it stands for an address number that the Programmer must specify with this instruction. The actual OPRD and ADRS values, together with their corresponding operation codes, will be stored in memory asin Fig. &-13, ____ Table 8-5 gives a word description for each instruction. This word descrip- tion is not precise. The statements listed under the function column give a concise and precise definition of each instruction. A computer with only three instructions is not very useful. We must assume that this computer has many more instructions, even though only three of them are considered here. A program written for the computer is stored in memory. This program consis af many instructions, but once in a while the instruction used will OF she three listed. We now consider the internal operations needed ‘0 execute the instructions that are stored in memory. Instruction Fetch Cycle Program counter PC must be i conta sored in memory. When a “att” swig ae Me follows a basic pattern, An operation vode memory into MBR. The PC is i i Im sequence, The operation co t t address of the program f tivated, the computer sequent we Whose address is in PC is read from Me gad By Vo prepare it for the next addieS This sequent erred from MBR tw IR, where it § ion code from memory led the instruction fetch cycle, sinc? it fy th, and 1 FY and places it in a control register. TH 2 Out of the timing decoder are used as cont! ‘nce the microoperations = Perations for reading an operation code (op-cot# | Scanned with CamScanner : / / 1 1 7 5 , Searser*.* a SEC. 8-12 DESIGN OF ASIMPLE COMPUTER 347 and placing it into JR: tg: MAR & PC transfer op-code address 4: MBROM,PC—PC +1 read op-code, IR— MBR transfer op-code to IR srement PC oa It is assumed that the timing counter, 7, starts from a value 000 which produces a f, timing variable out of the decoder. The T register is incremented with every clock pulse and automatically produces the next timing variable in sequence. The first three timing variables execute the microoperation sequence which may be symbolized with the macrooperation statement: IREM[PC), PCH PC +1 This states that the memory word specified by the address in PC is transferred into IR and then the PC is incremented. The hardware constraint in the simple computer is that only MAR and MBR can communicate with the memory. Since PC and JR cannot communicate directly with the memory, the above macroopera- tion must be executed with a sequence of three microoperations. Another hard- ware constraint is that the PC cannot be incremented while its value is being used to supply the address for a memory read. Only after the read operation is completed can the PC be incremented. By transferring the contents of PC into MAR, the PC can be incremented while the memory reads the word addressed by MAR. ‘The fetch cycle is common to all instructions. The microoperations and control functions that follow the fetch cycle are determined in the control section from the decoded operation code. This is available from outputs q, i = 1, 2, 3,.. + in the operation decoder. Execution of Instructions During timing variable f, the operation code is in JR and one output of the operation decoder is equal to I. The contro! uses the g, variables to determine the next microoperations in sequence. The MOV R instruction has an operation code that makes q, = 1. The execution of this instruction requires the microoperation: qs: AOR THO Thus, when q, = 1 at time 4s, the contents of R are transferred into register and the timing register Tis cleared. By clearing 7, control goes back to produce timing variable f and thus starts the fetch cycle again to read the operation code of the next instruction in sequence. Remember that PC was incremented during time ,, so now it holds the address of the next instruction in sequence. Tor aT AA Scanned with CamScanner CHa oaic 348 REGISTER-TRANSFER L ration code that makes 4, = 1, Thy The LDI OPRD instruction has an ore microoperations that execute this instructio! transfer operand address mat MARS ead operand, increment PC tg MBRAM, PCH PC +1 rea an ’ transfer operand, go to fetch cycle. Gols) A MBR, THO = id the The three timing variables that follow the fei gee while ta ai rea a he oped from memory and transfer it into register A. Sint location Tollowing the operation code, it is read from oe one addres specified in PC. The operand read into MBR is then trans red to A. Note that PC is incremented once again to prepare it for the address of the next operation code before going back to the fetch cycle. , ‘The LOA ADRS instruction has an operation code that makes 9 = I. The microoperations needed to execute this instruction are listed below: sty: MAR — PC transfer next instruction address MBR<—M,PC~— PC +1 __ read ADRS, increment PC she: Qyts:, MAR — MBR transfer operand address slg), MBR—M read operand Gly) A— MBR, THO transfer operand to A, go to fetch cycle The address of the operand, symbolized by ADRS, is placed in memory right after the operation code. Since PC was incremented at 1, during the fetch cycle, it now holds the address where ADRS is stored. The value of ADRS is read from memory at time 44. PC is incremented at this time to prepare it for the fetch cycle of the next instruction. At time fs, the value of ADRS is transferred from MBR 0 MAR. Since ADRS specifies the address of the operand, a memory read during time 4, causes the operand to be placed in MBR. The operand from MBR is transferred to register A and control goes back to the fetch eycle. The contro! functions and microoperations for the simple computer att summarized in Table 8-6, The first three timing variables constitute the fetch cy—1) Figure 615 Implementation of xj: MAR PC i + between the ion i lean function. The ta control function is a Boole Conal ovetiané denotes ‘a Boolean OR operation, and the he ab of Gn operator between g; and f, denotes a Boolean AND operation. t combines all the control conditions for the transfer from be into ae Te hardware implementation of the above statement is depicted in Fig. 8-15. The control function can be manipulated as a Boolean function to give: fo + ats + ats = to + (G2 + Ids 4 The binary variable x, is applied to the load input of MAR and the outputs from PC are applied to the inputs of MAR. When x, = 1, the next clock pulse transfers the contents of PC into MAR. The binary variables that cause x, to be a | come from the operation and timing decoders in the control unit. There are cight different microoperations listed in Table 8-6. For each distinct microoperation, we accumulate the associated control functions and OR them together. The result is as shown in Table 8-7. The combined control func- tions obtained for each microoperation are equated to a binary variable x, i=1,2,...,8. The eight x variables can be easily generated with AND and OR gates, and will not be done here, tn ute design of the simple computer can be now obtained from the register ne Hoewe aon sven ponble 7. The block diagram design is shown in Fig In addition. there 1 ey weisters, the memory unit, and two decoders 7 dition, there is a box labeled “combinational it.” i |. circuit block generates the eight control functions, xv, mene, The combinations ‘unctions, x, through x4, according to the ‘Tante8-7 Hardware specification for a simple computer a : of th + at: MAR & PC Sai ays aug HRS abe 2 ae. ne MBRAM a as armen ne a te Teo IR MBR 350 oR Scanned with CamScanner Nigse 616 Denga of « wmple computer 3st canned with CamScanner CH. REGISTER-TRANSFER LOGIC soe I functions enable the load ang A register that receives information from two. For example, 4p between the (we y fuiplexer to select hetwe Wliplexer associated 4 ee svonaaton trom Af oe from PC. The mul (x, 7 1) but tranger Maki mor the contents of PC when its select Up yecaine x, 7 Owhen x, = | themes cf BR nen he pee ine hat racontents of MBR go through at stintes the load input of MAR so that | ith every clock wee soulhteretenta MAR. Timing counter 7 is incremented wi ry Pulse; however, when x; = I, itis cleared to zero. 1, Fig. 816.ean be des ae The i \s specified in Fig. igned The eer a te dig funtion speci i Fi #16 can be dee Jividually by means of combinational and seq} pytem eam e can readily find commercial Ms tem contac ih nerd ici one can realy find commercial MS rcuits for all registers and digital functions. | control can be constructed with SSI gates, In a large computer, this part would be more efficiently implemented with a programmable logic array. control list of control funetions in the tables The of contre ! a increment inputs of the various regis REFERENCES 1 Mano, M.M.. Computer System Architecture, Englewood Cliffs, N.J.: Prentice-Hall, Inc, 1976, 2 Cine. Y= Computer Organization and Microprogramming. Englewood Cliffs, NJ: Prex tuce-Hall, Inc, 1972. 3. Dretmever, D, Lopical Design of Digital ‘Systems. Boston, Mass.: Allyn and Bacon, |97). 4 Bell CG. and A. Newell, Computer Structures: Readi sand Examples. New York: McGraw-Hill Book Co, 1971, ms “vee 3. Hull, F., and G. Peterson, Digital Systems: Hardwar rganizatic York: John Wiley & Sons, 1973, ” " =2 tion and Design. New 6 Banee, TC... L Lebow, and 1. § Reed, Th York McGraw-Hill Book Co, 1962 g x z EB PROBLEMS ©1 Show the block Magram that erccutes the statement ar bz ne A constant vatue A can be transferred tw 4 , ‘eral equivateat wy logic} OF lowe.0. spares! bY applying to each input a binary Show the implementation of the transfer: 1 4~ nowt Scanned with CamScanner

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