UNIT 5

LOGIC FAMILY:

∙ A group of compatible ICs with the same logic levels and supply voltages for performing
various logic functions have been fabricated using a specific circuit configuration which
is referred to as a logic family.

 A circuit configuration or approach used to produce a type of digital integrated circuit.

 Different logic functions, when fabricated in the form of an IC with the same approach,
or in other words belonging to the same logic family, will have identical electrical
characteristics. The set of digital ICs belonging to the same logic family are electrically
compatible with each other.

Bipolar Logic Families:

The main elements of a bipolar IC are resistors, diodes (which are also capacitors) and transistors. Basically,
there are two types of operations in bipolar ICs:

1. Saturated, and
2. Non-saturated.

In saturated logic, the transistors in the IC are driven to saturation, whereas in the case of non-saturated logic,
the transistors are not driven into saturation.

The saturated bipolar logic families are:

1. Resistor–transistor logic (RTL),

2. Direct–coupled transistor logic (DCTL),
3. Integrated–injection logic (I2L),
4. Diode–transistor logic (DTL),
5. High–threshold logic (HTL), and
6. Transistor-transistor logic (TTL).

The non-saturated bipolar logic families are:

1. Schottky TTL, and

2. Emitter-coupled logic (ECL).

Unipolar Logic Families

MOS devices are unipolar devices and only MOSFETs are employed in MOS logic circuits. The MOS logic
families are:

1. PMOS
2. NMOS
3. CMOS
Characteristics of Logic Families:
The main characteristics of Logic families include:
∙ Fan-in (Fan-in (input load factor))
Is the number of input signals that can be connected to a gate without causing it to
operate outside its intended operating range. Expressed in terms of standard inputs or
units loads (ULs)

Example: for standard TTL one unit load is defined as

1 UL = 40mA in the HIGH state ,1.6mA in the LOW state to determine the fan-in (or fan
out) for a gate, take the lower of HIGH state current
HIGH state unit load and LOW state current ,LOW state unit load.
A fan-in of 8 means that 8 unit loads can be safely connected to the gate inputs.

 Fan-out(output load factor): is the number of inputs of a logic function that can be
driven from a single output without causing any false output.

A fan-out of 10 means that 10 unit loads can be driven by the gate while still maintaining
the output voltage within specifications for logic levels 0 and 1.

Example:
A unit load for some particular logic family is as follows:

1UL = 50A HIGH state

= 1mA LOW state
Determine the fan-in and fan-out for a gate in this family that has the
following parameters:

IOH = 400mA
IOL = 10mA
IIH = 150mA
IIL = 4 mA

Solution:
 fan-in = 150/50 = 3 UL or 4/1 = 4 UL
therefore fan-in = 3.
fan-out = 400/50 = 8 UL or 10/1 = 10 UL
therefore fan-out = 8 UL.
 Power dissipation. The power dissipation parameter for a logic family is specified in
terms of power consumption per gate and is the product of supply voltage VCC and
supply current ICC. Power dissipation is the amount of heat (in milliwatts) that the IC
dissipates in the form of heat.

 Propagation delay tp. is the time delay between the occurrence of change in the logical
level at the input and before it is reflected at the output. It is the time delay between the
specified voltage points on the input and output waveforms.

tPLH is the propagation delay as the output waveform moves from low-to-high. Delay time
in going from logic 0 to logic 1(turn-on delay).
tPHL is the propagation delay as the output waveform moves from high-to-low. Delay time
in going from logic 1 to logic 0 (turn-off delay).

 Speed–power product. The speed of a logic circuit can be increased, that is, the
propagation delay can be reduced, at the expense of power dissipation.

Speed-power product: TPD ×Pavg Where TPD - propagation delay

Pavg - Average power
 Rise time, tr. This is the time that elapses between 10 and 90 % of the final signal level
when the signal is making a transition from logic LOW to logic HIGH.

 Fall time, tf. This is the time that elapses between 90 and 10 % of the signal level when it
is making HIGH to LOW transition.

 Maximum clock frequency, fmax.This is the maximum frequency at which the clock
input of a flip-flop can be driven through its required sequence while maintaining stable
 transitions of logic level at the output in accordance with the input conditions and the
product specification.

 Noise margin. This is a quantitative measure of noise immunity offered by the logic
family. When the output of a logic device feeds the input of another device of the same
family, a legal HIGH logic state at the output of the feeding device should be treated as a
legal HIGH logic state by the input of the device being fed. Similarly, a legal LOW logic
state of the feeding device should be treated as a legal LOW logic state by the device
being fed.

VNH = HIGH-state noise margin

VNL = LOW-state noise margin
VIL = LOW-state input voltage
VIH = HIGH-state input voltage
VOL = LOW-state output voltage
VOH = HIGh-state output voltage
HI state noise margin:VNH= VOH(min) –VIH(min)LO state noise margin:VNL=
VIL(max) –VOL(max)Noise margin:VN= min(VNH,VNL)
where
VNH = VOH -VIH
VNL = VIL – VOL
Manufacturers specify voltage limits to represent the logical 0 or 1. These limits are not
the same at the input and output sides. For example, a particular gate A may output a
voltage of 4.8V when it is supposed to output a HIGH but, at its input side, it can take a
voltage of 3V as HIGH. In this way, if any noise should corrupt the signal, there is some
margin for error.
Consider the following case where the output of logic circuit A is connected to the input
of logic circuit B.

When the output of A is low, VO, the input to B, Vi, should also be low. But because of noise Vi
is not exactly VO but could higher. As long as Viis not more than VIL, B will still take the signal
as a LOW. If Viis more than VIL though, then the signal may not appear as a LOW. The effect of
noise is shown in the following figure.

Example:
Find the HIGH state and LOW state noise margins for the IC with the
characteristics given in the table.
Minimum Typical Maximum
VOH 2.8 V 3.6V
VOL 0.2V 0.4V
VIH 2.0V
VIL 0.8V
From table,
HIGH-state noise margin VNH = 2.8 – 2 = 0.8
LOW-state noise margin VNL = 0.8 – 0.4 = 0.4

Transistor - Transistor
Logic or TTL:

V1 V2 V0

LLH

LHH

HLH

HHL

Fig: Two input TTL NAND gate

Circuits belonging to this family are built using transistors at the input, intermediate and output
stages. In the above fig Multi-emitter transistors(npn) are used at the input stage to accommodate
the inputs. The final stage is a transistor inverter. An npn switches „ON‟ when its base-emitter
junction is sufficiently at a positive voltage with the collector at a higher voltage with reference
to the emitter. Truth table represents the circuit operation, where L represents logic '0' voltage
and H represents logic '1' volts.

When both the emitters of Q1 are at 'H' level,Q1 is OFF and the collector voltage of Q1 keeps
Q2 ON . Current begins to flow from +5v supply through 1.4K resistor in to the 1K resistor. The
drop across the resistance turns Q3 ON into saturation, thereby taking the collector voltage of Q3
to logic 'L' level.

When one or both the emitters of Q1are at 'L' level, Q1 turns ON and the low voltage at collector
of Q2 is not sufficient to keep Q2 ON. thus Q2 goes OFF and thereby Q3 turns OFF. The
collector Q3 now goes to the logic 'H' level.

Wired Logic:
Outputs of gates simply tied together can also be configured to perform logic operations called
wired logic. figure shows two TTL NAND gates with two transistor outputs connected
together.

The wired output appears at the collector of the output transistors of the two gates connected
together.

Observe that if the output transistors of both the NAND gates are OFF, the wired output will be
at 'H' level. If the output transistor of one of the gate is ON, the wired output will be at 'L' level,
thereby exhibiting AND logic. The logic effect of the wired connection is illustrated in Fig.

From the fig. we can write Y=(ab)'.(cd)'= (ab+cd)'

Connecting two NAND gates as in fig effectively places the resistance R3 at the collectors of the
output transistors in parallel, reducing the effective resistance at the collector to R3/2.this
increases the current and power dissipation in the transistor which is ON. To avoid this TTL
gates without R3 are available commercially called open collector TTL. A two input open
collector TTL NAND gate is shown in fig. below.
The external resistance has to be connected across AB for normal operation at a desired current.
Such a external resistance is called a passive pull-up resistor because the collector of the output
transistor is pulled up to a positive supply voltage.

Two input NAND Gate with totem-pole output

In logic circuits transistors play the role of switches. For those in the TTL gate the conducting
state (on) occurs when the base emitter signal is high, and the non-conducting (off) when it is
low. Signals corresponding to logical variables x and y are applied to the emitters of the input
transistor T1 where the actual logic is essentially performed. Transistor T2 plays the role of a
phase splitter. When it is off, the collector voltage is at essentially V and the emitter is at 0.
When it is conducting current I2 flows through the series resistors. The collector voltage drops to
V-I2*R and the emitter voltage rises to I2R, where R is the appropriate resistor. The collector
and emitter voltages then vary in opposite phase. Moreover each phase leads to only one of the
two output transistors being conducting. Note that if either x or y is low (ie =0) then T1 is on and
the base voltage is at its lowest value V-I1*R. Here again R is used generically, each element
having distinct values in practice. The collector of T1 and the base of T2 are low so that T2 is
off. In this situation the base of T3 is high turning this transistor on while the base of T4 is 0 and
this transistor is off. In this situation the output is connected to the high voltage line V and goes
high. When connected to a load it will deliver current. In the case when both x and y are high
then T1 is off, turning T2 on. This reduces the voltage on the base of T3 below its emitter
voltage so that it becomes non-conducting. The base of T4 on the other hand is driven up by an
amount I2*R and becomes conducting. In this case the output is connected to ground through T4
and the output is low. Note that in this state, when connected to a load, 3.2 current will flow into
the gate. The operation is summarized in the following table.

The pair of transistors T3 and T4 constitutes what is known as a totem pole output. They are
arranged so that only one of the two is conducting in a steady state condition.

CMOS (Complementary Metal Oxide Semiconductor)Logic:

These circuits are constructed using both n-channel and p- channel enhancement type
MOSFETs.CMOS gates are manufactured in SSI and MSI packages also.

CMOS Inverter:

Figure shows the schematic of the CMOS inverter circuit. It can be seen that
the gates are at the same bias Vin which means that they are always in a
complementary state. When Vin is high, Vin≈Vdd, the voltage between
gate and substrate of the nMOS transistor is also approximately
Vdd and the transistor is in on-state. The gate-substrate bias at the pMOS on the other side is
nearly zero and the transistor is turned off. The output voltage Vout is pulled to ground, which is
the low state. When the input voltage is in a high-state, the complementary situation occurs and
the pMOSFET is turned on while the nMOSFET is turned off. The output voltage is therefore
pulled to Vdd which is the high-state. It is important to note that in both states, high and low, no
static current flows through the inverter. This is of course only valid when assuming ideal
devices with zero off- and leakage-currents.

Considering negative bias temperature instability, the worst stress conditions are imposed on the
p-channel MOSFET at Vin = Vlow. At this bias condition the pMOSFET is turned on, with
approximately the same potential at the source and the drain Vgs=Vgd=Vdd and negative gate to
substrate voltage Vgsub = - Vdd .

CMOS NAND Gate:

Fig Shows CMOS NAND gate. Transistors Q1 and Q3 resemble the series-connected
complementary pair from the inverter circuit. Both are controlled by the same input signal (input A),
the upper transistor turning off and the lower transistor turning on when the input is “high” (1), and
vice versa. Notice also how transistors Q2 and Q4 are similarly controlled by the same input signal
(input B), and how they will also exhibit the same on/off behavior for the same input logic levels. The
upper transistors of both pairs (Q1 and Q2) have their source and drain terminals paralleled, while the
lower transistors (Q3 and Q4) are series-connected. What this means is that the output will go “high”
(1) if either top transistor saturates, and will go “low” (0) only if both lower transistors saturate. The
following sequence of illustrations shows the behavior of this NAND gate for all four possibilities of
input logic levels (00, 01, 10, and 11):
CMOS NOR gate:

Fig Shows CMOS NOR gate. Ttransistors Q1 and Q3 work as a complementary pair, as do
transistors Q2 and Q4. Each pair is controlled by a single input signal. If either input A or input B
are “high” (1), at least one of the lower transistors (Q3 or Q4) will be saturated, thus making the
output “low” (0). Only in the event of both inputs being “low” (0) will both lower transistors be
in cutoff mode and both upper transistors be saturated, the conditions necessary for the output to
go “high” (1). This behavior, of course, defines the NOR logic function.

Characteristics of CMOS logic:

1. Dissipates low power: The power dissipation is dependent on the power supply voltage,

frequency, output load, and input rise time. At 1 MHz and 50 pF load, the power dissipation is

typically 10 nW per gate.

2. Short propagation delays: Depending on the power supply, the propagation delays are

usually around 25 nS to 50 nS.

3. Rise and fall times are controlled: The rise and falls are usually ramps instead of

step functions, and they are 20 - 40% longer than the propagation delays.
4. Noise immunity approaches 50% or 45% of the full logic swing.

5. Levels of the logic signal will be essentially equal to the power supplied since the input

impedance is so high.

Characteristics of TTL logic:

1. Power dissipation is usually 10 mW per gate.

2. Propagation delays are 10 nS when driving a 15 pF/400 ohm load.

3. Voltage levels range from 0 to Vcc where Vcc is typically 4.75V - 5.25V. Voltage range 0V

- 0.8V creates logic level 0. Voltage range 2V - Vcc creates logic level 1.

Compression of CMOS and TTL logic:

1. CMOS components are typically more expensive that TTL equivalents. However, CMOS
technology is usually less expensive on a system level due to CMOS chips being smaller and
requiring less regulation.

3. CMOS circuits do not draw as much power as TTL circuits while at rest. However, CMOS
power consumption increases faster with higher clock speeds than TTL does. Lower current
draw requires less power supply distribution, therefore causing a simpler and cheaper design.

4. Due to longer rise and fall times, the transmission of digital signals becomes simpler and less
expensive with CMOS chips.

5. CMOS components are more susceptible to damage from electrostatic discharge than TTL
components.