ECE department, BMSCE Digital Electronics Lab (15ES3GCDEC) III semester, ECE

Sl.No List of Experiments

l

a
1 Working of 74153 IC- Dual 4 X 1 Multiplexer,
74139 IC- Dual 1 X 4 De-multiplexer
n

2 Applications of 74153 and 74139.

i

3 Magnitude comparator- 1 bit comparator using logic gates and IC

b
i

7485 – 4-bit
m

4 Encoder – IC 74147, 74148, Decoder – 7 segment display

Design of a 3-bit asynchronous / ripple binary counter- Mod N ( N ≤

s

i
5
8) using 7476 ICs. The timing waveforms on CRO. Different Mod
u

values
r

6 Study of asynchronous counter ICs: 7490, Mod N (N ≤ 10), and 7493

a

e
(N ≤ 16). Timing waveforms on CRO. Different Mod values.
u

7 Design of a 3-bit synchronous binary counter- Mod N ( N ≤ 8) using

q

7476 ICs. The timing waveforms on CRO. Different Mod values

8 Study of synchronous counter ICs: 74190, Mod N (N ≤ 10), and 74192

and 74193 (N ≤ 16). Timing waveforms on CRO. Different Mod values.

9 Working of 4- bit shift register IC- 7495. Different modes of

operation with different data.

10 Applications of 4-bit shift register IC- 7495 as ring counter,

Johnson counter.

The DEC lab is to be evaluated for 15 marks which will be added to the IA marks of the theory
to generate the final IA marks of the integrated course.
⮚ Lab marks is for 15

⮚ Conduction and records = 10 marks,

⮚ lab test and Viva-voce = 05 marks

Instruction to students:

∙ Each student should complete all the experiments listed under preliminary
experiments.
∙ The duration fixed for completing the preliminary experiments is 4 lab sessions.
∙ 6 lab sessions are reserved for completing the open ended experiments. ∙ The list

of open ended design problems will be announced on notice board. ∙ All the results
and observations must be documented in the observation / record book.
Dr.HRB, DEC Course coordinator
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ECE department, BMSCE Digital Electronics Lab (15ES3GCDEC) III semester, ECE
Introductory experiment
Aim: (i) Realization of parallel adder / subtractor using 7483 ( 4 bits parallel adder) chip.
(ii) BCD to Ex-3 code conversion and Ex-3 to BCD code conversion. ( i ) Parallel adder /
subtractor using 7483

Input terminals: A4 A3 A2 A1, B4 B3 B2 B1 and Cin

Output terminals: S4 S3 S2 S1 and Cout

4 bit binary addition.

Procedure: 1) Keep control input M=0 (refer page 4, with 7486 IC )

2) Keep Cin = 0.( connect pin 13 to gnd)
3) Apply A & B ( both 4 bit numbers)
4) Verify the sum on S4S3S2S1 and cout.

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 ECE department, BMSCE Digital Electronics Lab (15ES3GCDEC) III semester, ECE

Eg : 1) A4A3A2A1 = 0111
B4B3B2B1 = 0110

S4S3S2S1 = 1101 , Cout = 0

Eg: 2) A4A3A2A1 = 1101

B4B3B2B1 = 0110

S4S3S2S1 = 10011 , Cout = 1

Try for other 4 bit numbers

4 bit binary subtraction using 1’s complement method:

Steps:

1. Add the minuend A to the 1’s complement of subtrahend B.

2. If an end-around carry occurs , add it to the least significant digit of the result obtained in
step 1 .The final result is +ve .

1. If there is no end –around carry, take 1’s complement of the result obtained in step1 .
The result is -ve .

Procedure :

1. Keep M = 1.,Cin = 0.
2. Apply A & B.
3. Verify the result on S4S3S2S1.and Cout.

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ECE department, BMSCE Digital Electronics Lab (15ES3GCDEC) III semester, ECE
Eg : 1) A4A3A2A1 = 1010 A4A3A2A1 = 1010
B4B3B2B1 = 0100 1’s of B, B4B3B2B1 = 1011

EAC = 1 S4S3S2S1 = 1 0101 , Cout = 1 1

Final ans S4S3S2S1 = 0110

Eg: 2) A4A3A2A1 = 0100 A4A3A2A1 = 0100

B4B3B2B1 = 1010 1’s of B B4B3B2B1 = 0101

S4S3S2S1 = 1001 , Cout = 0 EAC = 0 .Therefore the result is –ve and is in 1”s

complement form. 4 bit binary subtraction using 2’complement method:

Rules for 2’s complement method of subtraction.( A – B )

1. Add the minuend A to the 2’s complement of subtrahend B.

2. If an end-around carry occurs , discard it and the final result is +ve .

3. If there is no end –around carry, take 2’s complement of the result obtained in step1 and
place a -ve sign in front.

Procedure :
1. Keep M = 1, . & Cin =1
2. Apply A & B.
3. Verify the result on S4S3S2S1.

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ECE department, BMSCE Digital Electronics Lab (15ES3GCDEC) III semester, ECE
Eg : 1) A4A3A2A1 = 1010 A4A3A2A1 = 1010
B4B3B2B1 = 0100 2’s of B, B4B3B2B1 = 1100

S4S3S2S1 = 1 0110 , Cout = 1 Discard carry

Final ans S4S3S2S1 = 0110

Eg: 2) A4A3A2A1 = 0100 A4A3A2A1 = 0100

B4B3B2B1 = 1010 2’s of B B4B3B2B1 = 0110

S4S3S2S1 = 1010 , Cout = 0 EAC = 0 .Therefore the result is –ve and is in 2”s
complement form

ii) BCD to EX-3 conversion using 7483 IC : BCD to EX-3 number is obtained by adding 3 to
BCD number.
1. Set A to a BCD number (ie., A can vary from 0000 to 1001) and set B = 0011 2
Observe Ex-3 code of A on E4E3E2E1. and verify the truth table as shown below.

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ECE department, BMSCE Digital Electronics Lab (15ES3GCDEC) III semester, ECE
A3 A2 A1 A0 E3 E2 E1 E0

0 0 0 0 0 0 1 1
 0 0 0 1 0 1 0 0

0 0 1 0 0 1 0 1

0 0 1 1 0 1 1 0

0 1 0 0 0 1 1 1

0 1 0 1 1 0 0 0

0 1 1 0 1 0 0 1

0 1 1 1 1 0 1 0

1 0 0 0 1 0 1 1

1 0 0 1 1 1 0 0

Procedure:
1. Apply BCD number on A lines.
2. Set B input to 0011.
3. Mode control M = 0 & Cin = 0.
4. Observe Ex-3 code on the sum lines.
5. Verify the truth table .

iii) EX-3 to BCD number: If 3 is subtracted from EX- 3 code we get BCD code. 2’s
complement method of subtraction can be used.

1. Apply EX-3 code on A.

2. Set B = 0011.
3. Set M = 1 & Cin = 1.
4. Observe BCD equivalent of A on output lines of 7483.
5. Verify the table.

The above two circuits can be combined as follows.

If M = 0 , Cin = 1 BCD to EX-3 conversion can be done( addition ) If

M = 1 , Cin = 1 EX-3 to BCD conversion can be done( subtraction)
 Dr.HRB, DEC Course coordinator
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ECE department, BMSCE Digital Electronics Lab (15ES3GCDEC) III semester, ECE

Experiment No.1

Aim: MUX / DEMUX , use of 74153, 74139 for arithmetic circuits and code conversion.

i) Multiplexer: 74153 is a dual 4:1 MUX and output is same as input.

74153N
DUAL 4 X 1 mux
a0 a1 a2 a3 b0 b1 b2
b3 s0 s1 E1 E2
6
5
4
3
10111213142
1
15
1C 0 1C 1 1C 2 1C 3 2C 0 2C 1 2C 2
2C 3 A
B
~1 G ~2 G

1 Y7 2 Y9

Y1 Y2
 PS: Pin no 16 is Vcc and pin 8 is ground for this IC

E1 is enable input for MUX-1 and E2 is enable input for MUX-2.( both are active
low) S0,S1 are select lines common to both multiplexers.
a0-a3 = inputs of MUX-1 ,Y1 = output of MUX-1.
b0-b3 = inputs of MUX-2, Y2 = output of MUX-2.

Truth table for MUX-1

With E1 = 0 & E2 = 1 MUX-1 will be enabled and MUX –2 will be disabled ( truth table as
shown)
With E1 = 1 & E2 = 0 MUX-1 will be disabled and MUX-2 will be enabled.
With E1 = 0 & E2 = 0 both MUX-1 and MUX-2 are enabled.
E2 E1 S1 S2 DATA INPUTS Y1

a0 a1 a2 a3

1 0 0 0 0 X X X 0

0 0 1 X X X 1

1 0 0 1 X 0 X X 0

0 1 X 1 X X 1

1 0 1 0 X X 0 X 0

1 0 X X 1 X 1

1 0 1 1 X X X 0 0

1 1 X X X 1 1

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Procedure:
1. Refer the pin details of 74153 and make the connections as shown in the fig. 2. Data
inputs ,enable inputs and select inputs are connected to the toggle switches and outputs
are connected to LEDs.
3. Verify the truth table.

ii)DE-MUX : 74139 is a dual 1x 4 DEMUX and can be used as a 2 : 4 decoders

2 14 13 1B 2B
3

15 ~1G ~2G
1
1A 74139D
2A
1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 6 12 11 10 9
4 7
5

74139 can also be used as a 2 : 4 decoder by keeping Do = 0 and S1 ,S2 as data inputs. It can be
constructed using NAND
gates only. 0 1 1 1
Select inputs Data input
1 0 0 1
S1 S0 D0 Y3
1 0 1 1
0 0 0 1
1 1 0 0
0 0 1 1
1 1 1 1
0 1 0 1
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ECE department, BMSCE Digital Electronics Lab (15ES3GCDEC) III semester, ECE

Experiment No.2

Applications of 74153 and 74139

Arithmetic circuits using 74153.

Half adder :
Procedure : 1.Ground the two enable pins .
2. Take S1 as A input and S2 as B input.
3. Inputs of MUX1 take the Sum values and those of MUX2 take the carry values.
Circuit diagram (S1 and S2 are common to both MUX1 and MUX2)
B

INPUTS ~G
SUM Carry
INPUTS
A B CDr.HRB, DEC Course
A B SUM coordinator
(S) 0 0 0logic 0

0 0 1logic 1
0 0
0 1 0
A
0 1
0 1 1
B
1 0 Y
D0D1
1 0 0DD 23
1 1 A

1 0 1B
~G

1 1 0Y
D0D1

Full adder using 74153 D2

1 1 1A
D3
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ECE department, BMSCE Digital Electronics Lab (15ES3GCDEC) III semester, ECE

D0D1D2D3 B
cin 12 ~G sum
A
D0D1D2D3 YY
A

A
B

B
~G

logic 0 logic 1 carry

SUM = Σm(1,2,4,7,)
CARRY = Σm(3,5,6,7)

Learn MUX implementation table.

Procedure : 1.Ground the two enable pins in order to enable the 74153. 2.
Connect S1 as A input and S2 as B input.
3. Complete the circuit as shown in the fig and verify the truth table of the
Full adder.

Exercise : Implement half subtractor and Full subtractor using 74153.

Arithmetic circuits using 74139 ( full adder and full subtractor).

Learn Code converters using 74153 and 74139. Eg.Binary to Gray code converter.
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ECE department, BMSCE Digital Electronics Lab (15ES3GCDEC) III semester, ECE

Experiment No. 3
 Aim: Realization of one/two bit comparator and study of 7485 magnitude comparator.

One bit comparator: From the table,( A < B) = Ā0 B0 (A = B ) = A0B0 + Ā0B0

21

9
1 081 2

A0 B0 A< B A = B A > B
3

0 0 0 1 0 ( A > B) = A0B0

0 1 1 0 0

1 0 0 0 1

1 1 0 1 0

A0 B0
54

1 31 1
A<B

1 4 9
1 08 A=B
2 5
12
36

1
1 31 1 23

A>B

Procedure: Connect the circuit as shown in the fig.

Verify the truth table of one bit comparator.

The above circuit can also be constructed using basic gates and Ex-Or gates as shown in the fig
below.

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ECE department, BMSCE Digital Electronics Lab (15ES3GCDEC) III semester, ECE
2

A0 B0

1
34

1 3
A0 B0
2 4

Learn 2-bit comparator

1

A B 56

3
2
6 AB
5 AB

Study of 4 bit magnitude comparator IC

7485- Write the truth table for 4 bit comparator.

74LS85
1 5A 3 1 3A 2 1 2A 1 1 Data inputs C
A&B
0A 0 1B 3 1 4B 2 1 1B 1 A

9 2 IA<B3 IA=B4 IA>B7 A>B

B 0
A=B
A<B6 A=B5
A>B A<B

Procedure: Connections are made using the pin details of 7485 I.C. Connect A>B
and A<B cascading inputs to the logic 0 and A=B input to logci 1 level Connect the
inputs A and B ,the outputs to LEDs and verify the truth table.

Learn 8 bit comparator using 7485s

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ECE department, BMSCE Digital Electronics Lab (15ES3GCDEC) III semester, ECE

Experiment No. 4
Aim: Use of a) decoder chip to drive LED/LCD display
and b) Priority encoder
ICs required : 7446 (decoder / driver)

MAN72

ABCD 354 C LT 13 12 11 10 9 SEVEN_SEG_D

ISPLAY
71 D RBI 15 14
A OA OB OC OD
26
B OE OF OG A B C DE F G

Procedure: BI/RBO 7446N

1. Connections are made as shown in the circuit diagram.

2. Apply BCD inputs on DCBA lines using toggle switches and observe the output on
7 segment LED display unit.
3. Observe the outputs for the remaining combinations of the 4 bit code.

a) Priority Encoder –
74147 - Decimal to BCD encoder
74148 - Octal to Binary encoder

Pin details of 74147 and 74148 are as shown below.

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ECE department, BMSCE Digital Electronics Lab (15ES3GCDEC) III semester, ECE
 10
11
9
9 A 11 A0
12 1 01 7
13 1 3 BC 7 14 2 A1 6
2345 234
2 12 13 1 A2 G S
6 14 15
D 34 56 E0
46 57

10 9 5 ~EI
8 7
74147N 74148N

74147 is a 9 to 4 lines priority encoder. It accepts data from nine active –low inputs and
provides a BCD output on four active-low outputs. A priority is assigned to each input so that
when two or more inputs are simultaneously active(logic 0 ) ,the input having highest priority is
represented on the output. Input 9 (pin 10 ) has the highest priority.
When all inputs are high then four outputs are high which is nothing but
‘zero’ Truth table of 74147:
Active-low decimal inputs Active –low BCD outputs

1 2 3 4 5 6 7 8 9 D C B A

1 1 1 1 1 1 1 1 1 1 1 1 1

0 1 1 1 1 1 1 1 1 1 1 1 0

X 0 1 1 1 1 1 1 1 1 1 0 1

X X 0 1 1 1 1 1 1 1 1 0 0

X X X 0 1 1 1 1 1 1 0 1 1

X X X X 0 1 1 1 1 1 0 1 0

X X X X X 0 1 1 1 1 0 0 1

X X X X X X 0 1 1 1 0 0 0

X X X X X X X 0 1 0 1 1 1

X X X X X X X X 0 0 1 1 0

Procedure: Connect inputs to toggle switches and outputs to LEDs. Verify the truth table.
Dr.HRB, DEC Course coordinator
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ECE department, BMSCE Digital Electronics Lab (15ES3GCDEC) III semester, ECE
74148 is an octal to binary encoder. Like 74147 this also has active low inputs and active low
outputs. In addition an enable input ( EI – pin 5) and an enable output( EO- pin 15 ) are provided
for cascading purposes. The enable input must be asserted low state to enable the chip while the
enable output goes to low state only when all its inputs are inactive (i.e., all high). Also there is
one more output namely GS ( pin 14 – SELECT) which goes low whenever one of it’s inputs is
active(i.e., low state).
Truth table of 74148:
EI Active –low inputs Active-low outputs

0 1 2 3 4 5 6 7 C B A G EO
S

1 X X X X X X X X 1 1 1 1 1

0 0 1 1 1 1 1 1 1 1 1 1 0 1

0 X 0 1 1 1 1 1 1 1 1 0 0 1

0 X X 0 1 1 1 1 1 1 0 1 0 1

0 X X X 0 1 1 1 1 1 0 0 0 1

0 X X X X 0 1 1 1 0 1 1 0 1

0 X X X X X 0 1 1 0 1 0 0 1

0 X X X X X X 0 1 0 0 1 0 1

0 X X X X X X X 0 0 0 0 0 1

0 1 1 1 1 1 1 1 1 1 1 1 1 0

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ECE department, BMSCE Digital Electronics Lab (15ES3GCDEC) III semester, ECE

Introductory experiment for sequential circuits.

Truth table verification of J-K Master Slave Flip Flop, T-type FF and D – type FF.

Aim: Truth table verification of

i) J-K Master Slave Flip flop.
ii) T-type FF
iii) D-type FF

Truth table of J-K FF

With clock = 0, J = K = X, Qn+1 = Qn
With clock = 1, and apply various J and K verify the truth table as shown below.
 J K Qn Qn Qn+1 Qn+1 Remarks

0 0 0 1 0 1 No change
1 0 1 0

0 1 0 1 0 1 Reset
1 0 0 1

1 0 0 1 1 0 Set
1 0 1 0

1 1 0 1 1 0 Toggles
1 0 0 1

Realization of JK MS FF ,T and D FFs using 7476 I.C

7476 I.C is a dual J-K FF having preset and clear inputs. Refer the pin details of 7476 and
construct T- FF and D- FF .
Verify the truth tables of each circuit.

Realization of JK MS FF ,T and D FFs using 7473 I.C

7473 is a dual J-K FF having only clear inputs. Refer the pin details of the I.C Verify
the truth tables of each circuit.
7473 is a dual J-K FF having clr inputs (no presets).The pin details are as shown in the fig
below. 7473N
14 1 1CL K 2J 32 2K
~1Q13
1Q12 2CL K 10 6 ~2Q8
75 1K
1J 2Q9

~1CLR ~2CLR

pin 4 = Vcc and pin 11 = Gnd.

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ii)T-type FF using MS JK FF 0 X Qn

0 Qn
pr
1 Qn

SET

Inputs T Qn+1
clk
 K ~Q
T clk Q
J

RESET

cr
iii) D-type FF using MS JK FF

pr

clk
SET

Inputs D Qn+1
clk

0 X Qn

0 0

1 1

Q
 K
12 ~Q

RESET

cr
Procedure: 1. Connections are made as shown in figs.
2. Truth tables of JK-FF, D-FF and T-FF are verified.

Procedure: Connections for T- and D- FF s are similar to those using 7476.

Use pin details for construction.
If clr = 0 the output will be cleared.
Keep clr = 1 and verify the truth tables.

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ECE department, BMSCE Digital Electronics Lab (15ES3GCDEC) III semester, ECE

Experiment No 5
Asynchronous counters using 7476 JK Flip flops

Aim: Realization of 3 bit Asynchronous counters as a sequential circuit and mod-N counter
design.

Realization of 3 bit binary ripple counter using 7476 I.C.(Mod – 8 ) Q 0 Q 1 Q 2

Preset

Logic 1

J SET Q J SET Q J SET Q

clk
FF0 FF1 FF2
K ~Q K ~Q K ~Q

clear RESET RESET RESET

Connections: 1.J and K inputs are shorted together and both are kept at logic 1.
2.When pr = 1, clr = 0, counter is cleared. Q0 = Q1 = Q2 = 0.
 3.When pr = 0, clr = 1, counter is preset. Q0 = Q1 = Q2 = 1. 4. Keep pr = 1,
clr = 1, to put the counter in count mode.
Truth table :
Clock Q2 Q1 Q0
inputs

0 0 0 0

1 0 0 1

2 0 1 0

3 0 1 1

4 1 0 0

5 1 0 1

6 1 1 0

7 1 1 1

8 0 0 0

The waveforms at the outputs of the counter can be seen on CRO by applying a
clock signal of frequency 1khz and above.The waveforms are as shown in the
fig.

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ECE department, BMSCE Digital Electronics Lab (15ES3GCDEC) III semester, ECE

3 bit mod – 8 down counter. 1 1 1 0

Output Q0 is connected to Ck1,Q1 is connected to
2 1 0 1
Ck2 . Truth table for 3 bit down counter---
3 1 0 0
Realization of Mod-N ripple counter where N is [ 7
4 0 1 1
Procedure:1. Construct a 3 bit counter using 7476I.C.
2. Assume N = 6, which in binary is written as 110. 5 0 1 0
3. Connect Q2 and Q1 as inputs to a Nand gate(7400)
and it’s output to the clear input. 6 0 0 1
4. Verify the truth table of mod-6 counter .
5. Similarly try other mod counters. 7 0 0 0
Clock Q2 Q1 Q0 8 1 1 1
inputs

0 1 1 1
1 To Clear input
Q23
Q1 2

3 bit up/down counter using 7476 I.C.

p r(LSB)
Q0 Q1
Q2
LSBMSB 1 2
S ET Q J Q 4 J
J S ET S ET
1 31 1
Q

3
1

2
9
1 08
~Q ~Q 6 ~Q
FF0 FF1 FF2

R ES E T 45 6 12 3 R ES E T K
M K
clr 12 5
R ES E T K

If M = 1 counter works as an up counter.

If M = 0 counter works as a down counter.
Procedure:
Connections are made as shown in the fig (use the pin details of the Ics.) J =
K= 1, ie., FFs are in the toggle mode.

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ECE department, BMSCE Digital Electronics Lab (15ES3GCDEC) III semester, ECE
Clear the outputs by taking clr = 0 and pr = 1.
Keep preset and clear inputs at logic 1 for count mode
Apply clock pulses and verify the count table for both UP and DOWN counting.
Apply continuous clock of frequency f = 1KHz or above and observe the output
wave forms at Q0,Q1 and Q2 terminals on CRO.

The above circuit can be converted into a MOD N counter using suitable feedback to CLR
input as explained in the previous section.
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ECE department, BMSCE Digital Electronics Lab (15ES3GCDEC) III semester, ECE

Experiment No 6
Asynchronous counters ICs

Study of 7490 decade counter.

7490 is a decade counter ( BCD counter or a Mod-10 counter). It contains a mod-2 and mod-5
counter which can be cascaded to give a mod-10 counter.

74LS90
6MS1 7MS2 2MR1
3
MR2
14 CP0 1
CP1

Procedure:

11 8 9
Q3 Q2 Q1
12
Q0
MR1 MR2 MS1

1 1 0

0 0 X

1 1 X
 1. Connect MS1(pin 6 ) and MS2(pin 7) inputs GND .
2. MR1(pin 2) is connected to logic 1.
3. MR2( pin 3 ) is momentarily connected to logic 1 and then connected to logic 0 for
COUNT mode.( Refer to the functional table of 7490).
4. Connect Q0(pin 12 ) and CK B (pin 1 ) are shorted to convert the counter into
mod-10 counter.
5. Apply the clock pulses to CK A ( pin 14 ) and verify the count sequence. 6.
Apply a clock signal of frequency 1 khz or above and observe the waveforms at
Q0,Q1,Q2,and Q3.

ii) Realization of Mod- N counter using 7490 I.C. (N = 9 )

Example : Let N = 5.
5 in binary is written as 0101.
Connect the 1s in the word to a NAND gate as inputs ( Q2 and Q0 ) .The output of Nand gate
is complemented and connected to MR1 and MR2 as shown in the fig.
So, as the counter counts and when binary word 5 occurs at the output of 7490, both inputs to the
first Nand gate will be 1 and it’s output will be 0 and is inverted by the second Nand gate to 1
which is then applied to shorted MR1 and MR2 which takes the counter to reset mode( refer to
the functional table of the counter) and counter once again counts from 0000 and stops at 0100
and the sequence repeats.. Similarly other Mods can be tried .
Note: Some of the Mod counters can also be obtained without using external logic gates.

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For eg. In binary 5 the Q2 and Q0 ( two 1s) are taken and connected directly to MR1 and MR2
respectively in order to reset the counter.Same principle can be used for other mod counters.

14 QA 12

clkQ0 A
1 2 R 9(1) R 9(2) R 0(1) R 0(2) 8
QBQCQD
Q2
11
6 3
9
7 B
Q1 Q3

34
1
6
2
5

iii) Study of 7493 I.C binary ripple counter.

TO use 7493 as a Mod-16 counter and also to get mod-N counter (N [ 15 ) 7493 has a
mod-2 and a mod- 8 counter which can be cascaded to get mod-16 counter. Pin details
and functional table of 7493 are given below.
 Procedure: 1. Connect the circuit as shown in the fig.
2. MR1(pin 2) is connected to logic 1.
3. MR2( pin 3 ) is momentarily connected to logic 1 and then connected to logic 0
for COUNT mode.( Refer to the functional table of 7493). 4. Connect Q0(pin 12 )
and CK B (pin 1 ) are shorted to convert the counter into a mod-16 counter.
5.Apply the clock pulses to CK A ( pin 14 ) and verify the count sequence.
6.Apply a clock signal of frequency 1 khz or above and observe the
waveforms at Q0,Q1,Q2,and Q3.
MR1 MR2 Q3 Q2 Q1 Q0

1 1 0 0 0 0

0 1 Count mode

1 0 Count mode

1 1 Count mode

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74LS93
2MR1 3MR2 1 4 CP0 1 1 1 Q 38 Q 29 Q
CP1
11 2
Q 0

Realization of Mod-N counter (N = 15 ) USING 7493.

Let N = 6.
In binary 6 Q2 and Q1 are 1 . So, Q2 and Q1 outputs of the counter are used to reset the
counter. As soon as Q2 and Q1 both becomes 1 the output of the second Nand gate
becomes 1 which takes the counter to reset mode.
Similarly other mod counters can be realized.(See the pin details of 7493)

14
Q A12
CLK Q0
6 3 A 3 1
Q B9 Q C8 Q D11
1 B 2
4
2 R0(1) R0(2)
5 Q1 Q2 Q3

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ECE department, BMSCE Digital Electronics Lab (15ES3GCDEC) III semester, ECE
Experiment No 7
Synchronous Counters

Design and realization of 3 bit synchronous counters using 7476 I.C. 1. Design of

a Mod – 5 synchronous up counter using J – K master slave flip flops.

Counter sequence table. Excitation table of JK flip flop.

8 0 0 0
Clock A B C
inputs

0 0 0 0 State table :
Prese Next J K
1 0 0 1 nt state
State o/p
2 0 1 0 o/p
3 0 1 1 0 0 0 X
4 1 0 0 0 1 1 X
5 1 0 1 1 0 X 1
6 1 1 0 1 1 X 0
7 1 1 1
 Present state Next state FF A FF B FF C

A B C A B C JA KA JB KB JC KC

0 0 0 0 0 1 0 X 0 X 1 X

0 0 1 0 1 0 0 X 1 X X 1

0 1 0 0 1 1 0 X X 0 1 X

0 1 1 1 0 0 1 X X 1 X 1

1 0 0 1 0 1 X 1 0 X 0 X

1 0 1 1 1 0 X 1 0 X X 1

1 1 0 1 1 1 X 1 X 1 0 X

1 1 1 0 0 0 X 1 X 1 X 1

Use K-maps to get the expressions for J –K inputs of the three FFs.

JA = BC ; JB = C ; JC = 1 ; KA = BC ; KB = C ; KC = 1

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ECE department, BMSCE Digital Electronics Lab (15ES3GCDEC) III semester, ECE
CBA

Preset S ET S ET S ET
1 6
34 5
2

Logic 1 J ~Q Q J ~Q
Q J ~Q Q
FFC FFB FFA
clock Clear R ES E T K R ES E T K R ES E T K

Procedure: Connect the circuit as shown in the fig. Verify the truth table of the
counter.
Ex: The synchronous counter can be designed for any count sequence.
3 bit synchronous up/down counter:
Mode A B C
M

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

0 0 0 0

0 1 1 1

0 1 1 0

0 1 0 1

0 1 0 0

0 0 1 1

0 0 1 0

0 0 0 1

0 0 0 0
 Learn the design and calculate the expressions for JK inputs

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ECE department, BMSCE Digital Electronics Lab (15ES3GCDEC) III semester, ECE
C
B Amode

2 J Q 12 3 S ET 2 Q 12 S ET
pr S ET 1 31 2 1 31 1
1 J 1 J
3 9 Q
1 08
~Q ~Q ~Q
FFC FFB FFA

R ES E T K 45 6 345 6
1 clr clk R ES E T K R ES E T K

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ECE department, BMSCE Digital Electronics Lab (15ES3GCDEC) III semester, ECE
Experiment No 8
Synchronous Counters
 Study of 74192 decade up/down synchronous counter.

Functional table of 74192

15
Load Clear 1 0
1
109 3
ABCD X 1 0 0
2
QAQBQCQD
1 0 1 06
7

1113
~L OA D ~B O
1412

4 UP

5 C LR
D OW N 74192N
~C O

Procedure: For up counting ,

1.Clear = 1 to clear all the outputs.
2. Keep clear = 0
Load = 1, clk-down = 1.
3. Apply clock pulses to clk-up input and observe the count sequence from 0000 to
1001(0,1,2,……9)

P.S : Carry and borrow outputs are normally at logic 1, but if the outputs change from 1001 to
0000 then carry = 0 and then changes back to 1( up counting)

Procedure :For down counting ,

1.Clear = 1 to clear all the outputs.
2. Keep clear = 0
Load = 1, clk-up = 1.
3. Apply clock pulses to clk-down input and observe the count sequence from 1001 to
0000(9,8,7,……0)
4. As the outputs changes from 1001 to 0000 borrow output = 0 and changes back to
1 5. Observe the waveforms at various outputs.

Use of 74192 as presettable up counter.

Example: To count from 6 to 9.
Procedure: 1. Connect the circuit as shown in the fig.
2. Preset the data inputs to 6
3. Set the counter for up counting .
4. observe the count sequence from 6,7,8,9,6,7,8,9,6,…..

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ECE department, BMSCE Digital Electronics Lab (15ES3GCDEC) III semester, ECE
The above circuit is a Mod-4 presettable up counter.
To have a mod N presettable up counter, use N+1 th state for feedback.
For example in the above circuit 5th state ie. 0000 is used for feedback.

1 ABC QAQBQCQD 3267

0110 15 109

1113D

~L OA D 1
~B O
3

1412 5
9

2 4 6

45 C LR ~C O
8

D OW N U P

Use of 74192 as presettable down counter.

Example: To count from 7 to 3
Procedure: 1. Connect the circuit as shown in the fig.
2. Preset the data inputs to 7
3. Set the counter for down counting .
4. Observe the count sequence from 7,6,5,4,3,7,6,5,4,3,7,…. This is a mod-5
counter and notice that N+1 th state ie., 0010 is used for feedback.

1 110 1 ABCD QAQBQCQD

15 109 3267

1113
~L OA D 1
~B O
1412
3
5

2 4

45 C LR ~C O
6

D OW N U P

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ECE department, BMSCE Digital Electronics Lab (15ES3GCDEC) III semester, ECE
iii) Study of 74193 binary up/down synchronous counter.
74193 is a synchronous 4-bit binary up-down counter which can be cleared and preset for any
count.
Pin details and functional table are same as those of 74192.
Procedure for both up counting and down counting is same as in the case of 74192. Observe
that,in up counting mode 74193 counts from 0,1,2,……15 and carry goes low when the outputs
change from 1111 to 0000.
Similarly , in the down counting mode it counts from 15,14,13,………0 and borrow goes low
when outputs change from 0000 to 1111.
In the same manner ,we can have mod-N presettable up/down counter using 74193.

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ECE department, BMSCE Digital Electronics Lab (15ES3GCDEC) III semester, ECE
Experiment No.9
Shift left , shift right, SIPO,SISO,PISO,PIPO operations using 7495 I.C
Aim: To study 7495 , a 4 bit shift register and use it for
a) Shift right operation(SIPO,SISO,PISO and PIPO operations)
b) Shift left operation.

Pin details of 7495 are as below.

DS = serial input data ( pin 1 )

Q3,Q2,Q1,Q0 : Parallel outputs of the shift register.(pins 13,12,11,10 respectively, with Q3 as
MSBand Q0 as LSB)
D3,D2,D1,D0 : Parallel inputs to be loaded ( pins 2,3,4,5) .
S : Mode control, ( pin 6 ) S = 1 for loading parallel data inputs and to enable clock2
S = 0 for enabling the clock 1
Clock 1 : For right shift of data ( pin 9 )
Clock 2 : For loading parallel data and for left shift operation. ( pin 8 )
Pin 14 = Vcc and pin 7 = GND.
74LS95
6
S
9 CP1 8 CP2 5D3 4D2 3D1 2D0 1 10 Q3 11 Q2
DS
12 Q1 13
Q0

a) Shift right operation.

i) SIPO (Seial input parallel output) operation.

Procedure: 1. Assume a 4 bit data.
2. Mode control is made 0
3.Clock 1 is connected to the clock input on the trainer kit.
4. LSB of the Serial data to be converted into parallel output is given to serial input
DS( pin 1 ) of 7495.
5.Apply one clock pulse and observe Q3 .
6. Enter next higher data bit and apply a second clock pulse.
7. Observe the right shifting and outputs Q3,Q2.
Continue in the same manner and observe that after 4 clock pulses the serial data appears on
the 4 parallel outputs Q3Q2Q1Q0 as shown.

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ECE department, BMSCE Digital Electronics Lab (15ES3GCDEC) III semester, ECE
Number of Serial Input Q3 Q2 Q1 Q0
Clock Data DS
pulses
 1 1 1

2 0 01

3 1 101

4 0 0101

ii) Seial input – Serial output (SISO ) operation.

Number of Serial Input Q3 Q2 Q1 Q0

Clock Data DS
pulses

1 1 1

2 0 01

3 1 101

4 0 0101 010 01

5 0

Procedure.
1.Mode control = 0.
2.Apply clock to pin 9 –clk 1
3.Apply the serial data to be converted into serial output to DS input.
4. After 4 clock pulses the serial data appears on parallel outputs Q3Q2Q1Q0. 5.Apply another
4 clock pulses to move the data out serially at Q0 output as shown in the truth table.

iii)Parallel in Parallel output (PIPO) operation:

To perform this operation
1.Mode control = 1

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2.The parallel inputs to be loaded into shift register are given to D3 D2 D1 D0 inputs of 7495.
3.Apply a single clock pulse to pin 8 and observe the parallel data appearing on the outputs Q3
Q2 Q1 Q0 lines .

iv)Parallel in – serial output (PISO) operation:

To perform this operation

1.Load the parallel data as in step (iii).
2.Mode control = 0.
3. Change clock input to pin 9 from pin 8
4.Apply 4 clock pulses and observe the serial output data on Q0 line as shown in the table
below.
No of D3 D2 D1 D0 Q3 Q2 Q1 Q0
clock
pulses

Clock 2 1010 1010

Clock1 101 10 1

-1 2 3

b). Shift left operation.

Procedure :
1.Connect Q0 and D1 input, Q1 and D2 input ,Q2 and D3 inputs.
2.Mode control = 1.
3.Serial data to be shifted left is entered at D0 input.
4.Apply clock input to pin 8 and observe the data shifting left on Q3 line for each clock pulse.
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ECE department, BMSCE Digital Electronics Lab (15ES3GCDEC) III semester, ECE
Q3 Q2 Q1 Q0 Shift left Clock
data input
(DS)

1 11 110 1 Clock2 1

1101 1 2

0 3

1 4

74LS9
6
5 S
9 CP1 8 CP2 5D3 4D2 3D1 2D0 1 10 Q3
DS
11 Q2 12 Q1 13
Q0

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 ECE department, BMSCE Digital Electronics Lab (15ES3GCDEC) III semester, ECE

Experiment No. 10

Aim : To design and test a Ring counter / Johnson counter using 7495 I.C

a) Ring counter using 7495

Procedure: Learn the circuit

1.Mode control is made = 1.
2. A 4 bit word say 0001 is applied at the D3 D2 D1 D0 parallel inputs. 3.A single
clock pulse is applied at pin 8 to get the data on Q3 Q2 Q1 Q0 output lines 4.change
the clock to pin 9 and change the mode to 0.
5. Apply clock pulses and observe ‘1’ in the data rotating as shown in the truth
table. 6. observe the wave forms at the outputs.
clock No of clock Q3 Q2 Q1 Q0
pulses

Clock 2 Start pulse 0001 100

Clock 1 1 0 0100 00

2 10 0001 1

3 0 0 0 and so

4 on

ii) Johnson counter using 7495. Learn the circuit

Procedure:
1. Mode control is made = 1.
2. A 4 bit word say 0000 is applied at the D3 D2 D1 D0 parallel inputs. 3. A single
clock pulse is applied at pin 8 to get the data on Q3 Q2 Q1 Q0 output lines 4.Change
the clock to pin 9 and change the mode to 0.
5. Apply clock pulses and observe the outputs changing as shown in the truth table.
Also it starts repeating after 8 clock pulses .
6.Observe the wave forms at the outputs.

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 No of Outputs
clock Q3 Q2 Q1 Q0
pulses

1 0 0 0 0 1 0 0
2 0 1 1 0 0 1 1
3 1 0 1 1 1 1 0
4 1 1 1 0 0 1 1
5 0 0 0 1 0 0 0
6 0
7
8
9

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