Lecture 3

Data Preparation
VLSI Physical Design Fundamentals Course

Phil Hoang
Tresemi
Data Preparation

Logic Synthesis
▪ A crucial step that demands
proper handling before entering
the Place and Route (P&R) Gate-level
process. Netlist

▪ Errors occurring in this phase can Technology

Files
significantly impact the silicon's Data
Preparation
quality. IP Models

Timing
Constraints

Physical
Constraints

Inputs to P&R

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.2

Gate-Level Netlist
Manually Generated Constraints
create_clock –period 10 ... Gate-level Netlist is a textual description of a design circuit
module control … set_input_delay –max 1.2 ... • Functionally equivalent to RTL
input A, B, C; set_output_delay –max 2.5 ... • Described in Verilog HDL
output reg X; set_load 0.25 ...
… .....
if (A) This design abstraction
X = B | C; represents a design that
else module control … meets timing constraints with:
X = B &C; input A, B, C; • Ideal clocks
output reg X;
P&R …
• Estimated clock skews
Inputs and2 U1 (.I0(B), .I1(C), .Z(T1); • Estimated wire parasitics
or2 U2 (.I0(B), .I1(C), .Z(T2);
Gate-level
RTL Code Synthesis mux2 U3 (.S(A), .I1(T1), .I2(T2) .Z(X);
Netlist (Verilog) (Genus)
Gate-Level Netlist Structured
Technology (Verilog)
Files

IP Models

Timing Translation Mapping &

Constraints
Optimizatoin
Generic Boolean
Physical
Constraints Mapped to target technology
Logic Synthesis Optimized for timing, power, and area

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.3

P&R Tech File

P&R
Inputs

Gate-level
Netlist

Technology
Files

IP Models

Timing
Constraints

Physical
Constraints

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.4

Site
P&R
Inputs

Gate-level
Netlist

Technology
Files

IP Models

Timing
Constraints

Physical
Constraints

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.5

Interconnect Technology File

P&R
Inputs
▪ The RC tech file provides resistance and capacitance tables used
Gate-level
Netlist for RC extraction for a specific process corner.
Technology
Files

qrcTechFile_rcworst
qrcTechFile_rcbest
IP Models qrcTechFile_typical
...

Timing
Techgen
RCX Tech Files
Constraints
(binary)
Physical
Fabrication
RC
Constraints P&R
(Innovus) Extraction
Interconnect Technology Files (QRC)
(.ICT)

RC’s RC’s
(SPEF) (SPEF)

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.6

Interconnect Technology File Examples
dielectric "FOX" {
Interconnect
P&R conformal FALSE
Modeling
Inputs 22nm height 0.00

thickness 0.158
Gate-level
Netlist dielectric_constant 3.9

}
0.x/0.x
conductor "M1" {
Technology 0.xx/0.xx min_spacing 0.04275
Files min_width 0.04275
wire_top_enlargement 0.00198
wire_bottom_enlargement -0.002375
height 0.37500
thickness 0.08250
0.x/0.x rho
IP Models 0.xx/0x.x rho_silicon_widths 0.03847 0.04275 0.04703 0.05130
0.05558 0.06413 0.08550 0.12825 0.17100 0.21375 0.25650
0.29925 1.28250 1.92375 3.84750
0.x/0.x rho_silicon_thicknesses 0.05775 0.06600 0.07425 0.08250
0.09075 0.09900 0.10725 0.11550 0.12375
0.x/0.x rho_values 0.04415 0.04265 0.04147 0.04112 0.04057
Timing 0.03970 0.03862 0.03697 0.03613 0.03545 0.03500 0.03473
Constraints 0.x/0.x 0.03437 0.03431 0.03416
0.04370 0.04221 0.04105 0.04069 0.04011 0.03925
0.x/0.x 0.03813 0.03646 0.03559 0.03491 0.03447 0.03420 0.03370
0.03363 0.03349
0.xx/0x.x 0.04335 0.04188 0.04072 0.04037 0.03976 0.03891
Physical 0.xx/0x.x
0.03776 0.03607 0.03517 0.03451 0.03407 0.03380 0.03320
Constraints 0.03313 0.03299
0.xx/0x.x
0.xx/0x.x
conductor "AP" {
0.xx/0x.x min_spacing 1.71
0.xx/0x.x min_width 1.71
wire_top_enlargement -0.095
0.xx/0x.x wire_bottom_enlargement 0
0.xx/0x.x height 3.51500
thickness 2.80000
0.xx/0x.x rho
0.xx/0x.x rho_silicon_widths 1.71000 2.56500 5.13000
rho_silicon_thicknesses 1.96000 2.24000 2.52000 2.80000
0.xx/0x.x 3.08000 3.36000 3.64000 3.92000 4.20000
0.xx/0x.x 0.xx/0x.x rho_values 0.02909 0.02909 0.02909
0.02909 0.02909 0.02909
0.02909 0.02909 0.02909

Interconnect Technology File

(Cadence ICT format)

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.7

IP Models

P&R
Inputs
IO Cells
Gate-level
Netlist

Technology
Files

IP Models

Timing
Constraints

Physical
Constraints
Custom Cells/Macros

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.8

Abstraction Levels

P&R
Inputs

Gate-level
Netlist

Technology
Files

IP Models

Timing
Constraints

Physical
Constraints

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.9

Typical IP Views

▪ Behavioral
▪ FPGA
Front-End Design
▪ BIST
▪ RTL
▪ ATPG
▪ Synthesized Gate-Level
▪ Routed Gate-Level
▪ Transistor-Level
▪ Layout Back-End Design

▪ Physical Abstract
▪ Timing-Power
▪ Power Grid

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.10

Physical Abstraction

P&R SITE core

Inputs SIZE 0.140 BY 0.900 ; PIN VSS
SYMMETRY Y ; DIRECTION INOUT ;
CLASS CORE ; USE GROUND ;
Gate-level END core SHAPE ABUTMENT ;
Netlist PORT
MACRO NAND_1 LAYER M1 ;
CLASS CORE ; RECT 0.095 -0.075 0.280 0.075 ;
FOREIGN AN2D0BWP30P140 0.000 0.000 ; RECT 0.045 -0.075 0.095 0.200 ;
Technology ORIGIN 0.000 0.000 ; RECT 0.000 -0.075 0.045 0.075 ;
Files SIZE 0.560 BY 0.900 ; END
SYMMETRY X Y ; END VSS
SITE core ;
PIN VDD
IP Models PIN Y DIRECTION INOUT ;
ANTENNADIFFAREA 0.026350 ; USE POWER ;
DIRECTION OUTPUT ; SHAPE ABUTMENT ;
USE SIGNAL ; PORT LAYER M1 ;
Timing Physical Abstraction PORT RECT 0.095 0.825 0.280 0.975 ;
Constraints LAYER M1 ; RECT 0.045 0.685 0.095 0.975 ;
- Representation of layout
RECT 0.485 0.125 0.535 0.755 ; RECT 0.000 0.825 0.045 0.975 ;
for P&R purpose RECT 0.465 0.125 0.485 0.335 ; END
- Only metals are used in RECT 0.465 0.545 0.485 0.755 ; END VDD
Physical
Constraints P&R therefore the abstracts END
END Y OBS
only contain metals. The LAYER CO ;
rest of the layers are RECT 0.190 0.130 0.230 0.170 ;
PIN A
“hidden” ANTENNAGATEAREA 0.009300 ; RECT 0.190 0.715 0.230 0.755 ;
DIRECTION INPUT ; RECT 0.115 0.410 0.155 0.450 ;
USE SIGNAL ; RECT 0.050 0.125 0.090 0.165 ;
PORT RECT 0.050 0.720 0.090 0.760 ;
LAYER M1 ; END
Abstract RECT 0.095 0.320 0.155 0.555 ;
Generator END END NAND_1
(Abstract) END A

... Cell Abtract

(LEF)

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.11

Timing Abstraction

P&R
Inputs ▪ Timing models
Gate-level
specify Timing
Netlist
Arcs. There are
Technology
Files
2 types:
− Delay Arc
IP Models
− Constraint Arc
Timing
Constraints

Physical
Constraints

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.12

Non-Linear Delay Model (NLDM)

P&R ▪ xxx
Inputs
More
Gate-level details
Netlist

Technology
Files

IP Models

Timing
Constraints

Physical
Constraints

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.13

Current Source Models

▪ CCS:
P&R
Inputs
− Composite Current Source, released by Synopsys
Gate-level
▪ ECSM:
Netlist
− Effective Current Source Model, released by Cadence
Technology
Files

▪ CCS Driver Model

IP Models − captures output current flowing through
load capacitor
Timing − has to have a non-zero capacitance
Constraints
connected to the cell’s output
Physical
Constraints
▪ ECSM Driver Model
− captures voltage waveform at cell’s output
− can start with zero load capacitance
▪ Receiver Model of both models
− captures Miller capacitance of receiver
Source: Paripath with sensitivity to slope and load

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.14

Chip Physical Constraints

P&R
Inputs
▪ Chip x and y dimensions
Gate-level
Netlist
▪ Locations of the I/O pads.

Technology
Files

IP Models
Y

Timing
Constraints

Physical
Constraints

Timing
constraints were
X
covered in L2

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.15

Block Physical Constraints

P&R
Inputs
▪ PR boundary
Gate-level
Netlist
▪ Pin locations

Technology
Files

IP Models

Timing
Constraints

Physical
Constraints

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.16

Data Preparation Summary
Physical Library
P&R Logical/Timing Library
Inputs
Gate Netlist SC.lef Macro.lef Pad.lef
Gate-level SC.lib Macro.lib Pad.lib
Netlist

Technology
Files

IP Models Import P&R Tech File

Timing
Constraints
Timing
Constraints
MMMC/SDC

Physical
Constraints

Physical
Constraints,
including die size
and IO Placement Interconnect
File Technology Files
Floorplanning
(Innovus)

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.17

References

▪ CMOS VLSI Design – Weste-Harris ▪ asic back-end - https://usebackend.wordpress.com

▪ Digital Integrated Circuits – Jan Rabaey ▪ System-on-Chip Design – Anand Raghunathan
▪ 2011 Lecture Notes - David Money Harris ▪ Physical Design Flow – Mohammad Kakoee
▪ Digital VLSI Design – Adam Teman ▪ Team VLSI Blog – “teamvlsi.com”
▪ Principles of VLSI Design – Jim Plusquellic ▪ Cadence Online Support Site and YouTube Videos
▪ Digital Integrated Circuits – YuZhuo Fu ▪ Reliability of segmented edge seal ring for RF devices
- J. Gambino, et al.
▪ VLSI Back-End Adventure, ASIC Blog – “SoC
Physical Design” ▪ A Reliable I/O Ring For A Reliable SoC – Abdelliah
Bakhali
▪ VLSI Physical Design For Fresher –
“physicaldesign4u.com” ▪ Apply Wire bonding PBGA or Flip Chip PBGA? -
Fiona Zhang
▪ VLSI Begin… Blog - “vlsibegin.blogspot.com”
▪ Floorplan Strategies for Macro Dominating Blocks –
▪ SoC Physical Design – “physicaldesign- Team VLSI
asic.blogspot.com”
▪ Floorplan Guidelines for Sub-Micron Technology
▪ VLSI Expert – “vlsiexpert.com” Node for Networking Chips - Dhaval S. Shukla
▪ ASIC-System on Chip-VLSI Design – “asic- ▪ Internet search and many more…
soc.blogspot.com”
▪ From Logic to Layout – Rob Rutenbar

© Tresemi 2024 VLSI Physical Design Engineering Fundamentals p.18