1.

What is the difference between sequence_item, sequence and

sequencer?
a) A sequence item is an object that will model the information being
transmitted between two components. Sequence item is a transaction class.
b) A sequence is used to generate controlled randomized values of stimulus
with the help of constraints. i.e., sequence will generate the
sequence_items.
c) A Sequencer is a routing component used to route the sequence
items
generated by the sequence to driver.
2. What is the difference between copy and clone?
➢ Copy() method performs a deep copy of an object.

function void copy (uvm_object rhs);

do copy (rhs);

➢ Clone() method creates a new object and then does a deep copy of
an object.

virtual function uvm object clone();

3. Why $cast has to be used when copying an object using clone?
o Clone first calls create method & then copy method by which it will copy
the source object to the internal object created.
virtual function uvm object clone();

o The copied object is returned through the base class handle which has to be
assigned to the extended class handle, so we have to use Scast.
$cast (xtnh2,xtnhl.clone());
4. What is the difference between new and create?
1. Method new() is a constructor which creates objects for class handles.
drvh = new ("drvh", this);
2. Create() is a factory method which creates objects for components
and
object classes.
drvh=bus_wr driver::type_id::create("drvh",this);
Advantage of using create over new constructor is it facilitates overriding
mechanism. The methods required for overriding are defined inside
factory.
5.Can instance override and type override be used for both
uvm_component class and transaction types?
No, only uvm_component classes are part of UVM test bench hierarchy and can
be overridden on an instance granularity.
The sequence items or sequences are not a part of UVM test bench hierarchy and
hence can only be overridden using type override which will override all objects
of that type.
6. What is the command that invokes all the phases of UVM?
run_test
ex:module tb_top;
// Import UVM PKG
initial begin
run_test("ram test");
end
endmodule: tb top
7. What is the name of the instance of the test class created by
run_test?
uvm_test_top
8. What is the difference between uvm_root & uvm_top?
uvm_root is a class. and uvm_top is the reference to uvm_root. means uvm_top
is an object name of uvm_root.
class uvm root;
………..
endclass
uvm root uvm top;
during run_test, the instance of uvm_root is created and that instance name is
called uvm_top.
9. What is severity and verbosity in UVM?
In UVM, there exist 4 severity levels, which tells the importance.
UVM_INFO, UVM_WARNING, UVM_ERROR and
UVM_FATAL.
Messages in UVM can be filtered with the help of Verbosity. Different
Verbosity levels present in UVM is shown below.
verbosity value
UVM_NONE 0

UVM_LOW 100

UVM MEDIUM 200

UVM HIGH 300

UVM FULL 400

UVM DEBUG 500

Default verbosity threshold is UVM_MEDIUM.

10. Why do we encapsulate sequencer, driver and monitor in an
agent? What is the advantage of agent?
This encapsulation ensures the reusability of these components in plug and play
manner of agent because all the components present in the agent will work with a
common interface.
11. When get of Config db fails?
uvm_config_db get method will be failed in two cases.
1. When 3rd argument not matched in set and get methods.
2. When proper visibility is not provided using 2nd argument while set method
and trying to get.
uvm_config_db #(ram_config) :: set (this, "inst_path", "ram_config", tb_cfgh);
assert(!uvm_config_db #(ram_config) :: get (this, "", "ram_config", m_cgh));
12. How multiple uvm_config_db::set are resolved at the same
hierarchy level and at different hierarchy levels?
At the same hierarchy level - the last set/assignment wins
At different hierarchy level - the highest class in the hierarchy wins(typically test)
13. Can we connect multiple sequencers to a single driver?
No. Because the connection between sequencer and the driver is point-to-point
connection.
14.

15. What is the difference between get_next_item()

and try_next_item() methods in UVM driver class?
o The get_next_item() is a blocking call (part of the driver-sequencer API)
which blocks until a sequence item is available for the driver to process,
and returns a pointer to the sequence item.
o The try_next_item() is a nonblocking version which returns a null pointer
if no sequence item is available for driver to process.
16. What is the difference between get_next_item() and get()
methods in UVM driver class?
• The get_next_item() is a blocking call to get the sequence item from the
sequencer FIFO for processing by driver. Once the sequence item is
processed by a driver, it needs to call item_done() to complete the
handshake before a new item is requested using get_next_item().

• The get() is also a blocking call which gets the sequence item from
sequencer FIFO for processing by driver. However, while using get(), there
 is no need to explicitly call item_done() as the get() method completes the
handshake implicitly.
17. How get_name() differs from get_full_name() method in UVM?
a) get_name(): returns the name of the object itself, while get_full_name()
returns the full hierarchical name of the object, including the names of all
the parent objects in the hierarchy.
get_name(): drvh
b) get_full_name() : uvm_test_top.envh.agt_toph.agnth.drvh
18. Is the start() method on a sequence blocking or non-blocking?
The start() method is a blocking call. It blocks execution until the body() method
of the sequence completes execution.
19. What are pre_body() and post_body() functions in a sequence?
Do they always get called?
1. pre_body() is a method in a sequence class that gets called before
the body() method of a sequence is called. post_body() method in sequence
gets called after the body() method is called.
2. The pre_body() and post_body() methods are not always called. The
uvm_sequence::start() has an optional argument call_pre_post which if set
to 0, will result in these methods not being called.
20. What is the difference between starting a sequence using
a default_sequence and start method?
When default_sequence is set in a particular phase of the sequencer, it gets
triggered on the sequencer automatically in that phase. Using this we can only set
one sequence to drive on a sequencer.
Start method allows you to start a sequence on a sequencer and allows you to
control the order of multiple sequences - sequential or parallel.
21. What is the difference between `uvm_do and `uvm_send?
`uvm_do will create the object for item using 'uvm_create, then randomize and
then send the data to sequencer.
Whereas `uvm_send is used to send the data.
`uvm_send will NOT create or randomize while `uvm_do will do both.
22. What is a Singleton object in UVM?
The singleton object is nothing but a single object for the class. The same object
is returned even if a user tries to create multiple new objects. The class that allows
creating a single object is called a singleton class.
23. What is the difference between m_sequencer and p_sequencer?
m_sequencer is a generic uvm sequencer pointer of type uvm_sequencer_base. It
will always exist for an uvm_sequence and will point to the sequencer on which
the sequence will start.
p_sequencer will exist only when we use the 'uvm_declare_p_sequencer. The
type of p_sequencer should be mentioned through macro.
24. What is an analysis port?
Analysis port is a port that should be declared inside a component like monitor
and may be connected to zero, one or many analysis exports. By using analysis
port a non-blocking function write() will be called.
25. What are lock and grab methods in uvm sequencer?
The UVM sequencer provides the facility to have exclusive access for the
sequence to a driver via a sequencer using a locking mechanism. This locking
mechanism is implemented using lock and grab methods.
The lock and grab methods can be called using sequence handle to lock sequencer
or to grab sequencer. By using lock and grab methods sequencer arbitration
scheme can be changed.
The lock() and grab() calls have antidote calls to release a lock and these are
unlock and ungrab.
26. What are the benefits of using UVM?
Some of the benefits of using UVM are :
Modularity and Reusability – The methodology is designed as modular
components (Driver, Sequencer, Agents , env etc) which enables reusing
components across unit level to multi-unit or chip level verification as well as
across projects.
Separating Tests from Testbenches – Tests in terms of stimulus/sequencers are
kept separate from the actual testbench hierarchy and hence there can be reuse of
stimulus across different units or across projects
Simulator independent – The base class library and the methodology is supported
by all simulators and hence there is no dependence on any specific simulator
Better control on Stimulus generation – Sequence methodology gives good
control on stimulus generation. There are several ways in which sequences can be
developed which includes randomization, layered sequences, virtual
sequences etc which provides a good control and rich stimulus generation
capability.
Easy configuration – Config mechanisms simplify configuration of objects with
deep hierarchy. The configuration mechanism helps in easily configuring
different testbench components based on which verification environment uses it
and without worrying about how deep any component is in testbench hierarchy
Factory mechanism – Factory mechanisms simplifies modification of
components easily. Creating each components using factory enables them to be
overridden in different tests or environments without changing underlying code
base
27. can we use set_config and get_config in sequence?
set_config_* can be used only for the components not for the sequences. By
using configuration you can change the variables inside components only not in
sequences.
So from the sequence, using the sequencer get_config_* methods, sequence
members can be updated if the variable is configured