DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

VLSI DESIGN and Testing (21EC63)

Module 1 Introduction
The first integrated circuit was flip-flop with two transistors built by Jack Kilby at Texas
Instruments in the year 1958. In the year 2008, Intel’s Itanium microprocessor contained more than 2
billion transistors and a 16 Gb Flash memory contained more than 4 billion transistors. So in the range
of over 50 years there is the growth rate is around 53%. This incredible growth has come from steady
miniaturization of transistors and improvements in manufacturing processes. As transistors became
smaller, they also became faster, dissipate less power, and are got cheaper to manufacture. The memory
once needed for an entire company’s accounting system is now carried by a teenager in her iPod.
Improvements in integrated circuits have enabled space exploration, made automobiles safer and more
fuel efficient, revolutionized the nature of warfare, brought much of mankind’s knowledge to our Web
browsers, and made the world a flatter place.

• During the first half of the twentieth century, electronic circuits used large, expensive, power-
hungry, and unreliable vacuum tubes.
• In 1947, John Bardeen and Walter Brattain built the first functioning point contact transistor at Bell
Laboratories, shown in Figure 1.1(a).
• Later it was introduced by the Bell Lab and named it as Transistor, T-R-A-N-S-I-S-T-O- R, because it is
a resistor or semiconductor device which can amplify electrical signals as they are transferred through it
from input to output terminals.
• Ten years later, Jack Kilby at Texas Instruments realized the potential for miniaturization if multiple
transistors could be built on one piece of silicon. Figure 1.1(b) shows his first prototype of an integrated
circuit, constructed from a germanium slice and gold wires.

Fig. 1.1(a) First transistor (b) First Integrated Circuit

• Transistors are electrically controlled switches with a control terminal and two other terminals that
are connected or disconnected depending on the voltage or current applied to the control.
• After the invention of point contact transistor, Bell Labs developed the bipolar junction transistor, which
were more reliable, less noisy and more power-efficient.
Early integrated circuits used mainly bipolar transistors, which required a small current into the control
(base) terminal to switch much larger currents between the other two (emitter and collector)
terminals.

1.
 • The problem seen with bipolar transistors were the power dissipated by the base current which limited the
maximum number of transistors that can be integrated onto a single die
• Then in 1960 came Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). The advantages
seen in MOSFETs were that they draw almost zero control current while idle. It was available in 2 forms
as: nMOS and pMOS, using n-type and p-type silicon, respectively.
• In 1963, the first logic gates using MOSFETs was introduced at Fairchild. It included gates used both
nMOS and pMOS transistors. This gave the name Complementary Metal Oxide Semiconductor, or
CMOS. The circuits used discrete transistors but consumed only nanowatts of power, which was
about six times lesser than bipolar transistors.
• MOS ICs became popular because of their low cost, each transistor occupied less area and the fabrication
process was simpler. Early commercial processes used only pMOS transistors but it suffered from poor
performance, yield, and reliability. Later on Processes using nMOS transistors became common in the
1970s.
• Even though nMOS process was less expensive compared to CMOS, nMOS logic gates consumed
power while they were idle. Power consumption became a major issue in the 1980s as hundreds of
thousands of transistors were integrated onto a single die. CMOS processes were widely adopted and have
essentially replaced nMOS and bipolar processes for nearly all digital logic applications.
• In 1965, Gordon Moore observed that plotting the number of transistors that can be most economically
manufactured on a chip gives a straight line on a semi-logarithmic scale.
Also he found transistor count doubling every 18 months. This observation has bee n
called Moore’s Law.
o Fig 1.2 shows that the number of transistors in Intel microprocessors has doubled
every 26 months since the invention of the 4004.
o Moore’s Law is based on scaling down the size of transistors and to some extent
building larger chips.

Fig 1.2 Transistors in Intel microprocessors

Level of Integration:
The process of integration can be classified as small, medium, large, very large.
1. Small-Scale Integration (SSI): The number of components is less than 10 in every
package. Logic Gates like inverters, AND gate, OR gate and etc. are products of SSI
2. Medium Scale Integration (MSI): MSI devices has a complexity of 10 to 100 electronic
components in a single package. Ex: decoders, adders, counters, multiplexers, and de-

1.
 multiplexers.

3. Large Scale Integration (LSI): Products of LSI contain between 100 and 10,000 electronic
components in a single package. Ex: memory modules, I/O controllers, and 4-bit
microprocessor systems.

4. Very Large Scale Integration (VLSI): Devices that are results of VLSI contain between
10,000 and 300,000 electronic components. Ex: 8bit, 16-bit, and 32-bit microprocessor
systems.

• The feature size of a CMOS manufacturing process refers to the minimum dimension of a
transistor that can be reliably built. The 4004 had a feature size of 10μ m in 1971. The Core
2 Duo had a feature size of 45nm in 2008. Feature sizes specified in microns (10−6m), while
smaller feature sizes are expressed in nanometers (10−9 m).

MOS Transistors:
• Silicon (Si), a semiconductor, forms the basic starting material for most integrated
circuits
• Silicon is a Group IV element in periodic table, it forms covalent bonds with
four adjacent atoms, as shown in Figure 1.3(a). As the valence electrons of it are
involved in chemical bonds, pure silicon is a poor conductor.
• However its conductivity can be increased by introducing small amounts of impurities, called
dopants, into the silicon lattice.
• A dopant from Group V of the periodic table, such as arsenic, having five valence
electrons. It replaces a silicon atom in the lattice and still bonds to four neighbors, so the fifth valence
electron is loosely bound to the arsenic atom, as shown in Figure
1.3(b). Thermal vibration at room temperature is sufficient to free the electron. This
results in As+ ion and a free electron. The free electron can carry current and this is an
n-type semiconductor.

Fig 1.3 Silicon lattice and dopant atoms

• A Group III dopant, such as boron, having three valence electrons, as shown in Fig
1.3(c). The dopant atom can borrow an electron from a neighboring silicon atom, which
in turn becomes short by one electron. That atom in turn can borrow an electron, and so
forth, so the missing electron, or hole, can propagate about the lattice. The hole acts as a
positive carrier so we call this a p-type semiconductor.
• A Metal-Oxide-Semiconductor (MOS) structure is created by superimposing several
layers of conducting and insulating materials to form a sandwich-like structure.

1.
  Transistors can be built on a single crystal of silicon, which are available as thin flat
circular wafer of 15–30 cm in diameter. CMOS technology provides two types of
transistors an n- type transistor (nMOS) and a p-type transistor (pMOS).
• Transistor operation is controlled by electric fields so the devices are also called Metal
Oxide Semiconductor Field Effect Transistors (MOSFETs) or simply FETs. Cross-
sections and symbols of these transistors are shown in Figure 1.4. The n+ and p+ regions
indicate heavily doped n- or p-type silicon.

Fig 1.4 (a) nMOS transistor and (b) pMOS transistor

• Each transistor has conducting gate, an insulating layer of silicon dioxide (SiO2,
also known as glass), and the silicon wafer, also called the substrate/body/bulk. Gates of
early
transistors were built from metal, so was called Metal-Oxide-Semiconductor, or MOS.
• Even though the gate has been formed from polycrystalline silicon (polysilicon), the name
is still metal.
• An nMOS transistor is built with a p-type body and has regions of n-type semiconductor
adjacent to the gate called the source and drain. They are physically equivalent and they
can be interchangeable. The body is typically grounded.
• A pMOS transistor is just the opposite, consisting of p-type source and drain regions with
an n-type body.
• In both the gate is the control input.
• nMOS Transistor:
o It controls the flow of electrical current between the source and drain.
o Considering an nMOS transistor, its body is generally grounded so the p–n
junctions of the source and drain to body are reverse-biased. If the gate is
also
grounded, no current flows through the reverse-biased junctions and the transistor
is OFF.

o If the gate voltage is raised, it creates an electric field that starts to attract free
electrons to the underside of the Si–SiO2 interface.

1.
 o If the voltage is raised enough, the electrons outnumber the holes and a thin
region under the gate called the channel is inverted to act as an n-type
semiconductor.
o Hence, a conducting path is formed from source to drain and current can flow.
This is the condition for transistor is ON state.

o Thus when the gate of an nMOS transistor is high, the transistor is ON and there is
a conducting path from source to drain. When the gate is low, the nMOS transistor
is OFF and almost zero current flows from source to drain.

• pMOS Transistor:
o The condition is reversed.
o The body is held at a positive voltage and also when the gate is at a positive voltage,
the source and drain junctions are reverse-biased and no current flows, the transistor
is
OFF.

o When the gate voltage is reduced, positive charges are attracted to the underside of the
Si–SiO2 interface. A sufficiently low gate voltage inverts the channel and a
conducting path of positive carriers is formed from source to drain, so the transistor is
ON.
o The symbol for the pMOS transistor has a bubble on the gate, indicating that
the transistor behavior is the opposite of the nMOS.
o A pMOS transistor is just the opposite of that of nMOS. It is ON when the gate is low
and OFF when the gate is high
Transistor symbols and switch-level models is shown in Fig 1.5

Fig 1.5 Transistor symbols and switch-level models

2.
 CMOS Logic
1.Inverter

The inverter is the very important part of all digital designs. Once its operation and properties are clearly understood,
Complex structures like NAND gates, adders, multipliers, and microprocessors can also be easily done. The electrical
behavior of these complex circuits can be almost completely derived by extrapolating the results obtained for inverters.

Inverter Figure shows the schematic and symbol for a CMOS inverter or NOT gate using one nMOS transistor and one
pMOS transistor. The bar at the top indicates VDD and the triangle at the bottom indicates GND.
When the input A is 0, the nMOS transistor is OFF and the pMOS transistor is ON. Thus, the output Y is pulled up to 1
because it is connected to VDD but not to GND. Conversely, when A is 1, the nMOS is ON, the pMOS is OFF, and Y is
pulled down to ‘0.’ This is summarized in Table.

“ Input 0 makes Output 1” suggests a P-SWITCH connected from a “1” source (VDD) to the output.
“ Input 1 makes Output 0” suggests an N-SWITCH connected from a “0” source (VSS) to the output.

2.CMOS Logic Gates(NAND gate and NOR gate)

The inverter and NAND gates are examples of static CMOS logic gates, also called complementary
CMOS gates. In general, a static CMOS gate has an nMOS pull-down network to connect the output to 0
(GND) and pMOS pull-up network to connect the output to 1 (VDD), as shown in Figure 1. The networks
are arranged such that one is ON and the other OFF for any input pattern. Table 1.2 Illustrates the
realization of two input NAND gate
2.
 A B Pull-down Pull-up Output
network network
Output Output
0 0 OFF ON 1
0 1 OFF ON 1
1 0 OFF ON 1
1 1 On OFF 0

Table 1.2 NAND gate truth table

NOR gate symbol ,circuit and Truth table 1.3

Fig(a) Fig(b)

‘
2.
 A B Output
0 0 1
0 1 0
1 0 0
Table 1.3 NOR gate truth table
1 1 0

3.Combinational Logic
The pull-up and pull-down networks in the inverter each consist of a single transistor.
The NAND gate uses a series pull-down network and a parallel pullup network. More elaborate
networks are used for more complex gates. Two or more transistors in series are ON only if all of
the series transistors are ON. Two or more transistors in parallel are ON if any of the parallel

ransistors are ON. This is illustrated in Figure 1.6 for nMOS and pMOS transistor pairs. By using
combinations of these constructions, CMOS combinational gates can be constructed. Although such
static CMOS gates are most widely used, explores alternate ways of building gates with transistors.

Fig:1.6
3. Compound Gates:
A compound gate performing a more complex logic function in a single stage of logic is
formed by using a combination of series and parallel switch structures. For example, the derivation
of the circuit for the function Y = (A · B) + (C · D) is shown in Figure. This function is sometimes
called AND-OR-INVERT-22, or AOI22 because it performs the NOR of a pair of 2-input ANDs.
For the nMOS pull-down network, take the un-inverted expression ((A · B)
+ (C · D)) indicating when the output should be pulled to ‘0.’ The AND expressions (A · B) and (C

2.
 · D) may be implemented by series connections of switches, as shown in Figure 1.7(a). Now OR ing
the result requires the parallel connection of these two structures, which is shown in Figure 1.7(b).

Fig:1.7

Transistors that appear in series in the pull-down network must appear in parallel in the pull-
up network. Transistors that appear in parallel in the pulldown network must appear in series in the
pull-up network. This principle is called conduction complements and has already been used in the
design of the NAND and NOR gates. In the pull-up network, the parallel combination of A and B is
placed in series with the parallel combination of C and D. This progression is evident in Figure (c)
and Figure (d). Putting the networks together yields the full schematic (Figure (e)).

4.Pass Transistors and transmission Gates

The strength of a signal is measured by how closely it approximates an ideal voltage source.
In general, the stronger a signal, the more current it can source or sink. The power supplies, or rails,
(VDD and GND) are the source of the strongest 1s and 0s.
An nMOS transistor is an almost perfect switch when passing a 0 and thus we say it passes a
strong 0. However, the nMOS transistor is imperfect at passing a 1. The high voltage level is
somewhat less than VDD. We say it passes a degraded or weak 1.
2.
 Fig:1.
8

A pMOS transistor again has the opposite behavior, passing strong 1s but degraded 0s. The transistor
symbols and behaviors are summarized in Figure 1.8 with g, s, and d indicating gate, source, and drain.
When an nMOS or pMOS is used alone as an imperfect switch, we sometimes call it a pass transistor. By
combining an nMOS and a pMOS transistor in parallel (Figure 1.9(a)), we obtain a switch that turns on when a
1 is applied to g (Figure 1.9(b)) in which 0s and 1s are both passed in an acceptable fashion (Figure 1.9(c)).
We term this a transmission gate or pass gate. In a circuit where only a 0 or a 1 has to be passed, the
appropriate transistor (n or p) can be deleted, reverting to a single nMOS or pMOS device. Note that both the
control input and its complement are required by the transmission gate. This is called double rail logic. Some
circuit symbols for the transmission gate are shown in Figure1.9 (d).

Fig 1.9 Transmission

Gate

In all of our examples so far, the inputs drive the gate terminals of nMOS transistors in the pull-down
network and pMOS transistors in the complementary pull-up network, as was shown in Figure. Thus, the nMOS
transistors only need to pass 0s and the pMOS only pass 1s, so the output is always strongly driven and the
levels are never degraded. This is called a fully restored logic gate and simplifies circuit design considerably.

2.
5.Tristate Inverter

Table1.4

Fig 1.10

Figure 1.10 Shows symbols for tristate buffer. When the enable input EN is ‘1’,the output Y equals the input
A,just as in an ordinary buffer.When the enable is ‘0’,Y is left floating (a,’Z’ value).It is summarized in table
1.4.
Sometimes both true and complementary enable signals EN and are drawn explicitly.

Fig 1.11 Transmission Gate

Above figure Shows the transmission gate only two transistors are used but it is a non-restoring circuit.If the
input is a noisy or otherwise degraded signal, the output will receive the same noise.

Fig(a) Fig(b) Fig(c) Fig(d)

2.
 Fig:1.12 Tristate Inverter
Fig 1.12(a) shows a Tristate inverter. The output is actively driven from VDD or GND,so it is restoring logic
gate.When EN is ‘0’ Fig 1.12(b),both enable transistors are OFF,leaving the output floating. When EN is ‘1’

Fig 1.12(c),both enable transistors are ON,leaving the output floating.They are conceptually removed from their
circuit ,leaving a simple inverter. Fig 1.12(d) shows symbols for the tristate inverter. A tristate buffer can be
built as a tristate inverter following an ordinary inverter

6.Multiplexers
Multiplexers are key components in CMOS memory elements and data manipulation structures. A
multiplexer chooses the output from among several inputs based on a select signal. A 2-input, or 2:1
multiplexer, chooses input D0 when the select is 0 and input D1 when the select is 1. The truth table is given in
Table 1.5; the logic function is Y = S · D0 + S · D1.
Table 1.5

Fig:(a) Fig:(b)

Two transmission gates can be tied together to form a compact 2-input multiplexer, as shown in Figure
(a). The select and its complement enable exactly one of the two transmission gates at any given time. The
complementary select S is often not drawn in the symbol, as shown in Figure (b).

2.
7.Memory-Latches and Registers
Sequential circuits have memory: their outputs depend on both current and previous inputs. Using the
combinational circuits developed so far, we can now build sequential circuits such as latches and flip-flops.
These elements receive a clock, CLK, and a data input, D, and produce an output, Q. A D latch is transparent
when CLK = 1, meaning that Q follows D. It becomes opaque when CLK = 0, meaning Q retains its previous
value and ignores changes in D.

D latch built from a 2-input multiplexer and two inverters is shown in Figure (a). The multiplexer can be
built from a pair of transmission gates, shown in Figure (b), because the inverters are restoring. This latch also
produces a complementary output, Q. When CLK = 1, the latch is transparent and D flows through to Q
(Figure (c)). When CLK falls to 0, the latch becomes opaque. A feedback path around the inverter pair is
established (Figure (d)) to hold the current state of Q indefinitely. The D latch is also known as a level-
sensitive latch because the state of the output is dependent on the level of the clock signal, as shown in Figure
(e). The latch shown is a positive-level-sensitive latch, represented by the symbol in Figure (f ). By inverting the

2.
control connections to the multiplexer, the latch becomes negative-level-sensitive.

MOS Transistor Theory:

• MOS transistor is a majority-carrier device - current in channel between the source and
drain is controlled by a voltage applied to the gate.
o In nMOS transistor - majority carriers are electrons
o In pMOS transistor - majority carriers are holes.
• To understand the behavior of MOS transistors, an isolated MOS structure with a gate and
body but no source or drain is consider.
• It has top layer of good conducting gate layer. Middle layer is insulating oxide layer and
bottom layer is the p-type substrate i.e doped silicon body. Since it is a p-type body
carriers are holes

Fig 1.6 (a) Accumulation

• When a negative voltage is applied to the gate, the positively charged holes are attracted
to the region beneath the gate. This is called the accumulation mode shown in Fig 1.6(a)
• When a small positive voltage is applied to the gate, the positive charge on the gate repels
the holes resulting a depletion region beneath the gate as shown in Fig 1.6(b).

Fig 1.6(b) Depletion

Fig 1.6(c) Inversion

• When a higher positive potential exceeding a critical threshold voltage Vt is applied, the
holes are repelled further and some free electrons in the body are attracted to the region
beneath the gate. This results a layer of electrons in the p-type body is called the inversion
2.
 layer.

2.
 Fig 1.7 (a) nMOS demonstrating Cutoff and Linear operation
• Now considering transistor with MOS stack between two n-type regions called the source
and drain the operation is considered.

When gate-to-source voltage, Vgs is less than threshold voltage and if source is grounded,
then the junctions between the body and the source or drain are zero-biased or reverse-
biased and no current flows. We say the transistor is OFF, and this mode of operation is
called cutoff. This is shown in above fig. 1.7(a)
• When the gate voltage is greater than the threshold voltage, an inversion region of
electrons (majority carriers) called the channel connects the source and drain, creating a
conductive path and turning the transistor ON Fig 1.7(b). The number of carriers and the
conductivity increases with the gate voltage. The potential difference between drain and
source is Vds= Vgs - Vgd. If Vds = 0 (i.e., Vgs =Vgd), there is no electric field tending to
push current from drain to source. When a small positive potential Vds is applied to the
drain, current Ids flows through the channel from drain to source. This mode of
operation is termed linear, resistive, triode, nonsaturated, or unsaturated mode as
shown in Fig 1.7 (c)
• If Vds becomes sufficiently large that Vgd < Vt, the channel is no longer inverted near the
drain and becomes pinched off (Fig 1.7(d)). However, conduction is still brought about by
the drift of electrons under the influence of the positive drain voltage. Above this drain
voltage the current Ids is controlled only by the gate voltage and ceases to be influenced
by the drain. This mode is called saturation.
 Fig 1.7 (d) Saturation

Ideal I-V Characteristics:

• Considering Shockley model, which assumes the current through an OFF transistor is 0
i.e., when Vgs < Vt there is no channel and current from drain to source is 0.

• In other 2 regions (linear and saturation) channel is formed and electrons flow from source
to drain at a rate proportional to electric field (field between source and drain)
.
• If the amount of charge in the channel and the rate at which it moves is known, we
can determine the current.
• The charge on parallel plate of capacitor is given by, Q = C.V
• Here the charge in the channel is denoted by Qchannel and is given
by Qchannel = Cg . Vc
Where Cg – capacitance of gate to the channel
Vc – amount of voltage attracting charge to the channel
• If we model the gate as a parallel plate capacitor, then capacitance is given
by Area/Thickness

Fig a. Capacitance effect at the gate terminal Fig b. Transistor dimensions

• If gate is having length L and width W and the oxide thickness is tox, as shown in Fig
b, the capacitance is given by

𝐶𝑔= Ԑ𝑜𝑥 𝐿
t𝑜𝑥
Where Ԑox is the permittivity of oxide and it is 3.9 Ԑo.
Ԑo is permittivity of free space, 8.85 × 10–14 F/cm,
• Often, the Ԑox/tox term is called Cox, the capacitance per unit area of the gate oxide.
Page 17
 • Thus capacitance is now Cg = Cox W L
• Now the charges induced in channel due to gate voltage is determined by taking
the average voltage between source and drain (Fig. a) and it is given by
Vc = (Vs + Vd)/2
To form the channel and carriers to flow, the voltage condition at source and drain is as
follows:
Vs = Vgs – Vt , Vd = (Vgs – Vt) – Vds
Upon simplification, Vc is now Vc = (Vgs –Vt) – Vds/2
The plot of current and voltage i.e.,I-V Characteristics is shown in the fig.
pMOS Transistor:
pMOS transistors behave in the same way, but with the signs of all voltages and currents
reversed. The I-V characteristics are in the third quadrant, as shown in Fig.

Fig. Plot of I-V characteristics of (a) nMOS and (b) pMOS

Non ideal I-V Effects:

• The ideal I-V model does not consider many effects that are important to modern devices.
These effects are as follows:
Velocity saturation:
• Electron velocity is related to electric field through mobility by the equation
v = μ E , where E is the lateral electric field or field between drain and source.
• It is assumed that μ is constant and independent parameter w.r.t, E
• At higher E, μ is no more constant and it varies and is due to velocity saturation effect

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• When electric field reaches a critical value say Esat, the velocity of charge carriers tend to
saturate due to scattering effect at Esat. This is shown in graph below.

Page 19
 Fig. carrier velocity vs electric field
Ids depend quadratically on voltage without saturation and depends linearly when fully
saturated
• As shown in graph for short channel devices it has extended saturation region (from Esat
to Esat’) due to velocity saturation.

As channel length becomes shorter, lateral electrical field increases and transistor becomes
more velocity saturated and this decreases drain current Ids.
Mobility degradation:

• Velocity of charge carriers depend on electric field and when these carriers travel
along the length of channel, they get attracted to the surface (i.e., Gate) by the vertical
electric field (field created by gate voltage)
• Hence they bounce against the surface during their travel
• This reduces surface mobility in comparison with the mobility along the channel.
• This is known as mobility degradation and has an impact on I-V characteristics.
• As mobility decreases the current also decreases.
Channel length Modulation:
• Ideally drain current Ids is independent on Vds in the saturation region making transistor a
perfect current source.

• When Vds is increased further, near the drain barrier is build due to depletion region and
reduces the length of the channel.
• This results in reducing the length of the channel by L d. This is shown in Fig below. Thus
in saturation the effective channel length is modelled as
Leff = L - Ld

20
 Fig. Channel length modulation in saturation mode

• To avoid introducing the body voltage into our calculations, assume the source voltage is
close to the body voltage so Vdb ~ Vds. Hence, increasing Vds decreases the effective
channel length. Shorter channel length results in higher current; thus, Ids increases with
Vds in saturation
Thus as L decreases W/L ratio increases, this in turn increases Ids. Thus transistor in saturation
is no more a constant current source.
Note: Channel length modulation is important in analog designs as it reduces the gain of
the amplifier. But for digital circuits channel length modulations has no much importance.

Ԑox is the permitivity of oxide and is given by 3.9 Ԑo,

where Ԑo is the permittivity of free space = 8.825×10-14
/cm
Ԑsi is the permittivity of silicon and given by 11.7 Ԑo and Ԑo=8.825×10-14 F/cm
• Body effect parameter γ depends on doping level concentration, thus by varying
γ threshold
voltage can be varied
• Also Vt depend on Vsb thus by proving appropriate potential threshold voltage can be
varied.
• Thus a proper body bias can intentionally be applied to alter the threshold voltage,
permitting trade-offs between performance and sub threshold leakage current

Sub threshold Effects :

The threshold voltage vt increases with source voltage ,decreases with body effect, decreases with drain
voltage and increase with channel length
There are few threshold effects and it can be listed below
1.Body Effect:
• MOSFETs have 4th implicit terminal called body/substrate along with gate, source
and drain.
• The threshold voltage Vt which is assumed to remain constant is no more a constant
value and varies as potential between source and body is varied. This effect is called body
effect.
• The variation in the threshold voltage is modeled by the equation

21
 Where Vto is the threshold voltage when source and body are at same potential

Φs is the surface potential

γ is the body effect coefficient and these two are given by
Vsb is the source to body potential

υT is voltage at room temperature (υT = KT/q at 300 it is 26mV)

NA is the doping concentration level
ni is the intrinsic carrier
concentration q is charge (q = 1.6
×10-19 C) tox oxide thickness,

• The ideal I-V model assumes current flows from source to drain only when Vgs >Vt
(when gate voltage is high). But in practical transistors, current does not abruptly cut off
below threshold, but rather drops off exponentially.
• This regime of Vgs <Vt is called weak inversion/ subthreshold.
• This conduction of current is known as leakage and is undesired when the transistor is off
• The subthreshold conduction is modeled using equation given below

22
• Graph shows conduction in the subthreshold region

Fig. Subthreshold conduction

• Subthreshold conduction is useful for designing low power analog circuits and
dynamic circuits as it reduces threshold voltage and results in low power
consumptions.

Drain Induced Barrier Lowering (DIBL):

• As the drain voltage Vds is increased it creates an electric field that affects
the threshold
voltage.
• This effect is called drain-induced barrier lowering (DIBL) and this effect is
especially pronounced in short-channel transistors.
• As the channel length decreases, the DIBL effect shows up and the variation caused
in the threshold voltage can be modeled as

η is the DIBL coefficient

Junction Leakage:
• The MOS structure is considered there exists p–n junctions between diffusion and the
substrate. With CMOS structures p–n junctions between diffusion and the substrate or
well, forming diodes, as shown in Fig. The well-to-substrate junction is another
diode.

Page 14
 Fig. CMOS structure showing formation of p-n junctions between diffusion and substrate and also
between well and substrate

• The substrate and well are tied to GND or VDD so that these diodes does not get into
forward biased condition until voltage is applied in normal operation.
• But in reverse-biased conditions these diodes still conduct a small amount of
current ID. This leakage current is modeled using equation

Where, ID is the diode current

IS is the diode reverse bias saturation
current VD is the diode voltage (either Vsb
or Vdb)
• IS depends on doping levels and on the area and perimeter of the diffusion
region (geometry) and VD
•
Leakage current usually lies in the range of 0.1 – 0.01 fA/μm2, which is
negligible when compared to other leakage currents.
Tunneling (Focoler Nordheium Tunneling):
• According to quantum mechanics, for thinner gate oxides there is a nonzero probability
that an electron in the gate will find itself on the other side of the oxide, (i.e., in the region
below gate/ channel).
• This effect of carriers crossing a thin barrier is called tunneling, and results in leakage
current through the gate called gate leakage current.
• Thus gate oxide cannot be considered as an ideal insulator. This effects the circuit
functionality and increases power consumption due to static gate current.

Fig shows plot of gate leakage current density JG against voltage for different oxide
thickness. It can be observed that as oxide thickness decreases the leakage current density
increases.

Fig. plot of gate leakage current density vs voltage for different tox

• Research is going on in finding an alternate to silicon dioxide and silicon nitrate is one
contender for this.
 Note: As mobility of electrons is more than holes in silicon, tunneling current magnitude for
nMOS is more compared pMOS.
Temperature Dependence:
• Transistor characteristics are influenced by temperature
▪ Carrier mobility – decreases with temperature and this is modeled using the relation

where T is absolute temperature, Tr is room temperature, kμ is fitting constant.

▪ Threshold voltage – magnitude of threshold voltage decreases linearly with

temperature and can be modeled as

where kvt is typically about 1–2 mV/K.

▪ Junction Leakage – increases with temperature because Is (diode reverse
bias current) strongly depends on temperature
▪ Velocity saturation – occurs sooner with temperature.
▪ With increase in temperature drain current decreases with temperature when
transistor is ON and when transistor is OFF, the junction leakage and subthreshold
conduction contribute to leakage current and this increase. This condition is
shown in the graph.

▪ However, the circuit performance can be improved by providing cooling systems

like heat sinks, water cooling, thin film refrigerator and liquid nitrogen.
▪ Advantages of using at lower temperatures are
1. Leakages can be reduced
2. With lower temperature, reducing threshold voltage it can be used in
power saving
3. Most wear out mechanisms are temperature dependent and if used at
lower temp they are more reliable
Geometry Dependence:
The layout designer would draws transistors with width and length Wdrawn and Ldrawn.
▪ While mask preparation the actual gate dimensions may differ by XW and XL.
▪ While diffusion process, the source and drain would tend to diffuse laterally under
 the gate by LD, causing a smaller effective channel length that the carriers must
traverse between source and drain. Similarly, WD accounts for smaller width while
diffusion.
▪ Combing all these factors transistor, lengths and widths that should be used in
place of L and W is given by

▪ If there is variations in the length and width of the transistor there will be
variations in the performance. For example, if the currents have to be matched
then length should not be varied.

DC Transfer Characteristics
• DC transfer characteristics of a circuit relate the output voltage to the input voltage,
assuming the input changes slowly enough that capacitances have plenty of time to charge or
discharge,
CMOS Inverter Static Characteristics

Fig 1CMOS Inverter

CMOS inverter shown in Fig 1. Table below outlines various regions of operation for the n- and
p-transistors. In this table, Vtn is the threshold voltage of the n-channel device, and Vtp is the
threshold voltage of the p-channel device. Note that Vtp is negative. The equations are
given both in terms of Vgs/Vds and Vin/Vout. As the source of the nMOS transistor is grounded,
Vgsn = Vin and Vdsn = Vout. As the source of the pMOS transistor is tied to VDD, Vgsp =Vin –
VDD and Vdsp =Vout – VDD.
• The objective is to find the variation in output voltage (Vout) as a function of the input
voltage (Vin). This may be done graphically, for simplicity, we assume Vtp = –Vtn and
that the pMOS transistor is 2–3 times as wide as the nMOS transistor so βn = βp.
• The plot shows Idsn and Idsp in terms of Vdsn and Vdsp for various values of Vgsn and
Vgsp using drain current equation.
• Fig 1.10(b) shows the same plot of Idsn and |Idsp| now in terms of Vout for various values
of Vin. The possible operating points of the inverter, marked with dots, are the values of
Vout where Idsn = |Idsp| for same Vin.
• These operating points are plotted on Vout vs. Vin axes in Fig. (c) to show the inverter DC
transfer characteristics.

The supply current IDD = Idsn = |Idsp| is also plotted against Vin in Fig (d) showing that both
transistors are momentarily ON as Vin passes through voltages between GND and VDD,
resulting in a pulse of current drawn from the power supply.
• The operation of the CMOS inverter can be divided into five regions indicated on Fig
1.10(c). The state of each transistor in each region and state of output is shown in Table 2.
o In region A, the nMOS transistor is OFF so the pMOS transistor pulls the
output to VDD.
o In region B, the nMOS transistor starts to turn ON, pulling the output down.
o In region C, both transistors are in saturation.
o In region D, the pMOS transistor is partially ON
o In region E, pMOS is completely OFF, leaving the nMOS transistor to pull
the output down to GND.
 Table 2. Summary of CMOS Inverter Operation

Fig 1.10 Graphical Derivation of CMOS Inverter DC Characteristics

In the fig. the crossover point where Vin = Vout, is called the ‘input
threshold’

Fig. CMOS inverter Transfer Characteristics

Beta Ratio Effects:

• We have seen that for βn = βp the inverter threshold voltage Vinv is V DD/2. This may be
desirable because it maximizes noise margins.
• Inverters with different beta ratios βp/βn are called skewed inverters. If βp/βn > 1, the
inverter is HI-skewed. If βp/βn < 1, the inverter is LO-skewed. If βp/βn = 1, the inverter
has normal skew or is unskewed.

• A HI-skew inverter has a stronger pMOS transistor. Therefore, if the input is V DD/2, we
would expect the output will be greater than VDD/2.
• LO-skew inverter has a weaker pMOS transistor and thus a lower switching threshold.
• Figure explores the impact of skewing the beta ratio on the DC transfer characteristics. As
the beta ratio is changed, the switching threshold moves. However, the output
voltage
transition remains sharp. Gates are usually skewed by adjusting the widths of
transistors while maintaining minimum length for speed.

Fig. Transfer Characteristics of Skewed Inverters

Noise Margin:

• Noise margin is closely related to the DC voltage characteristics. This parameter allows
you to determine the allowable noise voltage on the input of a gate so that the output will
not be corrupted.
• The specification most commonly used to describe noise margin (or noise immunity) uses
two parameters: the LOW noise margin, NML, and the HIGH noise margin, NMH.
• With reference to Fig1.12, NML is defined as the difference in maximum LOW
input
voltage recognized by the receiving gate and the maximum LOW output voltage
produced by the driving gate.

• Similarly NMH is the difference between the minimum HIGH output voltage of the
driving gate and the minimum HIGH input voltage recognized by the receiving gate.

Where VIH = minimum HIGH input voltage

VIL = maximum LOW input voltage
VOH= minimum HIGH output voltage
VOL= maximum LOW output voltage
 Fig. Noise Margin Definitions
• Inputs between VIL and VIH are said to be in the indeterminate region or forbidden zone
and do not represent any legal digital logic levels. Therefore, it is generally desirable to
have VIH as close as possible to VIL and for this value to be midway in the “logic swing,”
VOL to VOH. This implies that the transfer characteristic should switch abruptly; that is,
there should be high gain in the transition region.
• DC analysis gives us the static noise margins specifying the level of noise that a gate may
see for an indefinite duration.

Pass Transistor DC characteristics:

• nMOS transistors pass ‘0’s well but 1s poorly. Figure (a) shows an nMOS
transistor with the gate and drain tied to VDD. Imagine that the source is initially at
Vs = 0.
Vgs > Vtn, so the transistor is ON and current flows. If the voltage on the source rises
to Vs = VDD – Vtn, Vgs falls to Vtn and the transistor cuts itself OFF.
• Therefore, nMOS transistors attempting to pass a 1 never pull the source above
VDD – Vtn. This loss is sometimes called a threshold drop.
• Similarly, pMOS transistors pass 1s well but 0s poorly. If the pMOS source
drops below |Vtp|, the transistor cuts off. Hence, pMOS transistors only pull down
to within
a threshold above GND, as shown in Fig (b).
• As the source can rise to within a threshold voltage of the gate, the output of
several transistors in series is no more degraded than that of a single transistor Fig
(c ).
• However, if a degraded output drives the gate of another transistor, the second transistor
can produce an even further degraded output Fig(d).
 Fig. Pass Transistor Threshold drop
• The problem seen with nMOS and pMOS of not passing strong 1’s and strong 0’s
respectively can be overcome by using Transmission gate.
• It has an nMOS and pMOS connected in parallel as shown in fig below.

Fig. Schematic and symbol of Transmission gate (TG)

 • When A is logic high both transistors are ON and TG is said to be ON. When
input is provided as nMOS is not able to transmit strong 1, pMOS will do the
function. Similarly when pMOS is not able to transmit strong 0, nMOS will do
this function.
• Thus transmission gate is able to send both strong 0 and strong 1 without any
signal degradation.
• Transmission gate can be used as
o Multiplexing element
o Analog switch
o Latch element

Fig. Resistance of Transmission gate as a function of input voltage

Tristate inverters:

• By cascading a transmission gate and an inverter forms a tristate inverter as

shown in Fig (a)
• When EN = 1, EN’= 0, thus transmission gate is ON and transmits the output Y as
 the compliment of inverter input A.
• When EN = 0 and EN’ =1, transmission gate is OFF and the output Y is in
tristate or high impedance state.
• Fig (b) and (c) shows other configurations of tristate inverters
Ratioed Inverters Transfer Characteristics
• Other than CMOS inverter there are also other forms of inverters. One
such is shown in the fig. below which has an nMOS with load as resistor.
• This is an nMOS inverter circuit. When Vin = 0, nMOS is OFF and output goes
to Vdd through the Rload.
• When Vin = 1, nMOS is ON and pulls the output to gnd.
• When we consider the transfer characteristics and I-V characteristics, we see that
as load is increased VOL decreases also the current decreases. Thus choosing load
resistor compromises between current and VOL.

Fig. nMOS inverter with resistive load, I-V characteristics and transfer characteristics

• An alternate to this is using a more practical circuit called pseudo-nMOS inverter

circuit, which uses a pMOS transistor as a load with its gate terminal
always grounded.
• Here pMOS will be in ON state. When Vin = 0, nMOS is OFF and as pMOS is
ON the output rises to Vdd. When Vin = 1, nMOS will be ON and pulls the
output to gnd.
• When the transfer characteristics is observed as the W/L ratio is varied for pMOS
in the pseudo-nMOS inverter circuit, the shape of the transfer characteristics
varies.
• As parameter P (i.e., as W is decreased sharper characteristics is obtained) is
varied characteristics varies with higher value of P less sharper characteristics is
seen.
• In the circuit P/2 represents the W/L ratio.
Fig. pseudo-nMOS inverter with I-V characteristics and transfer characteristics

• These types of gates are called as ratioed circuits as transfer function depends
on the strength of pull down (pMOS) to pull up (nMOS) devices.
• In these types of circuits ratios must be chosen properly so that circuit
operates properly.
• Disadvantage seen with these ratioed circuits are
o Constant power dissipation
o Poor noise margin
• However these circuits are used under limited circumstances such as reduced input
capacitance and smaller area.