SRM Institute of Science and Technology

College of Engineering and Technology Mode of Exam

School of Computing OFFLINE
(Common to all Branches)
DEPARTMENT OF COMPUTING TECHNOLOGIES
SRM Nagar, Kattankulathur – 603203, Chengalpattu District, Tamilnadu

Academic Year: 2023-24 (ODD)

Test: CLAT3 Date: 8.11.2023

Course Code & Title: 21CSS201T / COA Duration: 100 minutes
Year & Sem: II & III SET A Max. Marks: 50
Course Articulation Matrix:
Course
Learning At the end of this course, learners will PO PO PO PO PO PO PO PO PO PO PO PO
Outcome be able to: 1 2 3 4 5 6 7 8 9 10 11 12
s (CLO)
Analyze concepts of parallelism and - - - - - - -
CO-4 H - - - -
multi-core processors
Classify the memory technologies,
- - - - - - -
CO-5 input-output systems and evaluate the H M - - -
performance of memory system

Part – A
Instructions: Answer all (10 x 1 = 10 Marks)

Q. Question Marks BL CO PO PI
No Code
1. Pipelining increases ____________ of the processor 1 1 4 1.3 1.3.1
a. Throughput
b. Latency
c. Storage
d. Predictivity
2 operand forwarding method does the following to overcome data 1 2 4 1.3 1.3.1
dependencies

a. Introduce NULL instructions

b. Result of the instruction is written to the temporary register
c. Result of one instruction is directly sent to the next instruction for
execution
d. Blocking the execution of instructions
3 For a four-stage pipelining, the initial instruction requires _____ cycle for 1 1 4 1.3 1.3.1
execution completion?
a. 2
b. 4
c. 3
d. 1
4 When the data operands are not available then it is called ___ 1 1 4 1.3 1.3.1
a. Data hazard
b. Structural hazard
c. Control hazard
d. Instruction hazard
5 When the branch is actually not taken the state moves from ST to ____. 1 1 4 1.3 1.3.1
a. SNT
b. LT
c. LNT
d. ST
6 Which type of parallelism involves breaking down a program into 1 1 5 1 2.1.2
smaller tasks that can be executed concurrently?
A. Instruction-level parallelism
B. Data-level parallelism
C. Task-level parallelism
D. Pipeline parallelism
7 What is the primary advantage of MIMD architecture compared to 1 1 5 1 2.1.2
SISD architecture?
 A. Lower cost
B. Simplicity of programming
C. Higher processing power for parallel tasks
D. Energy efficiency
8 Which part of an ARM instruction specifies the operation to be 1 1 5 1 2.1.2
performed?
A. Opcode
B. Data register
C. Memory address
D. Condition code
9 Which part of an ARM-based system typically handles I/O 1 1 5 1 2.1.2
operations and device communication?
a) Memory unit
b) Arithmetic logic unit (ALU)
c) Input unit
d) Peripheral interface or controller
10 What is the primary advantage of the Thumb instruction set in 1 1 5 1 2.1.2
ARM7 architecture?
a. Greater computational power
b. Smaller code size
c. Enhanced multimedia capabilities
d. Improved memory management
Part – B
Instructions: Answer any 4 ( 4 x 4 = 16 Marks)

11 Design a 4-stage instruction pipeline for 3 instructions I1,I2,I3 to be 4 3 4 1.3 1.3.1

executed. Consider that there are no dependency between the
instructions.
12 Draw and explain the two state diagram for dynamic branch 4 4 4 1.3 1.3.1
prediction.
13 Interpret about out of order execution? 4 1 4 1.3 1.3.1
14 Discuss the five step Sequential execution with example 4 3 5 2 2.1.2
15 Discuss the concepts involved in ILP and how many unit of time to 4 3 5 2 2.1.2
complete the operations
x= a+b
y=c-d
z=x * y
PART C
Instructions: Answer all (12 x 2 = 24 Marks)

16. A Arun and Bob are having equal number of apples and it’s count are 12 3 4 1.3 1.3.1
stored in the register R1 and R2 respectively. Arun collected bob’s
apple and store the entire set of apples with him and update its
count in R1. Write the complete set of control sequences for the
above operation.
OR 2.1.2
16. B Illustrate the scenario where instructional hazard occurs and 12 3 4 1.3 1.3.1
provide the solution for handling the stall created by conditional
branch instruction.
17 A. Explain the various types of Parallelism. 12 3 5 2 2.1.2

OR
17 B With the evolution of computing, multi-core processors have 12 3 5 2 2.1.2
become a standard in modern computer architectures.

a. Define and differentiate between a processor and CPU cores.

(4 marks)
b. Discuss the advantages and potential challenges of multi-core
processors compared to single-core processors. (6 marks)
c. Explain how software developers might need to adapt their
 programming techniques to fully utilize the capabilities of
multi-core processors. (2 marks)

*Performance Indicators are available separately for Computer Science and Engineering in AICTE examination reforms
policy.

Course Outcome (CO) and Bloom’s level (BL) Coverage in Questions

Approved by the Audit Professor/Course Coordinator