+

Flip-Flops

8
OBJECTIVES
+Describe the operation of the basic RS flip-flop and explain the purpose of the
additional input on the gated (clocked) RS flip-flop
Show the truth table for the edge-triggered. RS flip-flop, edge-triggered D flip-flop,
and edge-triggered jK flip-flop
Discuss some of the timing problems related to flip-ilops
Draw a diagram of a JK master-slave flip-flop and describe its operation
State the cause of contact bounce and describe a solution for this problem
Describe characteristic equations of Flip-Flops and analysis techniques of sequential
Circuit
Describe excitation table of Flip-Flops and explain conversion of Flip-Flops as synthesis
example

ne outputs of the digital circuits considered previously are dependent entirely on their inputs. That is, it

input changes state, output may also change state. However, there are requirenents for a digital device
Ciruit whose output will remain unchanged, once set, even if there is a change in input levels). Such
device could be used to store a binary number. A flip-flop is one such circuit, and the characteristics of
he used in digital systems are considered in this chapter. Flip-tlops are
St Common of
types flip-flops
construction of registers and counters, and in numerous other applications. The elimination ot
bounce is a clever application utilizing the unique operating eharacteristies of tlip-tlops. In a
Contact
of such circuits are done through
ogic circuit flip-flops serve as key memory elements. Analysis
fe 1 C S or characteristic equations of flip-flops. The analysis result is normally presented through state
 Digital Principles and Applications
284
Conversion of flip-flop from one kind to
table state transition diagram through timing diagram.
and also
or
tables are very useful.
where flip-flop excitation
another can be posed as a synthesis problem

8.1 RS FLIP-FLOPs
a toggle switch has two
to be bistable. For instance,
device circuit that has two stable states is said
switch as shown in Fig. 8.la. The switch
or
Any on the position ofthe
stable states. It is either up or down. depending
s o m e o n e changes its position.
Is also said to have memor
since it will remain as set unti1l
states-that is, its output is either 0 or +5
circuit that has two stable
A fip-flop is a bistable electronic
will remain as set until something
also has memory since its output
Vdc as shown in Fig. 8.1b. The flip-flop device. In fact, any
it. As such, the flip-flop (or the switch) can be regarded as a memory
is done to change For instance, when the flip-flop has its output
set
bistable device can be used to store one binary digit (bit). 1. The
a logic 0 and when its output
is set at +5 Vdc, as storing a logic
at 0 Vde. it can be regarded as storing
will hold, or latch, in either stable state.
flip-flop is often called a latch, since it
+VcC +Vcc
-V cC VCC Output Output
+
Output Output Vdc +5 Vde

State 1 State 0 State 1

State 0
(a) Toggle switch (b) Flip-flop

Fig. 8.1 Bistable devices

Basic Idea
Ihe
One of the easiest ways to construct a flip-flop is to connect two inverters in series as shown in Fig. 8.2a.
the
line connecting the output of inverter B (INV B) back to the input of inverter A (INV A) is referred to as
feedhack line.
For the moment, remove the feedback line and consider V as the input and V3 as the output as show
Fig. .2b. There are only two possible signals in a digital system, and in this case we will detine L=0
Vdc and //- 1 - +5 Vde. If V, is set lo 0 Vdc, then V will also be 0 Vde. Now, if the feedback line shown m
Fig. K.2b is reconnected, theground can be removed from i, and Vi, will remain at 0 Vde. This is true sinee
once thc input of INV A is grounded, the output of INV B will go low and can then be used to hold the inpt
of INVA low by using the feedback line. This is one stable state = O Vde.
Conversely, if V is t+5 Vdc, will also be 15 Vde as seen in Fig. 8.2c. The feedback
V line can again De
used to hold Vi at +5 Vde since V, is also at 15 Vde. This is then the second stable state + 5 Vde

NOR-Gate Latch
The basic flip-flop shown in F1g. 8.2a can be improved by replacing the inverters with either NAND or N R
gales. The additional inpuls 0n these gales provide a convenient means for application of input signais
 Flip-Flops 285
Feedback line

Vi
INV AO- HINV B-

(a) Bistable circuit

V0 Vdc V,=+5 Vdc V =0 Vdc

INVAO- INV B o

(b)

V=+5Vdc V2 =0 Vde V = +5 Vdc

+Vcc- INVA- INV B o

(c)

Fig. 8.2 Bistable circuit

switch the fip-flop from one stable state to the other. Two 2-input NOR gates are connected in Fig. 8.3a to
form a flip-flop. Notice that if the two inputs labeled R and S are ignored, this cireuit will function exactly as
the one shown in Fig. 8.2a.

V=Q
NOR A

R
S
NOR A S
NOR B
NOR B

(a) (b)

OFig. 8.3 NOR-gate flip-flop

flip-tlop actually
8.3b. The has two outputs,
his circuit is redrawn in a more conventional form in Fig.
Chined in more general terms as Qand O. It should be clear that regardless of the value of Q, its complement
.There are two inputs to the flip-flop defined as R and S. The input/output possibilities for this RS tlip-
To aid in understanding the operation of this cireuit, recall
Op are summarized in the truth table in Fig. 8.4. =0.
dl an
l at any input of a NOR gate forces its outputto anlL
0 and S= 0. Since a 0 at the input of a NOR gate has
The first input condition in the truth table is R=
remains in i1s present state; that is, Qremains unchanged.
nocffect on its output, the flip-flop simply lorces the oI NOR gate B low. Both inputs to NOR
The second input condition R =0 and S=| output
must be high. t hus a
l at the S input is said to SET the
gate A are now low, and the NOR-gate oulput
where Q=
p-flop, and it switches to the stablestate
 Digital Principles and Applications
286
The third input condition is R = 1 and S = 0. This
R S Action
condition forces the output of NOR gate A low, and
0 0 Last No change
since both inputs to NOR gate B are now low, the state
output must be high. Thus a I at the R input is said 1 SET
to RESET theflip-flop, and it switches to the stable
RESET
state where Q = 0 (or Q =1).

4 The last input condition in the table, R =

1 and S =
1 2 Forbidden
1, is forbidden, as it forces the outputs of both NOR
OFig. 8.4 Truth table for a NOR-
gates to the low state. In other words, both Q =0 gate RS flip-flop
and =0 at the same time! But this violates the
basic definition of a flip-flop that requires Q to be
the complement of Q, and so it is generally agreed never to impose this input condition. Incidentally
i fthis condition is for some reason, imposed and the next input is R = 0, S=0 then the resulting state

depends on propagation delays of two NOR gates. If delay of gate A is less, i.e. it acts faster, then
Q 1 else it is 0. Such dependence makes the job of a design engineer difficult, as any replacement
of a NOR gate will make Q unpredictable. That's why R = 1, S= l is forbidden and truth table entry
is ?.This R = 0, S= 0 imposition after R = 1, S I can also lead to what is known as metastability i.e.
output is at neither of stable high or low state. From metastable state it can go into any of the stable
state depending on other factors but that cannot be fully factored into design.
It is also important to remember that TTL gate inputs are quite noise-sensitive and therefore should
never be left unconnected (floating). Each input must be connected either to the output of a prior
circuit, or ifunused, to GND or +Vcc:

Example 8.1 Use the pinout diagram for a 54/7427 triple 3-input NOR gate and show how to connect d

simple RS flip-flop.

Solution One possible arrangement is shown in Fig. 8.5. Notice that pins 3 and 4 are tied together, as are pins I0
and 11; thus no input leads are left unconnected and the two gates simply function as 2-input gates. The third NOK

gate is not used. (It can be a spare or can be used elsewhere.)

54/7427

14 +Vcc
2 13
S 3
12
R

10
9

Fig. 8554/7427
 Flip-Flops 287
The standard logic symbols for an RS flip-flop are shown in Fig. 8.6 along with its truth table. The truth
table is necessary since it describes exactly how the flip-flop functions

R S 2
0 0 Last state
S
0 1
10 0
IEEE symbol
12(Forbidden)
Logic symbol
(a) (b) Truth table

OFig. 8.6 RS flip-flop

NAND-Gate Latch
A slightly different latch
can be constructed by using NAND
gates as shown in Fig. 8.7. The truth table for
thisNAND-gate latch is different from that for the NOR-gate latch. We will call this latch an RS
To understand how this circuit
flip-flop.
functions, recall that a low on any input to a NAND gate will force its output
high. Thus a low on the S input will set the latch (Q = 1 and Q = 0). A low on the R input will reset it
Q 0). If both R and S are high, the flip-flop will remain in its previous state. Setting both R and S low
simultaneously is forbidden since this forces both Q and Q high.

3-S -e

R-R R Q
IEEE symbol Last state

0 0
0 0 (Forbidden)
R- R
Logic symbol
(a) NAND gate latch (b) (c) Truth table

Fig. 8.7 RS flip-flop

Example 8.2 Show how to convert the RS Aip-flop in Fig. 8.7 into an RS Hip-tlop.
uOBy placing an inverter at each
input as shown in Fig. 8.8, the 2 inputs are now R and S, and the resulting
Dchaves exactly as the RS flip-flop in Fig. 8.6. A single 54/7400 (quad 2-input NAND gate) is used.
nple latches as discussed in this section can be constructed from NAND or NOR gates or obtained as medium-
Cnlegraled circuits (MSI). For instance, the 741S279 is a quad RS lateh. The pinout and truth table for this
Circuit
RS
are given in Fig. 8.9. Study the truth table carefully, and you will see that the latches behave exactly ike the
fip-flop discussed above.
 Digital Principles and Applications
288
12
11 S 9
10
R S
00 Last state

0 0
3R 1 1 2(Forbidden)
K R
(a) 54/7400 (b) Logic symbol (c)

OFig. 8.8 An RS flip-flop (latch)

Vcc S R S S, R Q
16 15 14 1312 1O P

S R
0 0 0 ? Forbidden
0 X I |1
X0 1 |1
0 0

1 ? Forbidden
S R S GND X= Don't care
(a) Pinout 74S279A (b) Truth table

Fig. 8.9 Quad SET-RESET latch

The NOR-gate flip-flop in Fig. 8.3 is seen to be
S
an active-high circuit because an f= I at eitherthe S
orP input is required to change the output Q. On the
other hand, the NAND-gate flip-tlop in Fig. 8.7 can
be considered an active-low circuit because an , = 0
at either input is required to change 0. The NAND
gates in Fig. K.7 can be changed to bubbled-input OR
gates as shown in Fig. B.10. This circuit is equivalent R
to the NAND-gate latch in Fig. 8.7 and functions in
RS lip-tlop
cxactly the same way. 1lowever, the bubbled inputs
morc clearly express circuit operation
OFig. 8.10 Bubbled OR-gate equivalent o
Fig. 8.7

SELF-TEST

What do the letters R and Sstand for in the tem "RS latch"?
2. A 741LS279 is a quad latch. What does quad mean?
3. Why is the NAND-gate latch considered active-low?
 Flip-Flops 289
8.2 GATED FLIP-FLOPS
Twodifferent methods for constructing an RS flip-flop were discussed in Sec. 8.1. The NOR-gate realization
in Fig. 8.3b is an exact cquivalent of the NAND-gate realization in Fig. 8.8a, and they both have the exact
same symbol and truth table as given in Fig. 8.6. Both of these RS flip-flops, or latches, are said to be
ransparent; that is, any change in input information at R or S is transmitted immediately to the output at Q
and Q according to the truth table.

Clocked RS Flip-Flops
The addition of two AND gates at the R and S inputs as shown in Fig. 8.11 will result in a flip-flop that can be
enabled or disabled. When the ENABLE input is low, the AND gate outputs must both be low and changes in
neither R nor S will have any efiect on the flip-flop output Q. The latch is said to be disabled.
When the ENABLE input is high, information at the R and S inputs will be transmitted directly to the
outputs. The latch is said to be enabled. The output will change in response to input changes as long as the
ENABLE is high. When the ENABLE input goes low, the output will retain the information that was present
on the
input when the high-to-low transition took place.
In this fashion, it is possible to strobe or clock the flip-flop in order to store information (set it or reset it) at
any time, and then hold the stored information for any desired period of time. This flip-flop is called a gated
or clocked RSfip-flop. The proper symbol and truth table are given in Fig. 8.11b. Notice that there are now
three inputs-R, S, and the ENABLE or CLOCK input, labeled EN. Notice also that the truth-table output is
not simply Q, but Q,- |. This is because we must consider two different instants in time: the time before the
ENABLE goes low Q, and the time just after ENABLE goes low Q-1. When EN = 0, the fip-flop is disabled
and R and S have no effect; thus the truth table entry for R and S is X (don't care).

Example 8.3 Explain the meaning of Q, the truth table in Fig. 8.11b.

EN S R
I0 0Q, (no change)
s -o
ENABLE- EN 0
R -

R
I| (legal)
0 XA , (no change)
(b) IEEE Synmbol and truth table
(a) Logic diagram
OFig. 8.11 Clocked RS lip-ílop

Solu
otution For the flip-flop to operate properly, there must be a PT on the EN input While EN is high, the intormation
R and S causes the latch to sct or reset. Tlhen when EN transitions back to low, this iniormation is tetained m the
latch, When this NT occurred, both K and S inputs were low (0), and thus there was no change ofstate. In other w ords,
theC vvalue of at time n t 1 is the same as it was at time n. Remember that time n oceurs just betore the NT on EN.
dil
inen t1, occurs just after the transition.
The logic diugrams shown in Fig. 8.12a and b illustrate Iwo diflerent nethods for realizing a elock RS lip-tlop.
Ohrealizations are widely used in medium- and large-seale integrated circuits, and you will tind them easy to
CCOgnize. You might like to examine the logic diagrans lor a 54LS109 ora 54LS74, for instance
 Digital Principles and Applications
290

EN- EN

R
R-
(a) (b)

Two different realizations for a clocked RS flip-flop

Fig. 8.12
Figure 8.13 shows the input waveforms R, S, and EN applied to a clockedRS fip-fop. Explain
Example 8.4
the output waveform Q.

g
Time

EN
0

R
0

Fig. 8.13 Input waveform R, S, EN applied to a clocked RS flip-flop

Solution Between t2 and t both R and S change states, but since EN is low, the fip-flop is still disabled and

remains at I.

Betweenf and f6, the fip-flop will respond to any change in R and S since EN is high. Thus at /s Q goes low.at
at i4 it goes back high. No change occurs at 15. At t, the value Q= I is latched and no changes in Q oceur betc
and 7 even though both R and S change.
Between t7, and Iy no change in Q occurs since both R and S are low. Initially, the tlip-flop is reset (O=0).At
EN goes high; the fip-flop is now enabled, and it is immediately set (Q= 1)sinceR = 0 and S= 1. At tumeig
goes low and the flip-flop is disabled and latches in the stable state Q= 1.

Clocked D Flip-Flops
The RS fip-flop has two data inputs, k and S. To store a high bit, you need a high S; to store
you need a high R. Generation of two signals lo drive a flip-tlop is a disadvantage in many appe
Furthermore, the forbidden condition oflboth R and S high may occur inadvertently. This has leu

fiip-flop, a circuit that needsonly a single datainput

Figure 8.14 showsa simple way to build a D(Data) lip-flop. This lip-flop is disabledwhen EN
buth
is fransparent when EN is high. The action of the circuit is straightforward, as follows. When EN S d
hand

AND galcs are disabled; therefore, can change value without allecting the value ot (). On the
 Flip-Flops 291
when EN is high, both AND gates are enabled. In this case, Q
D
is forced to cqual the value of D. When EN again goes low, Q
retains or stores the last value of D. EN
There are many ways to design D flip-flops. In general, a D
fip-flop is a bistable circuit whose D input is transferred to the
output when EN is high. Figure 8.15 shows the logic symbols
used for any type of D flip-flop. Fig. 8.14 AD Flip-flop
In this section we're talking about the kind of D flip-flop in
which Q can follow the value of D while EN is high. In other words, if the data bit changes while EN is high.
value of D before EN return low is the value of D that is stored. This kind ofD fip-flop is often called
aD latch.
Figure 8.15b shows the truth table for a D latch. While (EN) is low, D is a don't care (X): Q will remain
latched in its last state. When EN is high, Q takes on the last value of D. If D is changing while EN is high.
it is the last value of D that is stored.

EN D -1
D
D
EN EN 0 X 2 , (last state)
0

IEEE symbol Logic symbol

(a) D flip-flop logic symbol (b) Truth table

Fig. 8.15 DFlip-flop logic symbol

The idea of data storage is illustrated in Fig. 8.16. D3 D D Do
Four D latches are driven by the same clock signal. Clock
When the clock goes high, input data is loaded into the
fiip-flops and appears at the output. Then when the clock D EN D EN D END EN
goes low, the output retains the data. For instance, sup-
pose that the data input is

D3D,D, Do =
0111
When the clock goes high, this word is loaded into
theDlatches, resulting in an output or

03001Qo =0111 Fig.Fig. 8.16 Storing a 4-bit word

Aller the clock goes low, the output data is retained

Or stored. As long as the clock is low, the D values can change without affecting the Q values.
The 7475 in Fig. 8.17 is a TTL MSI cireuit that contains four D latches; it's called a quad bistable latch.
e /475 is ideal for handling 4-bit nibbles of data. If more than one 7475 is used, words of any length can
be stored.

truth table?
OSELF-TEST
W h a t does an entry Xmean in a flip-flop
. What could you do to disable the flip-flop in Fig. 8.11?
. Which flip-flop is easier to use, the RS of the D, as a clocked or gated latch to store data?
292 Digital Principles and Applications

+Vcc
3D 2
D D, Do 4
EN I
7475
GND EN 2 13
12
, lI 14
15 14 16
16 1
10
(a)
EN D

(6)
Fig. 8.17 4-bit bistable latch: (a) Pinout, (b) Logic diagram (each latch)