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9 to 11 DSP Manuals

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13 views7 pages

9 to 11 DSP Manuals

Uploaded by

anujaryavart
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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PSIT-Pranveer Singh Institute of Technology

National Highway (NH-19), Bhautipratappur, Kanpur-209305 (U.P.), India

Experiment No. 10
AIM: To study about DSP Processors and architecture of TMS320C6713 DSP processor.
APPARATUS USED: DSP Processor KIT.
THEORY:
The Texas Instruments TMS320C6713 Starter Kits are low cost development platforms for real -
time digital signal processing applications. The kits comprises a small circuit board containing
aTMS320C6713floating –point digital signal processor and connects to a host PC via a USB port.
PC software in the form of Code Composer Studio (CCS) is provided in order to enable software
written in C or assembly language to be compiled and/or assembled, linked, and downloaded to run
on the DSK.
Diagrams of TMS320C6713 DSK

Features
The DSK comes with a full complement of on-board devices that suit a wide variety of application
environments. Key features include:
 A Texas Instruments TMS320C6713 DSP operating at 225 MHz
 An AIC23 stereo codec
 16 Mbytes of synchronous DRAM
 512 Kbytes of non-volatile Flash memory (256 Kbytes usable in default
configuration)
 4 user accessible LEDs and DIP switches

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING 35


PSIT-Pranveer Singh Institute of Technology
National Highway (NH-19), Bhautipratappur, Kanpur-209305 (U.P.), India

 Software board configuration through registers implemented in CPLD


 Configurable boot options
 Standard expansion connectors for daughter card use
 JTAG emulation through on-board JTAG emulator with USB host interface or
external emulator
 Single voltage power supply (+5V)
Architecture
The simplified architecture of TMS320C6713 is shown in the Figure below. The processor consists
of three main parts: CPU, peripherals, and memory.

Central Processing Unit


The CPU contains program fetch unit, Instruction dispatch unit, instruction decode unit.The CPU
fetches advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit
instructions to the eight functional units during every clock cycle. The VLIW architecture features
controls by which all eight units do not have to be supplied with instructions if they are not ready
to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the
same execute packet as the previous instruction, or whether it should be executed in the following
clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the
execute packets can vary in size. The variable-length execute packets are a key memory-saving
feature, distinguishing the C67x CPU from other VLIW architectures. The CPU also contains two
data paths (Containing registers A and B respectively) in which the processing takes place. Each
data path has four functional units (.L, .M, .S and .D).

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING 36


PSIT-Pranveer Singh Institute of Technology
National Highway (NH-19), Bhautipratappur, Kanpur-209305 (U.P.), India

The functional units execute logic, multiply, shifting and data address operation. Below Figure
shows the simplified block diagram of the two data paths.

All instructions except loads and stores operate on the register. All data transfers between the
register files and memory take place only through two data-addressing units (.D1 and .D2). The
CPU also has various control registers, control logic and test, emulation, and logic. Access to
control registers is provided from data path B.
General Purpose Register Files
The CPU contains two general purpose register files A and B. These can be used for data or as data
address pointers. Each file contains sixteen 32-bit registers (A0-A15 for file A and B0-B15 for file
B). The registers A1, A2, B0, B1, and B2 can also be used as condition registers. The registers A4-
A7 and B4-B7 can be used for circular addressing.
These registers provide 32-bit and 40-bit fixed-point data. The 32-bit data can be stored in any
register. For 40-bit data, processor stores least significant 32 bits in an even register and remaining
8 bits in upper (odd) register.

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING 37


PSIT-Pranveer Singh Institute of Technology
National Highway (NH-19), Bhautipratappur, Kanpur-209305 (U.P.), India

Experiment No. 09
AIM: To implement floating point arithmetic.
SOFT WARE USED: MATLAB R2013a
THEORY: Floating-point arithmetic involves representing real numbers in a way that can
accommodate a wide range of values while balancing precision and range. Here's a breakdown of the
concepts and an example implementation in MATLAB.
Key Concepts of Floating-Point Arithmetic
1. Representation:
o A floating-point number is typically represented as:
x=(−1)^sign×mantissa×2^exponent
o The sign bit indicates positive or negative.
o The mantissa represents the significant digits.
o The exponent determines the scale.
2. Precision Issues:
o Due to limited bits for the mantissa and exponent, certain numbers cannot be
represented exactly, leading to rounding errors.
3. Operations:
o Basic arithmetic operations (addition, subtraction, multiplication, and division) can
introduce errors, especially when dealing with very large or very small numbers.

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING 38


PSIT-Pranveer Singh Institute of Technology
National Highway (NH-19), Bhautipratappur, Kanpur-209305 (U.P.), India

RESULT: - Thus, we implement floating point numbers.


PRECAUTION: -
1. Write correct syntax.
2. Numbers should be inserted properly.
3. Save the .m-File format

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING 39


PSIT-Pranveer Singh Institute of Technology
National Highway (NH-19), Bhautipratappur, Kanpur-209305 (U.P.), India

Experiment No. 11
AIM: To verify the zero-padding used for better resolution in discrete Fourier transform.
SOFT WARE USED: MATLAB R2013a
THEORY:
Zero Padding refers to the operation of extending a signal length by appending zeros samples to the
given signal. The zero padding gives us a High-density spectrum and provides a better displayed
version for plotting.
e.g. the given signal

Let’s appending four zeros to the given signal

If we increase the number of points between 0 and 2 we can obtain a better representation of
magnitude and phase response.
Example
Find the DFT of the signal

For N=4, N=8 and N=32.


MATLAB Code

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING 40


PSIT-Pranveer Singh Institute of Technology
National Highway (NH-19), Bhautipratappur, Kanpur-209305 (U.P.), India

RESULT: - Thus, we implement zero padding and its effects.


PRECAUTION: -
4. Write correct syntax.
5. Save the .m-File format.

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING 41

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