Introduction to Verilog HDL

Verilog
1
 Hardware Description Language (HDL)
․High-Level Programming Language
․Special constructs to model microelectronic circuits
 Describe the operation of a circuit at various levels of abstraction
 Behavioral
 Functional (Register Transfer Level)
 Structural
 Express the concurrency of circuit operation
 Serve as input to synthesis

Verilog 2
 Major HDLs
․Verilog HDL
 Started by Gateway in 1984
 Became open to public by Cadence in 1990
 IEEE standard 1364 in 1995
 Slightly better at gate/transistor level
 Language style close to C/C++
 Pre-defined data type, easy to use
․VHDL
 Started by VHSIC project in 1980s
 IEEE standard 1076 in 1987, IEEE 1164 in 1993
 Slightly better at system level
 Language style close to Ada/Pascal
 User-defined data type, more flexible
․Equally effective, personal preference

Verilog 3
 Why HDL
․Facilitate a top-down design methodology using synthesis
 Design at a high implementation-independent level
 Delay decision on implementation details
 Easily explore design alternatives
 Automatically map high-level description to a technology-specific
implementation
․Provides greater flexibility
 Reuse earlier design components
 Move designs between multiple vendors and tools

Verilog 4
 Typical Design Flow

Design Specification Floorplanning

Automatic Place & Route

Behavioral Description
Physical Layout

RTL Description
Post-Layout Simulation

Functional Simulation
Layout Verification
(DRC, LVS,…)
Logic Synthesis

Implementation
Gate-Level Netlist

Pre-Layout Simulation

Verilog 5
 Verilog-Supported Levels of Abstraction

․Behavioral
 Describes a system by the flow of data between its functional blocks
 Defines signal values when they change
․Functional or Register Transfer Level (RTL)
 Describes a system by the flow of data and control signals between
and within its functional blocks
 Defines signal values with respect to a clock
․Structural
 Describes a system by connecting predefined components
 Uses technology-specific, low-level components when mapping from
an RTL description to a gate-level netlist, such as during synthesis.

Verilog 6
 Block Diagram & Schematic

a sum
b Add_half c_out

block diagram

a
sum
b

c_out_bar

c_out

schematic

Verilog 7
 Modules

․A module is the basic building block in Verilog

 Every module starts with the keyword module, has a name, and ends
with the keyword endmodule
․A module can be
 A design block
 A simulation block, i.e., a testbench

module add_1 (. . .);

. . .
. . .
endmodule

Verilog 8
 Module Ports

․Module ports describe the input and output terminals of a

module
 Listed in parentheses after the module name
 Declared to be input, output, or inout (bi-directional)

module add_1 (sum, a, b, c_in, c_out);

output sum;
input a;
input b;
input c_in;
output c_out;

// output sum, c_out;

// input a, b, c_in;
. . .
. . .
endmodule
Verilog 9
 Structural Level Description
module name module ports

module Add_half (sum, c_out, a, b);

input a, b; declaration of port modes
output sum, c_out;
wire c_out_bar; declaration of internal signal

xor (sum, a, b);

nand (c_out_bar, a, b); instantiation of primitive gates
not (c_out, c_out_bar);
endmodule

Note: All bold-faced items are Verilog keywords

Verilog 10
 Predefined Primitives

․Combinational logic gates

 and, nand
 or, nor

 xor, xnor

 buf, not

Verilog 11
 Full Adder
Add_full

c_in a sum sum

Add_half
a a sum b c_out
Add_half c_out
b b c_out

module Add_full (sum, c_out, a, b, c_in); //parent module

input a, b, c_in;
output c_out, sum;
wire w1, w2, w2; module instance name

Add_half M1 (w1, w2, a, b); //child module

Add_half M2 (sum, w3, w1, c_in); //child module
or (c_out, w2, w3); //primitive instantiation
endmodule

Verilog 12
 Hierarchical Description

Add_full

M1 M2
Add_half Add_half or

xor nand not xor nand not

Nested module instantiation is the mechanism for

hierarchical decomposition of a design

Verilog 13
 RTL Level Description
․An RTL model provides sufficient architectural details that a
synthesis tool can construct the circuit

module add_1 (sum, a, b, c_in, c_out);

output sum, c_out;
input a, b, c_in;

assign {c_out, sum} = a + b + c_in;

endmodule

Verilog 14
 The Behavioral Level

․Describes the behavior of a design without implying any

specific internal architecture
 High level constructs, such as @, case, if, repeat, wait, while, etc
 Testbench
 Limited support by synthesis tools
․The difference between a behavioral model and an RTL
model and an RTL model is not always clear
 whether synthesizable or not

Verilog 15
 Behavioral Level Description

module Add_half (sum, c_out, a, b);

input a, b;
output sum, c_out;
reg sum, c_out;

always@(a or b)
begin
sum = a ^ b; //exclusive or
c_out = a & b; //and
end
procedural statements
endmodule

Verilog 16
 Behavioral Description of D F/F

module Flip_flop (q, data_in, clk, rst);

input data_in, clk, rst;
rst output q;
data_in q reg q;

clk declaration of
always @ (posedge clk) synchronous
begin behavior
if(rst == 1) q=0;
block
else q = data_in;
diagram
end
endmodule

Verilog 17
 Variables
․Nets “wire”: structural connectivity
․Registers “reg”: abstraction of storage (may or may
not be physical storage)
․Both nets and registers are informally called signals,
and may be either scalar or vector

Verilog 18
 Logic Values
․Verilog signal values
 0: logical 0, or a FALSE condition
 1: logical 1, or a TRUE condition

 x: an unknown value

 z: a high impedance condition

Verilog 19
 Hierarchical De-Referencing
․To reference a variable defined inside an instantiated module
․Supported by a variable’s hierarchical path name
 X.w
 X.Y.Z.w

Module A - Instance X
wire w
Module B - Instance Y
Module C - Instance Z
Wire w

Verilog 20
 if…else
․else is paired with nearest if when ambiguous (use
begin…end in nesting to clarify)

(a) if (a < b) c = d + 1; (d) if (a < b)

(b) if (a < b); sum = sum + 1;
(c) if (k == 1) else
begin : A_block sum = sum + 2;
sum_out = sum_reg;
c_out = c_reg;
end

Verilog 21
 Example
module mux4_PCA (a, b, c, d, select, y_out);
input a, b, c, d;
input [1:0] select;
output y_out;
reg y_out;

always @ (select or a or b or c or d)
if (select == 0) y_out = a; else
if (select == 1) y_out = b; else
if (select == 2) y_out = c; else
if (select == 3) y_out = d; else
y_out = 1’bx;
endmodule
Verilog 22
 case

․Require complete bitwise match

․Example:
…
always @ (a or b or c or d or
select)
begin
case (select)
0: y = a;
1: y = b;
2: y = c;
3: y = d;
default: y = 1’bx;
endcase
end
Verilog … 23
 Netlist of Primitives

module or_nand_1 (enable, x1,

x2, x3, x4, y); x1 x2 x3 x4
w1
input enable, x1, x2, x3, x4;
output y; w2
wire w1, w2, w3; y
w3

or (w1, x1, x2); enable

or (w2, x3, x4); (a) Pre-optimized circuit
or (w3, x3, x4); // redundant
nand (y, w1, w2, w3, enable);
oai22_a
x1
endmodule x2
x3 nand2i_a
x4 y
enable
(b) Circuit synthesized from the circuit in (a)

Verilog 24
 Continuous Assignment
module or_nand_2 (enable, x1, x2, x3, x4, y);
input enable, x1, x2, x3, x4;
output y;

assign y = ~(enable & (x1 | x2) & (x3 | x4));

endmodule

x1 w1
oai22_a
x2 x1
x2
enable x3 nand2i_a
x4 y
x3 w3 enable
x4

Synthesis result
Verilog 25
 Behavioral Description
module or_nand_3 (enable, x1, x2, x3, x4, y);
input enable, x1, x2, x3, x4;
output y;
reg y;

always @ (enable or x1 or x2 or x3 or x4)

begin
y = ~(enable & (x1 | x2) & (x3 | x4));
end
endmodule

oai22_a
x1
x2
x3 nand2i_a
x4 y
enable

Circuit synthesized from a behavioral description

Verilog 26
 Avoid Latch Inference (1/2)
․When if or case statements are used without
specifying outputs in all possible conditions, a latch
will be created
always@(enable or data) data q

if(enable) DL0A
q = data; enable

always@(enable or data)
Latch inferred
begin
if(enable)
enable AN2A
q = data; data
q

else
q = 0;
Specify all output values
end

Verilog 27
 Avoid Latch Inference (2/2)

always@(a or b or c)
always@(a or b or c) case(a) Add a default
case(a) No latch statement
2’b11 : e = b;
2’b11 : e = b; 2’b10 : e = ~c;
2’b10 : e = ~c; default : e = 0;
endcase endcase

result in a latch

Verilog 28
 Code Converter (1/3)

․A code converter transforms Truth Table for Code Converter Example

one representation of data to Input Output
another BCD Excess-3
A B C D W X Y Z
․Ex: A BCD to excess-3 code 0 0 0 0 0 0 1 1
converter 0 0 0 1 0 1 0 0
 BCD: Binary Coded 0 0 1 0 0 1 0 1
Decimal 0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
 Excess-3 code: the
0 1 0 1 1 0 0 0
decimal digit plus 3 0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0

Verilog 29
 Code Converter (2/3)
․Equations: (share terms to minimize cost)
W = A + BC + BD = A + B(C + D)
X = BC + BD + BCD = B(C + D) + BCD
Y = CD + CD = C + D
Z=D D’ Z
CD C D CD
AB 00 01 11 10 C Y

00 (C + D)’
C+D
01 1 1 1 B B
11     X
A
10 1 1  
D
W
W = A + BC + BD A
Verilog 30
 Code Converter (3/3)

․ RTL style ․ Behavior style

assign W = A|(B&(C|D)); assign ROM_in = {A, B, C, D};
assign {W, X, Y, Z} = ROM_out;
assign X = ~B&(C|D)|(B&~C&~D);
always @(ROM_in) begin
assign Y = ~(C^D);
case (ROM_in)
assign Z = ~D; 4‘b0000: ROM_out = 4‘b0011;
4‘b0001: ROM_out = 4‘b0100;
…
4‘b1001: ROM_out = 4‘b1100;
default: ROM_out = 4‘b0000;
endcase
end

Verilog 31
 Decoder (1/2)
․A decoder is to generate D0 = x’y’z’
the 2n (or fewer)
minterms of n input z
D1 = x’y’z

variables
D2 = x’yz’
․Ex: a 3-to-8 line decoder
y
D3 = x’yz
Inputs Outputs
x y z D0 D1 D2 D3 D4 D5 D6 D7 D4 = xy’z’
0 0 0 1 0 0 0 0 0 0 0
x
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0 D5 = xy’z
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
D6 = xyz’
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1 D7 = xyz

Verilog 32
 Decoder (2/2)
․ Behavior style 1 ․ Behavior style 2
input x, y, z; input x, y, z;
output [7:0] D; output [7:0] D;
reg [7:0] D; wire [2:0] addr;
always @(x or y or z) begin reg [7:0] D;
case ({x, y, z}) assign addr = {x, y, z};
3‘b000: D = 8‘b00000001; always @(addr) begin
3‘b001: D = 8‘b00000010; D = 8‘b0;
… D[addr] = 1;
3‘b111: D = 8‘b10000000; end
default: D = 8‘b0;
endcase
end

Verilog 33
 Multiplexer (1/2)

․A multiplexer uses n I0

selection bits to choose

binary info. from a I1

maximum of 2n unique Y
input lines I2

S1 S 0 Y
I3
0 0 I0
0 1 I1
1 0 I2
1 1 I3
(b) Function table
S1
S0 decoder !!
(a) Logic diagram

Verilog 34
 Multiplexer (2/2)
․Behavior style 1 ․Behavior style 2
input [1:0] S; input [1:0] S;
input [3:0] I; input [3:0] I;
output Y; output Y;
reg Y; reg Y;
always @(S or I) begin always @(S or I)
case (S) begin
2‘b00: Y = I[0]; Y = I[S];
2‘b01: Y = I[1]; end
2‘b10: Y = I[2];
2‘b11: Y = I[3];
default: Y = 0;
endcase
end

Verilog 35
 BCD Adder (1/2)
Addend Augend
C detects whether the binary sum
is greater than 9 (1001)
Carry Carry
K 4-bit binary adder
out in
Z8 Z4 Z2 Z1
C = K + Z8Z4 + Z8Z2

Output
carry

If C=1, it is necessary to add 6

(0110) to binary sum 4-bit binary adder

S8 S4 S2 S1
Verilog 36
 BCD Adder (2/2)
module bcd_add (S, Cout, A, B, Cin);
input [3:0] A, B;
input Cin;
output [3:0] S;
output Cout;
reg [3:0] S;
reg Cout;

always @(A or B or Cin) begin

{Cout, S} = A + B + Cin;
if (Cout != 0 || S > 9) begin
S = S + 6;
Cout = 1;
end
end
endmodule
Verilog 37
 Latch Inference
․Incompletely specified wire in the synchronous section
․D latch
always @(enable or data)
if (enable)
q = data;

Verilog 38
 More Latches
․D latch with gated enable
always @(enable or d or gate)
if (enable & gate)
q = d; d
q
enable
gate

․D latch with asynchronous reset

always @(reset or data or enable)
if (reset)
q = 1’b0;
else if (enable)
q = data;
Verilog 39
 Flip-Flop Inference
․Wire (port) assigned in the synchronous section
module FF_PN (Clock, X1, X2, Y1, Y2);
input Clock;
input X1, X2; X1 Y1

output Y1, Y2;

reg Y1, Y2; Clock
always @(posedge Clock)
Y1 = X1;
always @(negedge Clock) X2 Y2

Y2 = X2;
endmodule Clock

Verilog 40
 Modeling Reset

Synchronous reset Asynchronous reset

always@(posedge clk) always@(posedge clk or negedge reset)

if(!reset) q=1’b0; if(!reset) q=1’b0;
else q=data; else q=data;

reset AN2S clk

q
data data DFQ3A
DF0S INA q
reset
clk
INA
set

Verilog 41
 The Simplest Shift Register

Serial SI D D D D SO Serial
input output

C C C C

CLK

4-Bit Shift Register

SRG4
Clock

SI SO

Symbol
Verilog 42
 Procedural Assignment

․Assign value to registers

․Blocking procedural assignment
 Use “=”
 An assignment is completed before the next
assignment starts

․Non-blocking procedural assignment

 Use “<=”
 Assignments are executed in parallel

Verilog 43
 Examples
a = 1; a = 1;
b = 0; b = 0;
… …
a <= b; // use b=0 b <= a; // use a=1
b <= a; // use a=1 a <= b; // use b=0

a = 1; a = 1;
b = 0; b = 0;
… …
a = b; // use b=0 b = a; // use a=1
b = a; // use a=0 a = b; // use b=1

Verilog 44
 HDL Modeling for Shift Reg.
․ Blocking assignment ․ Non-blocking assignment
assign SO = D; assign SO = D;
always @(posedge CLK) begin always @(posedge CLK)begin
if (reset) begin if (reset) begin
A=0; B=0; C=0; D=0; A<=0; B<=0; C<=0; D<=0;
end end
else if (shift) begin else if (shift) begin
D = C; A <= SI;
C = B; C <= B;
B = A; D <= C;
A = SI; B <= A;
end end
end end can be any order
order dependent

Verilog 45
 Non-Blocking Assignment
always@(posedge clk) always@(posedge clk)
begin outa=in;
outa<=in; always@(posedge clk)
outb<=outa; outb=outa;
outc<=outb; always@(posedge clk)
end outc=outb;

in outc
D Q D Q D Q

clk

Verilog 46
 References
․T.-C. Wang, course slides of “HDL and Synthesis”,
Dept. of CS, NTHU.
․C.-N. Liu, course slides of “Digital System Design”,
Dept. of EE. NCU.

Verilog 47