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SYLLABUS
EE2356 - MICROPROCESSOR AND MICRO CONTROLLER LABORATORY

m
AIM
1. To understand programming using instruction sets of processors.
2. To study various digital & linear

co
8-bit Microprocessor
1. Simple arithmetic operations:
Multi precision addition / subtraction / multiplication / division.

s.
2. Programming with control instructions:
Increment / Decrement, Ascending / Descending order, Maximum / Minimum of numbers,
Rotate instructions - Hex / ASCII / BCD code conversions.
3. Interface Experiments:

te
• A/D Interfacing.
• D/A Interfacing.
• Traffic light controller.
4. Interface Experiments: Simple experiments using 8251, 8279, 8254.

8-bit Microcontroller
no
5. Demonstration of basic instructions with 8051 Micro controller execution, including:
• Conditional jumps, looping
ar
• Calling subroutines.
• Stack parameter testing
6. Parallel port programming with 8051 using port 1 facility:
- Stepper motor and D / A converter.
t

7. Study of Basic Digital IC’s

(Verification of truth table for AND, OR, EXOR, NOT, NOR, NAND, JK FF, RS FF,D FF)
5s

8. Implementation of Boolean Functions, Adder / Subtractor circuits.

9. Combination Logic; Adder, Subtractor, Code converters, Encoder and Decoder
10. Sequential Logic; Study of Flip-Flop,Counters(synchronous and asynchronous),Shift
Registers
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LIST OF EXPERIMENTS

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Ex. No Page No.

8 – BIT MICROPROCESSOR (8085)

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1(a) 8- bit Addition
1(b) 8 – bit Subtraction
1
1(c) 8- bit Multiplication

s.
1(d) 8- bit Division
2(a) Ascending order
2(b) Descending order
2 2( c) Largest of a given numbers

te
2(d) Smallest of a given numbers
3(a) Code Conversion: ASCII to Hexadecimal
3(b) Code Conversion: Hexadecimal to ASCII
3
3(c) Code Conversion: Hexadecimal to Binary
no
3(d) Code Conversion: Hexadecimal to BCD
4(a) Interfacing: ADC with 8085
4
4(b)Interfacing: DAC with 8085
ar
5 Interfacing: Traffic Light Controller with 8085
6(a)Interfacing: 8251 with 8085
6 6(b) Interfacing: 8279 with 8085
6(c) Interfacing: 8253 with 8085
t

MICROCONTROLLER(8051)
7(a) Sum of elements in an array
5s

7 7(b) Sum using Stack

7( c) Sum using call option
8(a) Interfacing: Stepper Motor with 8051
8
8(b) Interfacing: DAC with 8051
w.

STUDY OF BASIC DIGITAL IC’S

9 Verification of truth table for AND, OR, EXOR,
NOT, NOR, NAND, JK FF, RS FF,D FF
ww

10 Implementation of Boolean Functions, Adder /

Subtractor circuits
11 Code converters, Encoder and Decoder
12 Study of Flipflops
13 Counters(synchronous and asynchronous), Shift
registers
14 Differentiator, Integrator
15 Timer IC applications

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8085 MICROPROCESSOR
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Ex.No: 1 SIMPLE ARITHMETIC OPERATIONS

m
AIM:

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To write an assembly language program to add, subtract, multiply and divide the given
data stored at two consecutive locations using 8085 microprocessor.

s.
A. 8 BIT DATA ADDITION:

ALGORITHM:

te
1. Initialize memory pointer to data location.
2. Get the first number from memory in accumulator.
3. Get the second number and add it to the accumulator.
4. Store the answer at another memory location.
no
t ar
5s
w.
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FLOW CHART:
START

m
co
[C] 00H

s.
[HL] 4500H

[A] [M]

te
[HL] [HL]+1

[A]
no
[A]+[M]
ar
Is there a NO
Carry ?

YES
t

[C] [C]+1
5s

[HL] [HL]+1
w.

[M] [A]
ww

[HL] [HL]+1

[M] [C]

STOP

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PROGRAM:

m
ADDRESS OPCODE LABEL MNEMONICS OPERAND COMMENT

co
4100 START MVI C, 00 Clear C reg.
4101
4102 LXI H, 4500 Initialize HL reg. to
4103 4500

s.
4104
4105 MOV A, M Transfer first data to
accumulator
4106 INX H Increment HL reg. to

te
point next memory
Location.
4107 ADD M Add first number to
acc. Content.
4108 no JNC L1 Jump to location if
4109 result does not yield
410A carry.
410B INR C Increment C reg.
410C L1 INX H Increment HL reg. to
ar
point next memory
Location.
410D MOV M, A Transfer the result from
acc. to memory.
t

410E INX H Increment HL reg. to

point next memory
5s

Location.
410F MOV M, C Move carry to memory
4110 HLT Stop the program
w.
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B. 8 BIT DATA SUBTRACTION

m
co
ALGORITHM:

1. Initialize memory pointer to data location.

2. Get the first number from memory in accumulator.

s.
3. Get the second number and subtract from the accumulator.
4. If the result yields a borrow, the content of the acc. is complemented and 01H is added
to it (2’s complement). A register is cleared and the content of that reg. is incremented
in case there is a borrow. If there is no borrow the content of the acc. is directly taken as
the result.

te
5. Store the answer at next memory location.

no
t ar
5s
w.
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FLOW CHART: START

m
[C] 00H

co
[HL] 4500H

s.
[A] [M]

te
[HL] [HL]+1

[A] [A]-[M]
no
NO
Is there a
ar
Borrow ?

YES

Complement [A]
t

Add 01H to [A]

5s

[C] [C]+1

[HL] [HL]+1
w.

[M] [A]
ww

[HL] [HL]+1

[M] [C]

STOP
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PROGRAM:

m
ADDRESS OPCODE LABEL MNEMONICS OPERAND COMMENT

co
4100 START MVI C, 00 Clear C reg.
4101
4102 LXI H, 4500 Initialize HL reg. to
4103 4500

s.
4104
4105 MOV A, M Transfer first data to
accumulator
4106 INX H Increment HL reg. to

te
point next mem.
Location.
4107 SUB M Subtract first number
from acc. Content.
4108 no JNC L1 Jump to location if
4109 result does not yield
410A borrow.
410B INR C Increment C reg.
410C CMA Complement the Acc.
ar
content
410D ADI 01H Add 01H to content of
410E acc.
410F L1 INX H Increment HL reg. to
t

point next mem.

Location.
5s

4110 MOV M, A Transfer the result from

acc. to memory.
4111 INX H Increment HL reg. to
point next mem.
Location.
w.

4112 MOV M, C Move carry to mem.

4113 HLT Stop the program
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C. 8 BIT DATA MULTIPLICATION:

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ALGORITHM:

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LOGIC: Multiplication can be done by repeated addition.

1. Initialize memory pointer to data location.

s.
2. Move multiplicand to a register.
3. Move the multiplier to another register.
4. Clear the accumulator.
5. Add multiplicand to accumulator
6. Decrement multiplier

te
7. Repeat step 5 till multiplier comes to zero.
8. The result, which is in the accumulator, is stored in a memory location.

no
t ar
5s
w.
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FLOW CHART:

m
START

co
[HL] 4500

B M

s.
[HL]  [HL]+1

te
A  00
no
C  00
ar
[A]  [A] +[M]
t

Is there NO
any carry
5s

YES
C  C+1
w.

B  B-1
ww

NO
IS B=0

YES

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m
[HL] [HL]+1

co
[M] [A]

s.
[HL] [HL]+1

te
[M] [C]

STOP
no
t ar
5s
w.
ww

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PROGRAM:

m
ADDRESS OPCODE LABEL MNEMONICS OPERAND COMMENT

co
4100 START LXI H, 4500 Initialize HL reg. to
4101 4500
4102
4103 MOV B, M Transfer first data to

s.
reg. B
4104 INX H Increment HL reg. to
point next mem.
Location.
4105 MVI A, 00H Clear the acc.

te
4106
4107 MVI C, 00H Clear C reg for carry
4108

4109 L1
no ADD M Add multiplicand
multiplier times.
410A JNC NEXT Jump to NEXT if there
410B is no carry
ar
410C
410D INR C Increment C reg
410E NEXT DCR B Decrement B reg
t

410F JNZ L1 Jump to L1 if B is not

4110 zero.
4111
5s

4112 INX H Increment HL reg. to

point next mem.
Location.
4113 MOV M, A Transfer the result from
w.

acc. to memory.
4114 INX H Increment HL reg. to
point next mem.
Location.
ww

4115 MOV M, C Transfer the result from

C reg. to memory.
4116 HLT Stop the program

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D. 8 BIT DIVISION:

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ALGORITHM:

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LOGIC: Division is done using the method Repeated subtraction.
1. Load Divisor and Dividend
2. Subtract divisor from dividend
3. Count the number of times of subtraction which equals the quotient

s.
4. Stop subtraction when the dividend is less than the divisor .The dividend now becomes
the remainder. Otherwise go to step 2.
5. stop the program execution.

te
no
t ar
5s
w.
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START
FLOWCHART:

m
B  00

co
[HL] 4500

s.
A M

te
[HL]  [HL]+1

M  A-M
no
[B]  [B] +1
ar
NO
IS A<0
YES
A  A+ M
t
5s

B  B-1

[HL] [HL]+1
w.

[M] [A]
ww

[HL] [HL]+1

[M] [B]

STOP

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PROGRAM:

ADDRESS OPCODE LABEL MNEMONICS OPERAND COMMENTS

m
4100 MVI B,00 Clear B reg for quotient
4101

co
4102 LXI H,4500 Initialize HL reg. to
4103 4500H
4104
4105 MOV A,M Transfer dividend to

s.
acc.
4106 INX H Increment HL reg. to
point next mem.
Location.

te
4107 LOOP SUB M Subtract divisor from
dividend
4108 INR B Increment B reg
4109 JNC LOOP Jump to LOOP if
410A
410B
410C
no
ADD M
result does not yield
borrow
Add divisor to acc.
410D DCR B Decrement B reg
410E INX H Increment HL reg. to
ar
point next mem.
Location.
410F MOV M,A Transfer the remainder
from acc. to memory.
t

4110 INX H Increment HL reg. to

point next mem.
5s

Location.
4111 MOV M,B Transfer the quotient
from B reg. to memory.
4112 HLT Stop the program
w.
ww

OBSERVATION:

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ADDITION:

m
S.NO INPUT OUTPUT

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ADDRESS DATA ADDRESS DATA
1 4500 4502
4501 4503
2 4500 4502

s.
4501 4503

SUBTRACTION:

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S.NO INPUT OUTPUT
ADDRESS DATA ADDRESS DATA
1 4500 4502
4501 no 4503
2 4500 4502
4501 4503

MULTIPLICATION:
ar

S.NO INPUT OUTPUT

ADDRESS DATA ADDRESS DATA
t

1 4500 4502
4501 4503
5s

2 4500 4502
4501 4503

DIVISION:
w.

S.NO INPUT OUTPUT

ADDRESS DATA ADDRESS DATA
1 4500 4502
ww

4501 4503
2 4500 4502
4501 4503

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RESULT:

Thus the addition, subtraction, multiplication and division of two numbers was
performed using the 8085 microprocessor.

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Ex.No: 2 SORTING OF AN ARRAY

m
AIM:

co
To write an assembly language program to arrange an array of data in ascending and
descending order and to find the smallest and largest data among the array.

s.
A. ASCENDING ORDER
ALGORITHM:

te
1. Get the numbers to be sorted from the memory locations.
2. Compare the first two numbers and if the first number is larger than second then I
interchange the number.
3. If the first number is smaller, go to step 4
4. Repeat steps 2 and 3 until the numbers are in required order
no
t ar
5s
w.
ww

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FLOWCHART:
START

m
[B]  04H

co
[HL]  [8100H]

s.
[C]  04H

[A]  [HL]

te
[HL  [HL] + 1

YES
no IS
[A] < [HL]?

NO
ar

[D] [HL]
t

[HL]  [A]
5s

[HL]  [HL] - 1
w.

[HL]  [D]

[HL]  [HL] + 1
ww

[C]  [C] – 01 H

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m
co
A

s.
IS NO
[C] = 0?

YES

te
[B]  [B]-1

IS
no
[B] = 0?
NO

YES
ar

STOP
t
5s
w.
ww

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PROGRAM:

ADDRESS OPC LABEL MNEMONICS OPERA COMMENTS

m
ODE ND
4100 MVI B,04 Initialize B reg with

co
4101 number of comparisons
(n-1)
4102 LOOP 3 LXI H,4200 Initialize HL reg. to
4103 4200H

s.
4104
4105 MVI C,04 Initialize C reg with no.
4106 of comparisons(n-1)
4107 LOOP2 MOV A,M Transfer first data to

te
acc.
4108 INX H Increment HL reg. to
point next memory
location
4109 CMP
no M Compare M & A
410A JC LOOP1 If A is less than M then
410B go to loop1
410C
410D MOV D,M Transfer data from M to
ar
D reg
410E MOV M,A Transfer data from acc
to M
410F DCX H Decrement HL pair
t

4110 MOV M,D Transfer data from D to

M
5s

4111 INX H Increment HL pair

4112 LOOP1 DCR C Decrement C reg
4113 JNZ LOOP2 If C is not zero go to
4114 loop2
4115
w.

4116 DCR B Decrement B reg

4117 JNZ LOOP3 If B is not Zero go to
4118 loop3
4119
ww

411A HLT Stop the program

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B. DESCENDING ORDER

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ALGORITHM:

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1. Get the numbers to be sorted from the memory locations.
2. Compare the first two numbers and if the first number is smaller than second then I
interchange the number.

s.
3. If the first number is larger, go to step 4
4. Repeat steps 2 and 3 until the numbers are in required order

te
no
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5s
w.
ww

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FLOWCHART:
START

m
co
[B]  04H

[HL]  [8100H]

s.
[C]  04H

[A]  [HL]

te
[HL  [HL] + 1
no
NO IS
[A] < [HL]?
ar
YES

[D] [HL]
t

[HL]  [A]
5s

[HL]  [HL] - 1
w.

[HL]  [D]

[HL]  [HL] + 1
ww

[C]  [C] – 01 H

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m
co
A

s.
IS NO
[C] = 0?

YES

te
[B]  [B]-1

IS
no NO
[B] = 0?

YES
ar

STOP
t
5s
w.
ww

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PROGRAM:

m
ADDRE OPCO LABEL MNEM OPER COMMENTS
SS DE ONICS AND

co
4100 MVI B,04 Initialize B reg with number
4101 of comparisons (n-1)
4102 LOOP 3 LXI H,4200 Initialize HL reg. to
4103 4200H

s.
4104
4105 MVI C,04 Initialize C reg with no. of
4106 comparisons(n-1)
4107 LOOP2 MOV A,M Transfer first data to acc.

te
4108 INX H Increment HL reg. to point
next memory location
4109 CMP M Compare M & A
410A JNC LOOP1 If A is greater than M then go
410B no to loop1
410C
410D MOV D,M Transfer data from M to D reg
410E MOV M,A Transfer data from acc to M
410F DCX H Decrement HL pair
ar
4110 MOV M,D Transfer data from D to M
4111 INX H Increment HL pair
4112 LOOP1 DCR C Decrement C reg
4113 JNZ LOOP2 If C is not zero go to loop2
t

4114
4115
5s

4116 DCR B Decrement B reg

4117 JNZ LOOP3 If B is not Zero go to loop3
4118
4119
411A HLT Stop the program
w.
ww

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C. LARGEST ELEMENT IN AN ARRAY

m
co
ALGORITHM:
1. Place all the elements of an array in the consecutive memory locations.
2. Fetch the first element from the memory location and load it in the accumulator.

s.
3. Initialize a counter (register) with the total number of elements in an array.
4. Decrement the counter by 1.
5. Increment the memory pointer to point to the next element.

te
6. Compare the accumulator content with the memory content (next
element).
7. If the accumulator content is smaller, then move the memory content
no
(largest element) to the accumulator. Else continue.
8. Decrement the counter by 1.
9. Repeat steps 5 to 8 until the counter reaches zero
ar
10. Store the result (accumulator content) in the specified memory location.
t
5s
w.
ww

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FLOW CHART:
START

m
co
[HL]  [8100H]

[B]  04H

s.
[A]  [HL]

[HL  [HL] + 1

te
NO no IS
[A] < [HL]?

YES

[A] [HL]
ar

[B]  [B]-1
t
5s

IS NO
[B] = 0?

YES
w.

[8105]  [A]

STOP
ww

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PROGRAM:

ADDRE OPCO LABEL MNEM OPER COMMENTS

m
SS DE ONICS AND
4101 LXI H,4200 Initialize HL reg. to

co
4102 4200H
4103
4104 MVI B,04 Initialize B reg with no. of
4105 comparisons(n-1)

s.
4106 MOV A,M Transfer first data to acc.
4107 LOOP1 INX H Increment HL reg. to point
next memory location
4108 CMP M Compare M & A

te
4109 JNC LOOP If A is greater than M then go
410A to loop
410B
410C MOV A,M Transfer data from M to A reg
410D LOOP DCR
no B Decrement B reg
410E JNZ LOOP1 If B is not Zero go to loop1
410F
4110
4111 STA 4205 Store the result in a memory
ar
4112 location.
4113
4114 HLT Stop the program
t
5s
w.
ww

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D.SMALLEST ELEMENT IN AN ARRAY

m
ALGORITHM:
1. Place all the elements of an array in the consecutive memory locations.

co
2. Fetch the first element from the memory location and load it in the accumulator.
3. Initialize a counter (register) with the total number of elements in an array.
4. Decrement the counter by 1.

s.
5. Increment the memory pointer to point to the next element.
6. Compare the accumulator content with the memory content (next

te
element).
7. If the accumulator content is smaller, then move the memory content
(largest element) to the accumulator. Else continue.
8. Decrement the counter by 1. no
9. Repeat steps 5 to 8 until the counter reaches zero
10. Store the result (accumulator content) in the specified memory location.
t ar
5s
w.
ww

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FLOW CHART:
START

m
co
[HL]  [8100H]

[B]  04H

s.
[A]  [HL]

[HL  [HL] + 1

te
YES no IS
[A] < [HL]?

NO

[A] [HL]
ar

[B]  [B]-1
t
5s

IS NO
[B] = 0?

YES
w.

[8105]  [A]

STOP
ww

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m
PROGRAM:

ADDRE OPCO LABEL MNEM OPER COMMENTS

co
SS DE ONICS AND
4101 LXI H,4200 Initialize HL reg. to
4102 4200H
4103

s.
4104 MVI B,04 Initialize B reg with no. of
4105 comparisons(n-1)
4106 MOV A,M Transfer first data to acc.
4107 LOOP1 INX H Increment HL reg. to point

te
next memory location
4108 CMP M Compare M & A
4109 JC LOOP If A is lesser than M then go
410A to loop
410B
410C
410D LOOP
MOV
DCR
no A,M
B
Transfer data from M to A reg
Decrement B reg
410E JNZ LOOP1 If B is not Zero go to loop1
410F
ar
4110
4111 STA 4205 Store the result in a memory
4112 location.
4113
t

4114 HLT Stop the program

5s
w.
ww

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OBSERVATION:

A. ASCENDING ORDER

m
INPUT OUTPUT

co
MEMORY DATA MEMORY DATA
LOCATION LOCATION
4200 4200
4201 4201

s.
4202 4202
4203 4203
4204 4204

te
B. DESCENDING ORDER

INPUT OUTPUT
MEMORY DATA MEMORY DATA
LOCATION no LOCATION
4200 4200
4201 4201
4202 4202
4203 4203
ar
4204 4204

C. SMALLEST ELEMENT
t

INPUT OUTPUT
MEMORY DATA MEMORY DATA
LOCATION LOCATION
5s

4200
4201
4202 4205
4203
w.

4204

D. LARGEST ELEMENT
ww

INPUT OUTPUT
MEMORY DATA MEMORY DATA
LOCATION LOCATION
4200
4201
4202 4205
4203
4204

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m
co
s.
te
no
t ar
5s
w.
ww

RESULT:

Thus the sorting operations of arranging an array in ascending, descending order and
the largest and smallest element were found using the 8085 microprocessor.

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Ex.No: 3 CODE CONVERSIONS

m
AIM:

co
To write an assembly language program to perform the conversions of ASCII to
hexadecimal number, hexadecimal to ASCII, hexadecimal to decimal number, binary to
hexadecimal number and hexadecimal to binary number.

s.
A.ASCII TO HEXADECIMAL
ALGORITHM:

te
1. Start the program
2. Load the data from address 4200 to A
3. Move data from accumulator to C
4. Move data from M to HL pair to accumulator
5. Subtract the data 30 from A no
6. Decrement content of register
7. Stop the program if C is zero
8. Jump to Step 5
9. End the program
t ar
5s
w.
ww

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FLOWCHART:

m
Start

co
Set the ASCII value

s.
Subtract 30 from A

te
Decrement the register content

no
Check YES
for
ar
Carry?

NO
t

Subtract 07 from A
5s

Store the hex value

w.

Stop
ww

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PROGRAM:

ADDRE OPCO LABEL MNEM OPER COMMENTS

m
SS DE ONICS AND
4100 LDA H,4200 Load data 4200 to A

co
4101
4102
4103 MOV C,A 4F Move data from A to C
4104 LXI H,4201 Load address 4201 in HL

s.
4105
4106
4107 LXI D,4301 Load address 4301 in DF
4108

te
4109
410A LOOP 1 MOV A,M Move data from M to A
410B SUI 30 Subtract 30 from A
410C
410D

410E
no
STAX D

DCR C
Store data from
accumulator to DE
Decrement from C
register
410F JZ LOOP Stop program if C is 0
ar
4110
4111
4112 INX H Increment HL register
pair
t

4113 INX D Increment DE register

pair
5s

4114 JMP LOOP 1 Jump to 410A

4115
4116
4117 LOOP HLT Stop
w.
ww

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B. HEXADECIMAL TO ASCII

m
co
ALGORITHM:

1. Start the program

2. Load the data from address 4200 to A
3. Move data from accumulator to C

s.
4. Move data from M to HL pair to accumulator
5. Add the data 30 to A
6. Decrement content of register
7. Stop the program if C is zero

te
8. Jump to Step 5
9. End the program

no
t ar
5s
w.
ww

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FLOWCHART:

m
Start

co
Set the ASCII value

s.
Add 30 to A

te
Decrement the register content
no
Check YES
ar
for
Carry?
t

NO
5s

Store the decimal value

Stop
w.
ww

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PROGRAM:

ADDRE OPCO LABEL MNEM OPER COMMENTS

m
SS DE ONICS AND
4100 LDA H,4200 Load data 4200 to A

co
4101
4102
4103 MOV C,A 4F Move data from A to C
4104 LXI H,4201 Load address 4201 in HL

s.
4105
4106
4107 LXI D,4301 Load address 4301 in DF
4108

te
4109
410A LOOP 1 MOV A,M Move data from M to A
410B ADI 30 Subtract 30 from A
410C
410D

410E
no
STAX D

DCR C
Store data from
accumulator to DE
Decrement from C
register
410F JZ LOOP Stop program if C is 0
ar
4110
4111
4112 INX H Increment HL register
pair
t

4113 INX D Increment DE register

pair
5s

4114 JMP LOOP 1 Jump to 410A

4115
4116
4117 LOOP HLT Stop
w.
ww

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C. HEXADECIMAL TO BINARY

m
co
ALGORITHM:

1. Start the program

2. Move the content of memory to accumulator

s.
3. Move data 0B o register B
4. Increment the content of HL register pair
5. Rotate the accumulator right
6. Jump to the specified address if carry generated
7. Move 00 to memory

te
8. Jump to specified address if there is no zero
9. Move 01 to memory
10. Jump to specified address if there is no zero
11. End the program no
t ar
5s
w.
ww

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FLOWCHART:

Start

m
co
Load address in HL pair

Move data from M to A

s.
Initialize counter B to 08

te
Increment HL register pair

Rotate accumulator right

no
ar

Check for YES

Carry?
NO
t

Move data from 00 to M

5s

Move data from 01 to M

w.

Decrement B register
ww

NO
If B=0?

YES

Stop

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PROGRAM:

ADDRE OPCO LABEL MNEM OPERAND COMMENTS

m
SS DE ONICS
4100 LXI H,4200 Load address in HL pair

co
4101
4102
4103 MOV A,M Move content of M to A
4104 MVI B 08 Move 0B to register pair

s.
4105
4106 L3 INX H Increment the content of
HL pair
4107 RRC Rotate accumulator right

te
4108 JC L1 Jump to specified address
if carry
4109
410A
410B MVI M
no 00 Move 00 to M
410C JMP L2 Decrement B register
410D
410E
410F L1 MVI M 01 Move 01 to M
ar
4110
4111 L2 DCR B Decrement B by 1
4112 JNZ L3 Jump to the specified
address if no zero
t

4113
4114
5s

4115 HLT Stop the program

w.
ww

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D. BINARY TO HEXADECIMAL

m
ALGORITHM:

1. Start the program

co
2. Load the address in HL pair
3. Move the content of memory to accumulator
4. Add the content of accumulator with previous content of accumulator
5. Move the content of B to accumulator

s.
6. Add the content of accumulator with previous content of accumulator
7. Repeat step 6
8. Add B with accumulator content
9. Increment H by 1
10. Move content of M to A

te
11. End the program

no
t ar
5s
w.
ww

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FLOWCHART:

Start

m
co
Load address in HL pair

Move data from M to A

s.
Add content of A to register B

te
Add content of A with itself
no
Add content of A to register B
ar
Increment HL reg pair

Add content of M with accumulator

t
5s

Increment HL reg pair content

Move content of M to accumulator

w.

Stop
ww

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PROGRAM:

ADDRE OPCO LABEL MNEM OPERAND COMMENTS

m
SS DE ONICS
4100 LXI H,4150 Load address in HL pair

co
4101
4102
4103 MOV M,A Move content of A to M
4104 ADD A Add A content with

s.
previous content of A
4105 MOV B,A Move the content from
A to B
4106 ADD A Add A content with

te
previous content of A
4107 ADD B Add B content with A
4108 INX H Increment H by 1
4109 ADD M Add M content with A
410A INX H
no Increment H by 1
410B MOV M,A Move content of A to M
410C HLT Stop the program
t ar
5s
w.
ww

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E. HEXADECIMAL TO DECIMAL

m
ALGORITHM:

1. Start the program

co
2. Load the address in HL pair
3. Move the content from HL to A
4. Subtract 64 from A
5. Increment BC pair

s.
6. Jump to address 4207
7. Subtract 0A from A
8. Increment HL pair
9. Rotate accumulator left
10. Increment HL pair

te
11. End the program

no
t ar
5s
w.
ww

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FLOWCHART:

Start

m
co
Load address in HL pair

Initialize D register

s.
Clear accumulator

Move HL to C register

te
Add 01 with A

Adjust A to BCD

Check
no YES
Carry?
NO
ar

Increment D register

Increment C register
t
5s

NO
Check
Carry?
YES
w.

Store A in 4151 H

Move D to accumulator
ww

Store A in 4150 H

Stop

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PROGRAM:

ADDRE OPCO LABEL MNEM OPER COMMENTS

m
SS DE ONICS AND
4100 LXI H 4150 Load data from 4150 to HL pair

co
4101
4102 LXI B 0000 Load data from address to BC
4103
4104

s.
4105
4106 MOV A,M Move the content from HL to A
4107 L4 SUI 64 Subtract 64 from A
4108

te
4109 JC L1 Stop if A has carry
410A
410B
410C INR B Increment BC
410D
410E
410F
no
JMP L4 Jump to specified address

4110 L1 ADI 64 Add 64 to A

4111
ar
4112 L3 SUI 0A Subtract 0A from A
4113
4114 JC L2 Stop if A has carry
4115
t

4116
4117 INR C Increment HL
5s

4118 L2 JNC L3 Stop if A has no carry

4119
411A
411B ADI 0A Add 0A to A
w.

411D INX H Increment HL

411E MOV M,B Move B to M
411F MOV B,A Move A to B
4120 MOV A,B Move B to A
4121 RLC Rotate accumulator
ww

4122 RLC Rotate accumulator

4123 RLC Rotate accumulator
4124 RLC Rotate accumulator
4125 ADD B Add B to A
4126 INX H Increment H by 1
4127 MOV M,A Move content of A to M
4128 HLT Stop the program

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OBSERVATION:

A. ASCII TO HEXADECIMAL

m
INPUT OUTPUT

co
MEMORY DATA MEMORY DATA
LOCATION LOCATION
4201 4301

s.
B. HEXADECIMAL TO ASCII

INPUT OUTPUT
MEMORY DATA MEMORY DATA

te
LOCATION LOCATION
4201 4301

C. HEXADECIMAL TO BINARY

INPUT
no OUTPUT
MEMORY DATA MEMORY DATA MEMORY DATA
LOCATION LOCATION LOCATION
ar
4200 4204
4200 4201 4205
4202 4206
4203 4207
t

D. BINARY TO HEXADECIMAL
5s

INPUT OUTPUT
MEMORY DATA MEMORY DATA
LOCATION LOCATION
4150
w.

4151 4152

E. HEXADECIMAL TO DECIMAL
ww

INPUT OUTPUT
MEMORY DATA MEMORY DATA
LOCATION LOCATION
4150
4151 4152

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m
co
s.
te
no
t ar
5s
w.
ww

RESULT:
Thus the assembly language programs for various code conversions are executed using
8085 microprocessor.

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m
EX.No:4 4(a) INTERFACING A/D AND D/A CONVERTER WITH 8085

co
AIM:
To write an assembly language program to convert an analog signal into a digital signal
and a digital signal into an analog signal using an ADC interfacing and DAC interfacing
respectively.

s.
A. ADC INTERFACING WITH 8085

APPARATUS REQUIRED:

te
SL.NO ITEM SPECIFICATION QUANTITY
1 Microprocessor kit 8085,Vi Microsystems 1
2 Power supply +5 V dc 1
3 ADC Interface board Vi Microsystems
no 1

PROBLEM STATEMENT:

To program starts from memory location 4100H. The program is executed for various
ar
values of analog voltage which are set with the help of a potentiometer. The LED display is
verified with the digital value that is stored in the memory location 4150H.

THEORY:
An ADC usually has two additional control lines: the SOC input to tell the ADC when
t

to start the conversion and the EOC output to announce when the conversion is complete. The
following program initiates the conversion process, checks the EOC pin of ADC 0419 as to
5s

whether the conversion is over and then inputs the data to the processor. It also instructs the
processor to store the converted digital data at RAM 4200H.

ALGORITHM:
w.

1. Select the channel and latch the address.

2. Send the start conversion pulse.
3. Read EOC signal.
4. If EOC =1 continue else go to step (3)
5. Read the digital output.
ww

6. Store it in a memory location.

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PROGRAM:

ADDRESS LABEL MNEMON ICS OPCO OPERA COMMENTS

m
DE ND
4100 MVI A 10 Select channel 0 and to

co
make accumulator low
4101
4102 OUT 0C8H
C8 Output the data
4103

s.
4104 MVI A A, 18
18 Make accumulator high
4105
4106 OUT 0C8H
C8 Display the data
4107

te
4108 MVI A 01 Make 01 to accumulator
4109
410A OUT 0D0H
D0 Display the data
410B
410C XRA no A XOR with accumulator
410D XRA A XOR with accumulator
410E XRA A XOR with accumulator
410F MVI A 00 Make 00 to accumulator
4110
ar
4111 OUT D0 Load D0 in output port
4112
4113 LOOP IN D8
4114
t

4115 ANI 01 01 Do and operation directly

5s

4116
4117 CPI 01 01 Compare with accumulator
4118
4119 JNZ LOOP Jump to specified address
411A
w.

411B
411C IN C0
411D
411E STA 4150 Store the data
ww

411F
4120
4121 HLT End the program

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ADC- CIRCUIT:

m
co
s.
te
no
t ar

SOC JUMPER SELECTION:

5s
w.
ww

J2 : SOC Jumper selection

J5 : Channel selection

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OBSERVATION

m
ANALOG VOLTAGE DIGITAL DATA ON HEX CODE IN
LED DISPLAY LOCATION 4150

co
s.
te
no
t ar
5s
w.
ww

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4(b) DAC INTERFACING WITH 8085

m
APPARATUS REQUIRED:

co
SL.NO ITEM SPECIFICATION QUANTITY
1 Microprocessor kit 8085,Vi Microsystems 1
2 Power supply +5 V dc 1
3 DAC Interface board Vi Microsystems 1

s.
SOFTWARE EXAMPLES

The following examples illustrate how to control the DAC using 8085 and generate

te
sine wave, saw tooth wave by means of software.

(a) SQUARE WAVE GENERATION:

no
The basic idea behind the generation of waveforms is the continuous generation of
Analog output of DAC. With 00(HEX) as input to DAC2, the analog output is -5V.
Similarly, with FF (Hex) as input, the output is +5V. Outputting digital data 00 and FF at
regular intervals, to DAC2, results in a square wave of amplitude I5 Volts
ar
ALGORITHM:

1. Load the initial value (00) to Accumulator and move it to DAC.

2. Call the delay program
t

3. Load the final value (FF) to accumulator and move it to DAC.

4. Call the delay program.
5s

5. Repeat steps 2 to 5.

PROGRAM:

ADDRESS LABEL MNEMON ICS OPC OPERAND COMMENT

w.

ODE
4100 START MVI A 00 Move 00 to A register
4101
4102 OUT C8 Load C8 to output port
ww

4103
4104 CALL DELAY DELAY Call delay program
4107 MVI A FF Load FF to B register
4109 OUT C8
410B CALL DELAY DELAY
410E JMP START START Jump to start of address
4112 DELAY MVI B 05 Move 05 to B register
4114 L1 MVI C FF Move FF to C register

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4116 L2 DCR C Decrement C
4117 JNZ L2 L2 Jump to L2 if no zero

m
411A DCR B Decrement B register
411B JNZ L1 L1 Jump to L1 if no zero

co
411E RET

Execute the program and using a CRO, verify that the waveform at the DAC2 output is a
square-wave. Modify the frequency of the square-wave, by varying the time delay.

s.
(b) SAW TOOTH GENERATION:

ALGORITHM:

te
1. Load the initial value (00) to Accumulator
2. Move the accumulator content to DAC.
3. Increment the accumulator content by 1.
4. Repeat steps 3 and 4.
Output digital data from 00 to FF constant steps of 01 to DAC1 repeat this sequence again and
no
again. As a result a saw – tooth wave will be generated at DAC1 output.

PROGRAM:
ar
ADDRESS LABEL MNEMON ICS OPCO OPERAN COMMENT
DE D
4100 START MVI A 00 Load 00 to accumulator
4102 L1 OUT C0 Load CO in output port
t

4104 INR A Increment A register

4105 JNZ L1 L1 Jump to L1 if no zero
5s

4108 JMP START START Go to START

unconditionally

(c) TRIANGULAR WAVE GENERATION:

w.

ALGORITHM:

1. Load the initial value (00) to Accumulator.

2. Move the accumulator content to DAC
ww

3. Increment the accumulator content by 1.

4. If accumulator content is zero proceed to next step. Else go to step 3.
5. Load value (FF) to accumulator.
6. Move the accumulator content to DAC.
7. Decrement the accumulator content by 1.
8. If accumulator content is zero go to step 2. Else go to step 2.

The following program will generate a triangular wave at DAC2 output.

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PROGRAM:

ADDRESS LABEL MNEMON ICS OPC OPERA COMMENT

m
ODE ND
START MVI L 00 Move 00 to L register

co
L1 MOV A,L Load L to a register
OUT C8 Load c8 to output port
INR L Increment L register
JNZ L1 L1 Jump to L1 if no zero

s.
MVI L FF Load FF to L register
L2 MOV A,L Move L to a register
OUT C8 Load C8 to output port
DCR L Decrement L register

te
JNZ L2 L2 Jump to L2 if no zero
JMP START START Go to START unconditionally

no
t ar
5s
w.
ww

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DAC - CIRCUIT:

m
co
s.
te
WAEFORMS:
no
t ar
5s
w.
ww

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OBSERVATION:

WAVE FORMS AMPLITUDE TIME PERIOD

m
Square waveform
Saw tooth waveform

co
Triangular waveform

s.
te
no
t ar
5s
w.
ww

Result:
Thus the conversion of an analog signal into a digital signal and a digital signal into an
analog signal was done using interfacing of ADC and DAC respectively with 8085.

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EX.No:5 TRAFFIC LIGHT CONTROLLER WITH 8085

m
AIM

co
To write an assembly language program to simulate the traffic light at an intersection
using a traffic light interface.

APPARATUS REQUIRED:

s.
SL.NO ITEM SPECIFICATION QUANTITY
1 Microprocessor kit 4185,Vi Microsystems 1
2 Power supply +5 V dc 1
3 Traffic light interface kit Vi Microsystems 1

te
ALGORITHM:
1. Initialize the ports.
2. Initialize the memory content, with some address to the data.
no
3. Read data for each sequence from the memory and display it through the ports.
4. After completing all the sequences, repeat from step2.

A SAMPLE SEQUENCE:
1. (a) Vehicles from south can go to straight or left.
ar
(b) Vehicles from west can cross the road.
(c) Each pedestrian can cross the road.
(d) Vehicles from east no movement.
(e) Vehicles from north, can go only straight.
t

2. All ambers are ON, indicating the change of sequence.

5s

3. (a) Vehicles from east can go straight and left.

(b) Vehicles from south, can go only left.
(c) North pedestrian can cross the road.
(d) Vehicles from north, no movement.
w.

(e) Vehicles from west, can go only straight.

4. All ambers are ON, indicating the change of sequence.

ww

5. (a) Vehicles from north can go straight and left.

(b) Vehicles from east, can go only left.
(c) West pedestrian can cross the road.
(d) Vehicles from west, no movement.
(e) Vehicles from south, can go only straight.

6. All ambers are ON, indicating the change of sequence.

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7. (a) Vehicles from west can go straight and left.
(b) Vehicles from north, can go only left.
(c) South pedestrian can cross the road.

m
(d) Vehicles from south, no movement.
(e) Vehicles from east, can go only straight.

co
8. All ambers are ON, indicating the change of sequence.

9. (a) All vehicles from all directions no movement.

s.
(b) All pedestrian can cross the road.

BIT ALLOCATION:

BIT LED BIT LED BIT LED

te
PA0 SOUTH LEFT PB0 NORTH LEFT PC0 WEST STRAIGHT
PA1 SOUTH RIGHT PB1 NORTH RIGHT PC1 NORTH STRAIGHT
PA2 SOUTH AMBER PB2 NORTH AMBER
no PC2 EAST STRAIGHT
PA3 SOUTH RED PB3 NORTH RED PC3 SOUTH STRAIGHT
PA4 EAST LEFT PB4 WEST LEFT PC4 NORTH PD
PA5 EAST RIGHT PB5 WEST RIGHT PC5 WEST PD
PA6 EAST AMBER PB6 WEST AMBER PC6 SOUTH PD
ar
PA7 EAST RED PB7 WEST RED PC7 EAST PD
t
5s
w.
ww

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m
PATH REPRESENTATION:

co
s.
te
no
t ar
5s

CONTROL ----- 0F ( FOR 8255 PPI )

PORT A ----- 0C
PORT B ----- 0D
w.

PORT C ----- 0E
ww

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m
PROGRAM :

co
ADDRESS LABEL MNEMON ICS OPCO OPER COMMENT
DE AND
4100 MVI A, 41 3E 41 Move 80 immediately to

s.
accumulator
A,41 A,41
4102 OUT CONTROL D3 0F Output contents of
accumulator to OF port
4104 LXI H,DATA_SQ Load address 417B to HL

te
register

4107 LXI D,DATA_E 11 41,87 Load address 4187 to DE

no register
410A CALL OUT CD 42,41 Call out address
410D XCHG EB Exchange contents of HL
with DE pair
410E MOV A,M 7E Move M content to
ar
accumulator
410F OUT PORT A D3 0C Load port A into output port
4111 CALL DELAY1 CD 66,41 Call delay address
4114 XCHG EB Exchange content of HL
t

with DE pair
4115 INX D 13 Increment the content of D
5s

4116 INX H 23 Increment the content of H

4117 CALL OUT CD 42,41 Call out the address
411A XCHG EB Exchange content of HL
with DE pair
w.

411B MOV A,M 7E Move M content to

accumulator
411C OUT PORT B D3 0D Load port B into output port
411E CALL DELAY1 CD 66,41 Call DELAY address
4121 XCHG EB Exchange content of HL
ww

with DE pair
4122 INX D 13 Increment D register
4123 INX H 23 Increment H register
4124 CALL OUT CD 42,41 Call specified address
4127 XCHG EB Exchange content of HL
with DE pair
4128 MOV A,M 7E Move M content to
accumulator

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4129 OUT PORT C D3 0E Load port C into output port
412B CALL DELAY1 CD 66,41 Call DELAY address

m
412E XCHG EB Exchange content of HL
with DE pair
412F INX D 13 Increment D register

co
4130 INX H 23 Increment H register
4131 CALL OUT CD 42,41 Call specified address
4134 XCHG EB Exchange content of HL
with DE pair

s.
4135 MOV A,M 7E Move M content to
accumulator
4136 OUT PORT C D3 0E Load port C into output port
4138 INX H 23 Increment H register

te
4139 MOV A,M 7E Move M content to
accumulator
413A OUT PORT A D3 0C Load port A into output port
413C CALL DELAY1 CD 66,41 Call DELAY address
413F JMP REPEAT C3
no 04,41 Jump to specified address
4142 MOV A,M 7E Move M content to
accumulator
4143 OUT PORT C D3 0E Load port C into output port
4145 INX H 23 Increment H register
ar
4146 MOV A,M 7E Move M content to
accumulator
4147 OUT PORT B D3 0D Load port B into output port
4149 INX H 23 Increment H register
t

414A MOV A,M 7E Move M content to

accumulator
5s

414B OUT PORT A D3 0C Load port A into output port

414D CALL DELAY CD 51,41 Call DELAY address
4150 RET C9 Return to accumulator
4151 PUSH H E5 Push the register H
4152 LXI H,001F 21 1F,00 Load 00 1F in HL register
w.

pair
4155 LXI B,FFFF 01 FF,FF Load FF FF in DE register
pair
4158 DCX B 0B Decrement B register
ww

4159 MOV A,B 78 Move B content to

accumulator
415A ORA C B1 OR content of C with
accumulator
415B JNZ LOOP C2 58,41 Jump to LOOP if no zero
415E DCX H 2B Decrement H register
415F MOV A,L 7D Move L content to
accumulator

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4160 ORA H B4 OR content of H with
accumulator
4161 JNZ L1 C2 55,41 Jump to L1 if no zero

m
4164 POP H E1 Pop the register H
4165 RET C9 Return from subroutine

co
4166 PUSH H E5 Push the register H
4167 LXI H,001F 21 1F,00 Load 00 1F in HL register
pair
416A LXI B,FFFF 01 FF,FF Load FF FF in DE register

s.
pair
416D DCX B 0B Decrement B register
416E MOV A,B 78 Move B content to
accumulator

te
416F ORA C B1 OR content of C with
accumulator
4170 JNZ LOOP2 C2 6D,41 Jump to LOOP2 if no zero
4173 DCX H 2B Decrement H register
4174

4175
MOV A,L

ORA H
no 7D

B4
Move L
accumulator
OR
content

content of H with
to

accumulator
4176 JNZ L2 C2 6A,41 Jump to L2 if no zero
ar
4179 POP H E1 Pop the register H
417A RET C9 Return to subroutine
417B DATA 12 27 44 10 2B
SEQ DB 92 10 9D 84 48
t

2E 84
48 4B 20 49 04
5s
w.
ww

RESULT:
Thus an assembly language program to simulate the traffic light at an intersection using a
traffic light interfaces was written and implemented.

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EX.No:6 6(a) INTERFACING 8251 WITH 8085
AIM:

m
To write a program to initiate 8251 and to check the transmission and reception

co
of character.

APPARATUS REQUIRED:
1. 8085 Microprocessor kit

s.
2. 8251 Interface board
3. DC regulated power supply
THEORY:

te
The 8251 is used as a peripheral device for serial communication and is
programmed by the CPU to operate using virtually any serial data transmission technique.
The USART accepts data characters from the CPU in parallel format and the converts them
in a continuous serial data stream of transmission. Simultaneously, it can receive serial data
no
streams and convert them into parallel data characters for the CPU. The CPU can read the
status of USART at any time. These include data transmissions errors and control signals.

Prior to starting data transmission or reception ,the 8251 must be loaded with a
ar
set of control words generated by the CPU.These control signals define the complete
functional definition of the 8251 and must immediately follow a RESET operation. Control
words should be written in to the control register of 8251. words should be written in to the
control register of 8251.words should be written in to the control register of
8251.Thesecontrol words are split into two formats.
t

1. MODE INSTRUCTION WORD

2. COMMAND INSTRUCTION WORD.
5s

1. MODE INSTRUCTION WORD

This format defines the BAUD rate, character length, parity and stop bits required to
work with asynchronous data communication. by selecting the appropriate BAUD
w.

factor synchronous mode, the 8251 can be operated in synchronous mode.

Initializing 8251 using the Mode instructions to the following conditions.

ww

8 bit data
No parity
Baud rate factor(16X)
1 stop bit
Gives a mode command word of 01001110=4E(X)

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ALGORITHM
1. Initialize timer (8253) IC
2. Move the Mode command word (4EH) to A reg.

m
3. Output it port address C2
4. Move the command instruction word (37H) to A reg.

co
5. Output it to port address C2
6. Move the data to be transfer to A reg.
7. Output it to port address C0.
8. Reset the system

s.
9. Get the data through input port address C0.
10. Store the value in memory
11. Reset the system

PROGRAM:

te
ADDRES LA MNEMON OPC OPE COMMENT
S BE ICS ODE RAN
L noD
4100 MVI A 36 Move 36 to A
4102 OUT CE Output contents of accumulator to CE
port
4104 MVI A 0A Move 0A to accumulator
ar
4106 OUT C8 Output contents of accumulator to C8
port
4108 MVI A 00 Move 00 to accumulator
410A OUT C8 Output contents of accumulator to C8
t

port
410C LXI H 4200 Store 4200 address in HL register pair
5s

410F MVI A 4E Move 4E to accumulator

4111 OUT C2 Output contents of accumulator to C2
port
4113 MVI A 37 Move 37 to accumulator
w.

4115 OUT C2 Output contents of accumulator to C2

port
4117 MVI A 41 Move 41 to accumulator
4119 OUT C0 Output contents of accumulator to C0
ww

port
411B RST1
4200 IN C0 Input the contents from port C0 to
accumulator
4202 STA 4150 Store the output from accumulator to
4150
4205 RST1

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SYNCHRONOUS MODE:

m
co
S2 S1 EP PEN L2 L1 B2 B1

0 1 0 1

s.
0 0 1 1
5 6 7 8
BIT BIT BIT BIT

te
PARITY ENABLE
1-Enable
0-Disable
no EVEN PARITY GENERATION
0-Odd
1-Even
ar

EXTERNAL SYNC DETECT

1-Sysdetect is an input
0- Sysdetect is an output
t

SINGLE CHARACTER SYNC

5s

1-Single sync character

0- Double sync character
w.
ww

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ASYNCHRONOUS MODE:

m
S2 S1 EP PEN L2 L1 B2 B1

co
0 1 0 1
0 0 1 1

s.
Synch (1 X) (16 X) (64 X)
mode

te
0 1 0 1
0 0 1 1
5 6 7 8
no BIT BIT BIT BIT
ar
PARITY ENABLE
1-Enable
0-Disable
t

EVEN PARITY GENERATION

0-Odd
5s

1-Even
w.

0 1 0 1
0 0 1 1
Invalid 61BIT 1.5BIT 2 BIT
ww

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m
OBSERVATION:

co
MEMORY LOCATION INPUT DATA OUTPUT DATA

s.
te
no
t ar
5s
w.
ww

RESULT:
Thus the program to initiate 8251 was written and the transmission and reception of
character was checked by interfacing 8251 with 8085.

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6(b) INTERFACING 8253 TIMER WITH 8085

m
co
AIM:
To interface 8253 Interface board to 8085 microprocessor to demonstrate the generation of
square wave.

s.
APPARATUS REQUIRED:
1. 8085 microprocessor kit
2. 8253 Interface board
3. DC regulated power supply

te
4. CRO.

.
PROGRAM:

Address Opcodes Label

no
Mnemonic Operands Comments
4100 3E 36 START: MVI A, 36 Channel 0 in mode 3
4102 D3 CE OUT CE Send Mode Control word
ar
4104 3E 0A MVI A, 0A LSB of count
4106 D3 C8 OUT C8 Write count to register
4108 3E 00 MVI A, 00 MSB of count
410A D3 C8 OUT C8 Write count to register
t

410C 76 HLT
5s

Set the jumper, so that the clock 0 of 8253 is given a square wave of frequency 1.5
MHz. This program divides this PCLK by 10 and thus the output at channel 0 is 150 KHz.

Vary the frequency by varying the count. Here the maximum count is FFFF H. So, the
square wave will remain high for 7FFF H counts and remain low for 7FFF H counts. Thus
w.

with the input clock frequency of 1.5 MHz, which corresponds to a period of 0.067
microseconds, the resulting square wave has an ON time of 0.02184 microseconds and an OFF
time of 0.02184 microseconds.
ww

To increase the time period of square wave, set the jumpers such that CLK2 of 8253 is
connected to OUT 0. Using the above-mentioned program, output a square wave of frequency
150 KHz at channel 0. Now this is the clock to channel 2.

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CONTROL WORD:

m
SC1 SC2 RW1 RW0 M2 M1 M0 BCD

co
SC-SELECT COUNTER:

SC1 SC0 SELECT COUNTER

s.
0 0 Select counter 0
0 1 Select counter 1

te
1 0 Select counter 2

1 1 Read back command

M-MODE:
no
M2 M1 M0 MODE
0 0 0 Mode 0
ar
0 0 1 Mode 1
X 1 0 Mode 2
X 1 1 Mode 3
1 0 0 Mode 4
1 0 1 Mode 5
t

READ/WRITE:
5s

RW1 RW0
0 0 Counter latch command
w.

0 1 R/W least significant bit only

1 0 R/W most significant bit only

1 1 R/W least sig first and most sig byte

ww

BCD:

0 Binary counter 16-bit

1 Binary coded decimal counter

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m
co
s.
te
no
t ar
5s
w.
ww

Result:
Thus the 8253 has been interfaced to 4185 p and six different modes of 8253 have
been studied.

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6(c) INTERFACING 8279 WITH 8085

m
co
AIM:
To interface 8279 Programmable Keyboard Display Controller to 8085 Microprocessor.

APPARATUS REQUIRED:

s.
1. 8085 Microprocessor toolkit.
2. 8279 Interface board
3. Regulated D.C. power supply.

te
PROGRAM:

ADDRESS LABEL MNEMON ICSno OPCO OPERA COMMENT

DE ND

4100 START LXI H 4130 Store the 16 bit address

H, 4130H in HL pair
ar
4103 MVI D D, 0FH
0F Move 0F to D register
4105 MVI A 10 Move 10 to A

4107 OUT C2 Output the contents of

t

A to C2 output port
C2H
4109 MVI A A,CC
90H Move CC to A
5s

410B OUT C2 Output the contents of

A to C2 output port
410D MVI A A,90
90H Move 90 to A
w.

410F OUT C2 Output the contents of

C2H A to C2 output port
4111 LOOP MOV A, M Move content of M to
A
ww

4112 OUT C0H

C0 Output the contents of
M to A
4114 CALL DELAY DELAY Call the delay address
DELAY
4117 INX H Increment H register

4118 DCR D Decrement D register

D

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4119 JNZ LOOP LOOP Jump to specified
address
411C JMP START START
START Jump to START

m
address
411F DELAY MVI B A0 Move a to B register

co
4121 LOOP1 MVI C FF Move FF to C register

4123 LOOP2 DCR C Decrement C register

s.
4124 JNZ LOOP 1 LOOP 1 Jump to LOOP 1 if no
zero
4127 DCR B Decrement B register

te
4128 JNZ LOOP 2 LOOP 2 Jump to LOOP 2 if no
zero
412B RET
no
Pointer equal to 4130 .FF repeated eight times

4130 FF
4131 FF
ar
4132 FF
4133 FF
4134 FF
4135 FF
t

4136 FF
4137 FF
5s

4138 98
4139 68
413ª 7C
413B C8
w.

413C 1C
413D 29
413E FF
413F FF
ww

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m
SEGMENT DEFINITION:

co
s.
te
DATA BUS D7 D6 D5 D4
no
D3 D2 D1 D0
SEGMETS d c b a dp g f e
ar
OBSERVATION:

LETTER 7 DATA BUS

SEGMENT HEXADECIMAL
t

D7 D6 D5 D4 D3 D2 D1 D0
5s
w.
ww

RESULT:

Thus 8279 controller was interfaced with 8085 and program for rolling display was executed
successfully.

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m
co
s.
te
no
ar

MICROCONTROLLER
t
5s
w.
ww

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m
Ex.No:7 7(a) 8051 - SUM OF ELEMENTS IN AN ARRAY

co
AIM:
To find the sum of elements in an array.
ALGORITHM:

s.
1. Load the array in the consecutive memory location and initialize the
memory pointer with the starting address.
2. Load the total number of elements in a separate register as a counter.

te
3. Clear the accumulator.
4. Load the other register with the value of the memory pointer.
5. Add the register with the accumulator.
no
6. Check for carry, if exist, increment the carry register by 1. otherwise,
continue
7. Decrement the counter and if it reaches 0, stop. Otherwise increment the
ar
memory pointer by 1 and go to step 4.
t
5s
w.
ww

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m
PROGRAM:

co
ADDRESS OPCODE LABEL MNEMONICS OPERAND COMMENT
4100 MOV DPTR, #4200
4103 MOVX A, @DPTR
4104 MOV R0, A

s.
4105 MOV B, #00
4108 MOV R1, B

te
410A ADD CLR C C3
410B INC DPTR A3
410C MOVX A, @DPTR
410D
410F
no
ADD
MOV
A, B
B, A
4111 JNC NC
ar
4113 INC R1
4114 NC INC DPTR
4116 MOV DPTR, #4500
t

4119 MOV A, R1
411A MOVX @DPTR, A
5s

411B INC DPTR

411C MOV A, B
w.

411E MOVX @DPTR, A

411F SJMP HLT
ww

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m
OBSERVATION:

co
INPUT OUTPUT
4200 4500

s.
4201
4202
4203 4501

te
no
t ar
5s
w.
ww

RESULT:
The sum of elements in an array is calculated.

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m
co
7(b) 8051 - SUM USING STACK
AIM:
To find the sum of elements in an array using stack.

s.
ALGORITHM:
1. Start
2. Move the data to stack pointer

te
3. Move the data to accumulator
4. Move the data to reg B
5. Move the data to DPL no
6. Push the value of A to stack
7. Push the value of B to stack
8. Push the value of DPL to stack
ar
9. Halt
t
5s
w.
ww

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m
PROGRAM:

co
ADDRESS OPCODE LABEL MNEMONICS OPERAND COMMENT
4100 MOV SP, #67 67
4103 MOV A, #88 88
4105 MOV B, #66 66

s.
4108 MOV DPL, #43 43
410B PUSH A

te
410D PUSH B
410F PUSH DPL
4111 SJMP
no
t ar
5s
w.
ww

RESULT:
The sum of elements in an array is calculated.

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m
7(c) 8051 - SUM USING CALL OPTION

co
AIM:
To find the sum of elements in an array using call option.
ALGORITHM:

s.
1. Start
2. Move the data to DPTR
3. Move the data to accumulator

te
4. Adjacent call 4200
5. Add A & R0
6. Move the 16 bit data from A to DPTR
no
7. Move the data to accumulator
8. Move the data to R0
9. Return to 4107
t ar
5s
w.
ww

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m
PROGRAM:

co
ADDRESS OPC LABEL MNEMONICS OPERAND COMMENT
ODE
4100 MOV DPTR,# 4300 43,00
4103 MOV A, # 00 00

s.
4105 ACALL 4200 42,00
4108 ADD A, R0
410B MOVX @DPTR,A 80

te
410D SJMP
410F MOVA,#02 02
4111 MOV R0, #01
no 01
RET
t ar
5s

OBSERVATION:
w.

INPUT OUTPUT
4200 4300
ww

4202

RESULT:
The sum of elements in an array using call option is calculated is calculated.

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Ex.No:8 8(a) STEPPER MOTOR INTERFACING WITH 8051

m
AIM:

co
To interface a stepper motor with 8051 microcontroller and operate it.

THEORY:
A motor in which the rotor is able to assume only discrete stationary angular position is

s.
a stepper motor. The rotary motion occurs in a step-wise manner from one equilibrium position
to the next. Stepper Motors are used very wisely in position control systems like printers, disk
drives, process control machine tools, etc.
The basic two-phase stepper motor consists of two pairs of stator poles. Each of the
four poles has its own winding. The excitation of any one winding generates a North Pole. A

te
South Pole gets induced at the diametrically opposite side. The rotor magnetic system has two
end faces. It is a permanent magnet with one face as South Pole and the other as North Pole.
The Stepper Motor windings A1, A2, B1, B2 are cyclically excited with a DC current
to run the motor in clockwise direction. By reversing the phase sequence as A1, B2, A2, B1,
anticlockwise stepping can be obtained.

2-PHASE SWITCHING SCHEME:

no
In this scheme, any two adjacent stator windings are energized. The switching scheme
is shown in the table given below. This scheme produces more torque.
ar

ANTICLOCKWISE CLOCKWISE
STEP A1 A2 B1 B2 DATA STEP A1 A2 B1 B2 DATA
t

1 1 0 0 1 9h 1 1 0 1 0 Ah
2 0 1 0 1 5h 2 0 1 1 0 6h
5s

3 0 1 1 0 6h 3 0 1 0 1 5h
4 1 0 1 0 Ah 4 1 0 0 1 9h

ADDRESS DECODING LOGIC:

The 74138 chip is used for generating the address decoding logic to generate the device
w.

select pulses, CS1 & CS2 for selecting the IC 74175.The 74175 latches the data bus to the
stepper motor driving circuitry.
Stepper Motor requires logic signals of relatively high power. Therefore, the interface
circuitry that generates the driving pulses use silicon darlington pair transistors. The inputs for
ww

the interface circuit are TTL pulses generated under software control using the Microcontroller
Kit. The TTL levels of pulse sequence from the data bus is translated to high voltage output
pulses using a buffer 7407 with open collector.

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m
co
BLOCK DIAGRAM:

s.
8051
MICROCONTROLLER 8255
DRIVER CIRCUIT STEPPER MOTOR

te
no
ar
REPRESENTATION:
t
5s
w.
ww

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PROGRAM :

MNEM

m
Address OPCODES Label OPERAND Comments
ONICS
ORG 4100h

co
4100 START MOV DPTR, #TABLE Load the start address
of switching scheme
data TABLE into Data

s.
Pointer (DPTR)
4103 MOV R0, #04 Load the count in R0
4105 LOOP: MOVX A, @DPTR Load the number in
TABLE into A

te
4106 PUSH DPH Push DPTR value to
4108 PUSH DPL Stack
410A MOV DPTR, #0FFC0h Load the Motor port
address into DPTR
410D MOVX
no @DPTR, A Send the value in A to
stepper Motor port
address
410E MOV R4, #0FFh Delay loop to cause a
4110 DELA MOV R5, #0FFh specific amount of
ar
Y: time delay before next
4112 DELA DJNZ R5, DELAY1 data item is sent to the
Y1: Motor
4114 DJNZ R4, DELAY
t

4116 POP DPL POP back DPTR value

4118 POP DPH from Stack
5s

411A INC DPTR Increment DPTR to

point to next item in
the table
411B DJNZ R0, LOOP Decrement R0, if not
zero repeat the loop
w.

411D SJMP START Short jump to Start of

the program to make
the motor rotate
continuously
ww

411F TABLE DB 09 05 06 0Ah Values as per two-

: phase switching
scheme

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PROCEDURE:
1. Enter the above program starting from location 4100.and execute the same.

m
2. The stepper motor rotates.
3. Varying the count at R4 and R5 can vary the speed.

co
4. Entering the data in the look-up TABLE in the reverse order can vary direction of
rotation.

s.
te
no
t ar
5s
w.
ww

RESULT:
Thus a stepper motor was interfaced with 8051 and run in forward and reverse
directions at various speeds.

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8 (b) INTERFACING D/A CONVERTER WITH 8051

m
AIM:

co
To interface DAC with 8051 to demonstrate the generation of square, saw tooth and
triangular wave.

APPARATUS REQUIRED:

s.
SL.NO ITEM SPECIFICATION QUANTITY
1 Microprocessor kit 4185,Vi Microsystems 1
2 Power supply +5 V dc 1
3 DAC Interface board Vi Microsystems 1

te
THEORY:

SOFTWARE EXAMPLES no
After going through the software examples you can learn how to control the
DAC using 8051 and generate sine wave, saw tooth wave etc by means of software.
ar
ALGORITHM:

(a) SQUARE WAVE GENERATION:

1. Load the initial value (00) to Accumulator and move it to DAC.
t

2. Call the delay program

3. Load the final value (FF) to accumulator and move it to DAC.
5s

4. Call the delay program.

5. Repeat steps 2 to 5.
w.
ww

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DAC - CIRCUIT:

m
co
s.
te
no
ar
WAVEFORMS:
t
5s
w.
ww

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m
OBSERVATION:

co
WAVE FORMS AMPLITUDE TIME PERIOD
Square waveform
Saw tooth waveform

s.
Triangular waveform

PROGRAM:
The basic idea behind the generation of waveforms is the continuous generation of

te
Analog output of DAC.
With 00(HEX) as input to DAC2, the analog output is -5V. Similarly, with FF (Hex) as
input, the output is +5V. Outputting digital data 00 and FF at regular intervals, to DAC2,
results in a square wave of amplitude I5 Volts.

ADDRESS LABEL MNEMON ICS

MOV DPTR,#FFC8
no OPCODE OPERAND COMMENT

START MOV A,#00

MOVX @DPTR,A
ar
LCALL DELAY
MOV A,# FF
MOVX @DPTR,A
LCALL DELAY
t

LJMP START
DELAY MOV R1,#05
LOO[P MOV R2,#FF
5s

DJNZ R2,HERE
DJNZ R1,LOOP
RET
SJMP START
w.

Execute the program and using a CRO, verify that the waveform at the DAC2 output is
a square-wave. Modify the frequency of the square-wave, by varying the time delay.

(b) SAW TOOTH GENERATION

ww

1. Load the initial value (00) to Accumulator

2. Move the accumulator content to DAC.
3. Increment the accumulator content by 1.
4. Repeat steps 3 and 4.
Output digital data from 00 to FF constant steps of 01 to DAC1 repeat this sequence again and
again. As a result a saw – tooth wave will be generated at DAC1 output.

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PROGRAM:

m
ADDRESS LABEL MNEMON ICS OPCODE OPERAND COMMENT

co
MOV DPTR,#FFC0
MOV A,#00
LOOP MOVX @DPTR,A
INC A

s.
SJMP LOOP

(c) TRIANGULAR WAVE GENERATION

1. Load the initial value (00) to Accumulator.

te
2. Move the accumulator content to DAC
3. Increment the accumulator content by 1.
4. If accumulator content is zero proceed to next step. Else go to step 3.
5. Load value (FF) to accumulator.
6. Move the accumulator content to DAC.
no
7. Decrement the accumulator content by 1.
8. If accumulator content is zero go to step 2. Else go to step 2.

The following program will generate a triangular wave at DAC2 output. The program is
ar
self explanatory.

ADDRESS LABEL MNEMON ICS OPCODE OPERAND COMMENT

MOV DPTR,#FFC8
START MOV A,#00
t

LOOP1 MOVX @DPTR,A

INC A
5s

JNZ LOOP1
MOV A,#FF
LOOP2 MOVX @DPTR,A
DEC A
w.

JNZ LOOP2
LJMP START

OBSERVATION:
ww

WAVE FORMS AMPLITUDE TIME PERIOD

Square waveform
Saw tooth waveform
Triangular waveform

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m
co
s.
te
no
t ar
5s
w.
ww

Result:
Thus the square, triangular and saw tooth wave form were generated by interfacing
DAC with 8051 trainer kit.

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Ex. No: 9 STUDY OF BASIC DIGITAL ICS

m
AIM:

co
To verify the truth table of basic digital ICs of AND, OR, NOT, NAND, NOR, EX-OR
gates.

s.
APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1

te
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5.
6.
NAND gate
NOR gate
no IC 7400
IC 7402
1
1
7. EX-OR gate IC 7486 1
ar
8. Connecting wires As required

THEORY:
t

a. AND gate:
5s

An AND gate is the physical realization of logical multiplication operation. It is

an electronic circuit which generates an output signal of ‘1’ only if all the input signals
are ‘1’.
w.

b. OR gate:

An OR gate is the physical realization of the logical addition operation. It is an

electronic circuit which generates an output signal of ‘1’ if any of the input signal is ‘1’.
ww

c. NOT gate:

A NOT gate is the physical realization of the complementation operation. It is

an electronic circuit which generates an output signal which is the reverse of the input
signal. A NOT gate is also known as an inverter because it inverts the input.

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d. NAND gate:

m
A NAND gate is a complemented AND gate. The output of the NAND gate
will be ‘0’ if all the input signals are ‘1’ and will be ‘1’ if any one of the input signal is

co
‘0’.

e. NOR gate:

s.
A NOR gate is a complemented OR gate. The output of the OR gate will be ‘1’
if all the inputs are ‘0’ and will be ‘0’ if any one of the input signal is ‘1’.

f. EX-OR gate:

te
An Ex-OR gate performs the following Boolean function,

A B = ( A . B’ ) + ( A’ . B )
no
It is similar to OR gate but excludes the combination of both A and B being
equal to one. The exclusive OR is a function that give an output signal ‘0’ when the
two input signals are equal either ‘0’ or ‘1’.
ar
PROCEDURE:

1. Connections are given as per the circuit diagram

1. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.
t

2. Apply the inputs and verify the truth table for all gates.
5s

AND GATE

LOGIC DIAGRAM:
w.
ww

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PIN DIAGRAM OF IC 7408:

m
co
s.
CIRCUIT DIAGRAM:

te
no
ar

TRUTH TABLE:

INPUT OUTPUT
t

S.No
A B Y=A.B
1. 0 0 0
5s

2. 0 1 0
3. 1 0 0
4. 1 1 1
w.

OR GATE

LOGIC DIAGRAM:
ww

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PIN DIAGRAM OF IC 7432 :

m
co
s.
te
CIRCUIT DIAGRAM:

no
ar

TRUTH TABLE:
t
5s

INPUT OUTPUT
S.No
A B Y=A+B
1. 0 0 0
2. 0 1 1
w.

3. 1 0 1
4. 1 1 1

NOT GATE
ww

LOGIC DIAGRAM:

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PIN DIAGRAM OF IC 7404 :

m
co
s.
te
CIRCUIT DIAGRAM: no
t ar

TRUTH TABLE:
5s

INPUT OUTPUT
S.No
A Y = A’
1. 0 1
2. 1 0
w.

NAND GATE
ww

LOGIC DIAGRAM:

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m
PIN DIAGRAM OF IC 7400 :

co
s.
te
CIRCUIT DIARAM:
no
t ar
5s

TRUTH TABLE:

INPUT OUTPUT
w.

S.No
A B Y = (A. B)’
1. 0 0 1
2. 0 1 1
3. 1 0 1
ww

4. 1 1 0

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NOR GATE

LOGIC DIAGRAM:

m
co
s.
PIN DIAGRAM OF IC 7402 :

te
no
ar

CIRCUIT DIAGRAM:
t
5s
w.

TRUTH TABLE:
ww

INPUT OUTPUT
S.No
A B Y = (A + B)’
1. 0 0 1
2. 0 1 0
3. 1 0 0
4. 1 1 0

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EX-OR GATE

m
LOGIC DIAGRAM

co
s.
PIN DIAGRAM OF IC 7486:

te
no
ar

CIRCUIT DIAGRAM:
t
5s

TRUTH TABLE:
w.

INPUT OUTPUT
S.No
A B Y=A B
1. 0 0 0
ww

2. 0 1 1
3. 1 0 1
4. 1 1 0

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m
co
s.
te
no
t ar
5s
w.
ww

RESULT:

The truth tables of all the basic digital ICs were verified.
.

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EX.NO.10 DESIGN AND IMPLEMENTATION OF ADDER/SUBTRACTOR

m
AIM:

co
To design and construct half adder, full adder, half subtractor and full subtractor
circuits and verify the truth table using logic gates.
APPARATUS REQUIRED:

s.
S. No Name Specification Quantity
1. IC 7432, 7408, 7486, 7483 1
2. Digital IC Trainer Kit 1

te
3. Patch chords -

THEORY: no
The most basic arithmetic operation is the addition of two binary digits. There are four
possible elementary operations, namely,
ar
0+0=0
0+1=1
1+0=1
1 + 1 = 102
t

The first three operations produce a sum of whose length is one digit, but when the last
operation is performed the sum is two digits. The higher significant bit of this result is called a
5s

carry and lower significant bit is called the sum.

HALF ADDER:

A combinational circuit which performs the addition of two bits is called half adder.
w.

The input variables designate the augend and the addend bit, whereas the output variables
produce the sum and carry bits.

FULL ADDER:
ww

A combinational circuit which performs the arithmetic sum of three input bits is called
full adder. The three input bits include two significant bits and a previous carry bit. A full
adder circuit can be implemented with two half adders and one OR gate.

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HALF ADDER

TRUTH TABLE:

m
INPUT OUTPUT

co
S.No
A B S C
1. 0 0 0 0
2. 0 1 1 0
3. 1 0 1 0

s.
4. 1 1 0 1

DESIGN:

te
From the truth table the expression for sum and carry bits of the output can be
obtained as, Sum, S = A B ; Carry, C = A . B

CIRCUIT DIAGRAM: no
t ar
5s

FULL ADDER

TRUTH TABLE:
w.

INPUT OUTPUT
S.No
A B C SUM CARRY
1. 0 0 0 0 0
2. 0 0 1 1 0
ww

3. 0 1 0 1 0
4. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 1
7. 1 1 0 0 1
8. 1 1 1 1 1

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DESIGN:

From the truth table the expression for sum and carry bits of the output can be obtained

m
as,SUM = A’B’C + A’BC’ + AB’C’ + ABC;CARRY = A’BC + AB’C + ABC’ +ABC
Using Karnaugh maps the reduced expression for the output bits can be obtained as,

co
SUM

s.
SUM = A’B’C + A’BC’ + AB’C’ + ABC = A B C

te
CARRY

no
ar
CARRY = AB + AC + BC

CIRCUIT DIAGRAM:
t
5s
w.
ww

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HALF SUBTRACTOR:

A combinational circuit which performs the subtraction of two bits is called half

m
subtractor. The input variables designate the minuend and the subtrahend bit, whereas the
output variables produce the difference and borrow bits.

co
FULL SUBTRACTOR:

A combinational circuit which performs the subtraction of three input bits is called full

s.
subtractor. The three input bits include two significant bits and a previous borrow bit. A full
subtractor circuit can be implemented with two half subtractors and one OR gate.

HALF SUBTRACTOR

te
TRUTH TABLE:

INPUT OUTPUT
S.No no
A B DIFF BORR
1. 0 0 0 0
2. 0 1 1 1
3. 1 0 1 0
ar
4. 1 1 0 0

DESIGN:

From the truth table the expression for difference and borrow bits of the output can be
t

obtained as, Difference, DIFF = A B; Borrow, BORR = A’ . B

5s

CIRCUIT DIAGRAM:
w.
ww

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FULL SUBTRACTOR
TRUTH TABLE:

m
INPUT OUTPUT
S.No
A B C DIFF BORR

co
1. 0 0 0 0 0
2. 0 0 1 1 1
3. 0 1 0 1 1
4. 0 1 1 0 1

s.
5. 1 0 0 1 0
6. 1 0 1 0 0
7. 1 1 0 0 0
8. 1 1 1 1 1

te
DESIGN:

From the truth table the expression for difference and borrow bits of the output can be
obtained as, no
Difference, DIFF= A’B’C + A’BC’ + AB’C’ + ABC
Borrow, BORR = A’BC + AB’C + ABC’ +ABC
ar
Using Karnaugh maps the reduced expression for the output bits can be obtained as,

DIFFERENCE
t
5s

DIFF = A’B’C + A’BC’ + AB’C’ + ABC = A B C

w.

BORROW
ww

BORR = A’B + A’C + BC

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CIRCUIT DIAGRAM:

m
co
s.
te
PROCEDURE:

 The connections are given as per the circuit diagram.

 Two 4 – bit numbers added or subtracted depend upon the control input and the
no
output is obtained.
 Apply the inputs and verify the truth table for thehalf adder or s subtractor and
full adder or subtractor circuits.
t ar
5s
w.
ww

RESULT:
Thus the half adder, full adder, half subtractor and full subtractor circuits were designed
and their truth table were verified.

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EX.NO.11 11(a) CODE CONVERTER

m
AIM:

co
To construct and verify the performance of binary to gray and gray to binary.

APPARATUS REQUIRED:

s.
S. No Name Specification Quantity

te
1. IC 7404, 7486 1
2. Digital IC Trainer Kit 1
3. Patch chords -

THEORY:
no
BINARY TO GRAY:
ar
The MSB of the binary code alone remains unchanged in the Gray code. The remaining
bits in the gray are obtained by EX-OR ing the corresponding gray code bit and previous bit in
the binary code. The gray code is often used in digital systems because it has the advantage
t

that only one bit in the numerical representation changes between successive numbers.
5s

GRAY TO BINARY:
The MSB of the Gray code remains unchanged in the binary code the remaining bits are
obtained by EX – OR ing the corresponding gray code bit and the previous output binary bit.
w.

PROCEDURE:
 Connections are given as per the logic diagram.
ww

 The given truth tables are verified.

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BINARY TO GRAY:

m
co
s.
te
no
GRAY TO BINARY
t ar
5s
w.
ww

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TRUTH TABLE

Decimal Binary code Gray code

m
D C B A G3 G2 G1 GO

co
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
2 0 0 1 0 0 0 1 1
3 0 0 1 1 0 0 1 0

s.
4 0 1 0 0 0 1 1 0
5 0 1 0 1 0 1 1 1
6 0 1 1 0 0 1 0 1
7 0 1 1 1 0 1 0 0

te
8 1 0 0 0 1 1 0 0
9 1 0 0 1 1 1 0 1
10 1 0 1 0 1 1 1 1
11 1 0 no 1 1 1 1 1 0
12 1 1 0 0 1 0 1 0
13 1 1 0 1 1 0 1 1
14 1 1 1 0 1 0 0 1
ar
15 1 1 1 1 1 0 0 0
t
5s
w.

RESULT:
ww

The design of the three bit Binary to Gray code converter & Gray to Binary code
converter circuits was done and its truth table was verified.

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11(b) ENCODER

m
AIM:

co
To design and implement encoder using IC 74148 (8-3 encoder)
APPARATUS REQUIRED:

S. No Name Specification Quantity

s.
1. IC 74148 1
2. Digital IC Trainer Kit 1

te
3. Patch chords -

THEORY:
An encoder is digital circuit that has 2n input lines and n output lines. The output lines
no
generate a binary code corresponding to the input values 8 – 3 encoder circuit has 8 inputs, one
for each of the octal digits and three outputs that generate the corresponding binary number.
ar
Enable inputs E1 should be connected to ground and Eo should be connected to VCC

PROCEDURE:
t

 Connections are given as per the logic diagram.

 The truth table is verified by varying the inputs.
5s

PIN DIAGRAM
w.

1 1
2N INPUT 2
ENCODER 2 N OUTPUT
ww

N-1
2 N
N
2

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m
co
s.
te
TRUTH TABLE

INPUTS no OUTPUTS
E1 A0 A1 A2 A3 A4 A5 A6 A7 D2 D1 D0
0 0 1 1 1 1 1 1 1 0 0 0
0 1 0 1 1 1 1 1 1 0 0 1
0 1 1 0 1 1 1 1 1 0 1 0
ar
0 1 1 1 0 1 1 1 1 0 1 1
0 1 1 1 1 0 1 1 1 1 0 0
0 1 1 1 1 1 0 1 1 1 0 1
0 1 1 1 1 1 1 0 1 1 1 0
t

0 1 1 1 1 1 1 1 0 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1
5s
w.
ww

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11(c) DECODER
AIM:

m
To design and implement decoder using IC 74155 (3-8 decoder).

co
APPARATUS REQUIRED:

s.
S. No Name Specification Quantity
1. IC 74155 1
2. Digital IC Trainer Kit 1
3. Patch chords -

te
THEORY:
A decoder is a combinational circuit that converts binary information from n input lines
no
to 2n unique output lines.
In 3-8 line decoder the three inputs are decoded into right outputs in which each output
representing one of the minterm of 3 input variables. IC 74155 can be connected as a dual 2*4
ar
decoder or a single 3*8 decoder desired input in C1 and C2 must be connected together and used
as the C input. G1 and G2 should be connected and used as the G (enable) input. G is the
enable input and must be equal to 0 for proper operation.
t

PROCEDURE:
5s

 Connections are given as per the logic diagram.

 The truth table is verified by varying the inputs.
w.

CIRCUIT DIAGRAM:

1
1
2 N OUTPUT
N INPUT 2
DECODER
ww

2N-1
N 2N

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m
co
s.
te
TRUTH TABLE no
INPUTS OUTPUTS
G C B A 2Y0 2Y1 2Y2 2Y3 1Y0 1Y1 1Y2 1Y3
1 X X X 1 1 1 1 1 1 1 1
ar
0 0 0 0 0 1 1 1 1 1 1 1
0 0 0 1 1 0 1 1 1 1 1 1
0 0 1 0 1 1 0 1 1 1 1 1
0 0 1 1 1 1 1 0 1 1 1 1
t

0 1 0 0 1 1 1 1 0 1 1 1
0 1 0 1 1 1 1 1 1 0 1 1
5s

0 1 1 0 1 1 1 1 1 1 0 1
0 1 1 1 1 1 1 1 1 1 1 0
w.
ww

RESULT:
Thus the encoder and decoder circuits were designed and implemented.

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EX.NO.12 STUDY OF FLIP FLOPS

AIM:

m
To verify the characteristic table of RS, D, JK, and T Flip flops .

co
APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity

s.
1. Digital IC trainer kit 1
2. NOR gate IC 7402
3. NOT gate IC 7404
4. AND gate ( three input ) IC 7411

te
5. NAND gate IC 7400
6. Connecting wires As required

THEORY:
no
A Flip Flop is a sequential device that samples its input signals and changes its output
states only at times determined by clocking signal. Flip Flops may vary in the number of
inputs they possess and the manner in which the inputs affect the binary states.
ar
RS FLIP FLOP:

The clocked RS flip flop consists of NAND gates and the output changes its state with
respect to the input on application of clock pulse. When the clock pulse is high the S and R
inputs reach the second level NAND gates in their complementary form. The Flip Flop is
t

reset when the R input high and S input is low. The Flip Flop is set when the S input is high
and R input is low. When both the inputs are high the output is in an indeterminate state.
5s

D FLIP FLOP:

To eliminate the undesirable condition of indeterminate state in the SR Flip Flop when
w.

both inputs are high at the same time, in the D Flip Flop the inputs are never made equal at the
same time. This is obtained by making the two inputs complement of each other.

JK FLIP FLOP:
ww

The indeterminate state in the SR Flip-Flop is defined in the JK Flip Flop. JK inputs
behave like S and R inputs to set and reset the Flip Flop. The output Q is ANDed with K input
and the clock pulse, similarly the output Q’ is ANDed with J input and the Clock pulse.
When the clock pulse is zero both the AND gates are disabled and the Q and Q’ output retain
their previous values. When the clock pulse is high, the J and K inputs reach the NOR gates.
When both the inputs are high the output toggles continuously. This is called Race around
condition and this must be avoided.
T FLIP FLOP:

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This is a modification of JK Flip Flop, obtained by connecting both inputs J and K

inputs together. T Flip Flop is also called Toggle Flip Flop.

m
RS FLIP FLOP

co
LOGIC SYMBOL:

s.
te
CIRCUIT DIAGRAM:
no
t ar
5s

CHARACTERISTIC TABLE:

CLOCK INPUT PRESENT NEXT STATUS

w.

PULSE S R STATE (Q) STATE(Q+1)

1 0 0 0 0
2 0 0 1 1
3 0 1 0 0
ww

4 0 1 1 0
5 1 0 0 1
6 1 0 1 1
7 1 1 0 X
8 1 1 1 X
D FLIP FLOP

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LOGIC SYMBOL:

m
co
s.
CIRCUIT DIAGRAM:

te
no
t ar
5s

CHARACTERISTIC TABLE:
w.

CLOCK INPUT PRESENT NEXT STATUS

PULSE D STATE (Q) STATE(Q+1)

1 0 0 0
2 0 1 0
ww

3 1 0 1
4 1 1 1

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JK FLIP FLOP

LOGIC SYMBOL:

m
co
s.
te
CIRCUIT DIAGRAM:

no
t ar
5s

CHARACTERISTIC TABLE:
w.

CLOCK INPUT PRESENT NEXT STATUS

PULSE J K STATE (Q) STATE(Q+1)
1 0 0 0 0
2 0 0 1 1
ww

3 0 1 0 0
4 0 1 1 0
5 1 0 0 1
6 1 0 1 1
7 1 1 0 1
8 1 1 1 0

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T FLIP FLOP

m
LOGIC SYMBOL:

co
s.
te
CIRCUIT DIAGRAM:

no
t ar
5s
w.
ww

CHARACTERISTIC TABLE:

CLOCK INPUT PRESENT NEXT STATUS

PULSE T STATE (Q) STATE(Q+1)
1 0 0 0
2 0 1 0
3 1 0 1
4 1 1 0

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PROCEDURE:

m
1. Connections are given as per the circuit diagrams.
2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.

co
3. Apply the inputs and observe the status of all the flip flops.

s.
te
no
t ar
5s
w.
ww

RESULT:

The Characteristic tables of RS, D, JK, T flip flops were verified.

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EX.NO.13 13(a)ASYNCHRONOUS COUNTER

m
AIM:

co
To implement and verify the truth table of an asynchronous decade counter.

APPARATUS REQUIRED:

s.
S.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. JK Flip Flop IC 7473 2
4. NAND gate IC 7400 1

te
5. Connecting wires As required

THEORY:

Asynchronous decade counter is also called as ripple counter. In a ripple counter the
no
flip flop output transition serves as a source for triggering other flip flops. In other words the
clock pulse inputs of all the flip flops are triggered not by the incoming pulses but rather by the
transition that occurs in other flip flops. The term asynchronous refers to the events that do not
occur at the same time. With respect to the counter operation, asynchronous means that the
ar
flip flop within the counter are not made to change states at exactly the same time, they do not
because the clock pulses are not connected directly to the clock input of each flip flop in the
counter.

PIN DIAGRAM OF IC 7473:

t
5s
w.
ww

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m
CIRCUIT DIAGRAM:

co
s.
te
no
ar

TRUTH TABLE:

CLOCK OUTPUT
t

S.No D(MSB) C B A(LSB)

PULSE
1 - 0 0 0 0
5s

2 1 0 0 0 1
3 2 0 0 1 0
4 3 0 0 1 1
5 4 0 1 0 0
w.

6 5 0 1 0 1
7 6 0 1 1 0
8 7 0 1 1 1
9 8 1 0 0 0
ww

10 9 1 0 1 0
11 10 0 0 0 0

PROCEDURE:

1. Connections are given as per the circuit diagrams.

2. Apply the input and verify the truth table of the counter.

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m
co
s.
te
no
t ar
5s
w.
ww

RESULT:

The truth table of the Asynchronous counter was hence verified.

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EX.NO.13 13(b) SHIFT REGISTERS

m
AIM:

co
To implement the following shift register using flip flop
(i) SIPO
(ii) SISO

s.
(iii) PISO
(iv) PIPO
APPARATUS REQUIRED:

te
S. No Name Specification Quantity
1. IC 7474 1
2.
3.
Digital IC Trainer Kit
Patch chords
no 1
-
THEORY:
ar
A register is used to move digital data. A shift register is a memory in which
information is shifted from one position in to another position at a line when one clock pulse is
applied. The data can be shifted either left or right direction towards right or towards left.
t

A shift register can be used in four ways depending upon the input in which the data are
entered in to and takes out of it. The four configuration are given as
5s

 Serial input – Serial output

 Parallel input – Serial output
 Serial input – Parallel output
w.

 Parallel input – Parallel output

RS or JK flip flop are used to construct shift register have D flip flop is used for
constructing shift register.
ww

PROCEDURE:
 Give the connections as per the circuit
 Set or Reset at the pin 2 which it’s the MSB of serial data.
 Apply a single clock Set or Reset second digital input at pin 2.
 Repeat step 2 until all 4-bit data are taken away.

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SHIFT REGISTER:
_

m
+5VCC CLR2 D2 CLK PR2 Q2 Q2

co
14 13 12 11 10 9 8

IC 7474

s.
1 2 3 4 5 6 7

_
CLR1 D1 CLK PR1 Q1 Q1 GND

te
SIPO LEFT SHIFT
Q3

Q2 Q1
no Q0
+5VCC

10 4 10 4
2 12 D IN
12 5 9 5 2
9
IC 7474 IC 7474 IC 7474 IC 7474
ar
11 3 11 3
13 1 13 1

+5VCC
t

CLK
5s

SIPO RIGHT SHIFT

w.
ww

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m
SISO

co
DOUT

+5VCC

s.
10 4 10 4
2 12 D IN
12 5 9 5 2
9
IC 7474 IC 7474 IC 7474 IC 7474
11 3 11 3
13 1 13 1

te
+5VCC

no CLK

PIPO

Q2 Q1
Q0
t ar
5s
w.

D C B A
Q2
ww

SISO
Data input = 1100
Clock Serial input Serial output
0 0 0
4 1 1
8 1 1
12 0 0
16 0 0

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PIPO

Clock Parallel input Parallel output

m
A B C D QA QB QC QD

co
0 0 0 0 0 0 0 0 0

1 1 1 0 1 1 1 0 1

s.
SIPO
Left shift

te
No of clk pulse Serial input Din Parallel output
Q3 Q2 Q1 Q0
0 0 0 0 0 0
1
2
no 1
1
0
0
0
0
0
1
1
1
3 0 0 1 1 0
4 1 1 1 0 1
ar
5 0 1 0 1 0
6 0 0 1 0 0
7 0 1 0 0 0
t

8 0 0 0 0 0
5s

Right Shift

No of clock pulse Serial input Din Parallel output

Q3 Q2 Q1 Q0
w.

0 0 0 0 0 0
1 1 1 0 0 0
2 1 0 1 0 0
3 0 1 0 1 0
ww

4 1 1 1 0 1
5 0 0 1 1 0
6 0 0 0 1 1
7 0 0 0 0 1
8 0 0 0 0 0

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m
co
s.
te
no
t ar
5s
w.
ww

RESULT:
Thus the SISO, SIPO, PISO, PIPO shift registers were designed and implemented.

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m
EX.NO.14 14(a) DIFFERENTIATOR

co
AIM:
To design a Differentiator circuit for the given specifications using Op-Amp IC 741.

APPARATUS REQUIRED:

s.
S.No Name of the Apparatus Range Quantity
1. Function Generator 3 MHz 1
2. CRO 30 MHz 1

te
3. Dual RPS 0 – 30 V 1
4. Op-Amp IC 741 1
5. Bread Board 1
6. Resistors
7.
8.
Capacitors
Connecting wires and probes
no As required

THEORY:
The differentiator circuit performs the mathematical operation of differentiation; that is,
ar
the output waveform is the derivative of the input waveform. The differentiator may be
constructed from a basic inverting amplifier if an input resistor R1 is replaced by a capacitor C1.
The expression for the output voltage is given as, Vo = - Rf C1 (dVi /dt)
Here the negative sign indicates that the output voltage is 180 0 out of phase with the
t

input signal. A resistor Rcomp = Rf is normally connected to the non-inverting input terminal of
the op-amp to compensate for the input bias current. A workable differentiator can be
5s

designed by implementing the following steps:

1. Select fa equal to the highest frequency of the input signal to be differentiated. Then,
assuming a value of C1 < 1 µF, calculate the value of Rf.
w.

2. Choose fb = 20 fa and calculate the values of R1 and Cf so that R1C1 = Rf Cf.

3. The differentiator is most commonly used in waveshaping circuits to detect high
frequency components in an input signal and also as a rate–of–change detector in FM
modulators.
ww

PIN DIAGRAM:

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m
co
CIRCUIT DIAGRAM OF DIFFERENTIATOR:

s.
te
no
ar

DESIGN:
Given fa = ---------------
We know the frequency at which the gain is 0 dB, fa = 1 / (2π Rf C1)
Let us assume C1 = 0.1 µF; then
t

Rf = _________
Since fb = 20 fa, fb = ---------------
5s

We know that the gain limiting frequency fb = 1 / (2π R1 C1)

Hence R1 = _________
Also since R1C1 = Rf Cf ; Cf = _________
PROCEDURE:
w.

1. Connections are given as per the circuit diagram.

2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC.
3. By adjusting the amplitude and frequency knobs of the function generator, appropriate
input voltage is applied to the inverting input terminal of the Op-Amp.
4. The output voltage is obtained in the CRO and the input and output voltage waveforms
ww

are plotted in a graph sheet.

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OBSERVATIONS:
Input - Sine wave
S.No. Amplitude Time period

m
( No. of div x Volts per div ) ( No. of div x Time per div )
Input

co
Output
Input – Square wave
S.No. Amplitude Time period
( No. of div x Volts per div ) ( No. of div x Time per div )

s.
Input
Output

DIFFERENTIATOR:

te
INPUT SIGNAL:

no
Amplitude

ar

Time Period
t

OUTPUT SIGNAL:
5s Amplitude
w.
ww

Time Period

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m
co
s.
te
no
t ar

RESULT:
5s

The design of the Differentiator circuit was done and the input and output waveforms
were obtained.
w.
ww

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14(b) INTEGRATOR

m
AIM:

co
To design an Integrator circuit for the given specifications using Op-Amp IC 741.

APPARATUS REQUIRED:
S.No Name of the Apparatus Range Quantity

s.
1. Function Generator 3 MHz 1
2. CRO 30 MHz 1
3. Dual RPS 0 – 30 V 1
4. Op-Amp IC 741 1

te
5. Bread Board 1
6. Resistors
7. Capacitors
8. Connecting wires and probes As required

THEORY:
no
A circuit in which the output voltage waveform is the integral of the input voltage
waveform is the integrator. Such a circuit is obtained by using a basic inverting amplifier
configuration if the feedback resistor Rf is replaced by a capacitor Cf . The expression for the
ar
output voltage is given as,

Vo = - (1/Rf C1) ∫ Vi dt
Here the negative sign indicates that the output voltage is 180 0 out of phase with the
input signal. Normally between fa and fb the circuit acts as an integrator. Generally, the value
t

of fa < fb . The input signal will be integrated properly if the Time period T of the signal is
larger than or equal to Rf Cf. That is,
5s

T ≥ R f Cf
The integrator is most commonly used in analog computers and ADC and signal-wave
shaping circuits.
w.

PIN DIAGRAM:
ww

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m
co
s.
CIRCUIT DIAGRAM OF INTEGRATOR:

te
no
t ar
5s

DESIGN:
w.

We know the frequency at which the gain is 0 dB, fb = 1 / (2π R1 Cf)

Therefore fb = _____
Since fb = 10 fa, and also the gain limiting frequency fa = 1 / (2π Rf Cf)
We get, Rf = _______ and hence R1 = __________
ww

PROCEDURE:

1. Connections are given as per the circuit diagram.

2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC.
3. By adjusting the amplitude and frequency knobs of the function generator, appropriate
input voltage is applied to the inverting input terminal of the Op-Amp.

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4. The output voltage is obtained in the CRO and the input and output voltage waveforms
are plotted in a graph sheet.

m
OBSERVATIONS:

co
S.No. Amplitude Time period
( No. of div x Volts per div ) ( No. of div x Time per div )
Input

s.
Output

MODEL GRAPH:

te
INTEGRATOR:
INPUT SIGNAL:

no
Amplitude

ar

Time Period
OUTPUT SIGNAL:
t
5s
w.
Amplitude
ww

RESULT:

The design of the Integrator circuit was done and the input and output waveforms were
obtained.

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EX.NO. 15 15(a) TIMER IC APPLICATIONS - I

(ASTABLE MULTIVIBRATOR)

m
AIM:

co
To design an astable multivibrator circuit for the given specifications using 555 Timer
IC.

APPARATUS REQUIRED:

s.
S. No Name of the Apparatus Range Quantity
1. Function Generator 3 MHz 1
2. CRO 30 MHz 1
3. Dual RPS 0 – 30 V 1

te
4. Timer IC IC 555 1
5. Bread Board 1
6. Resistors
7. Capacitors no
8. Connecting wires and probes As required

THEORY:
An astable multivibrator, often called a free-running multivibrator, is a rectangular-
ar
wave-generating circuit. This circuit do not require an external trigger to change the state of
the output. The time during which the output is either high or low is determined by two
resistors and a capacitor, which are connected externally to the 555 timer. The time during
which the capacitor charges from 1/3 Vcc to 2/3 Vcc is equal to the time the output is high and is
given by,
t

tc = 0.69 (R1 + R2) C

5s

Similarly the time during which the capacitor discharges from 2/3 Vcc to 1/3 Vcc is
equal to the time the output is low and is given by,
w.

td = 0.69 (R2) C

Thus the total time period of the output waveform is,

T = tc + td = 0.69 (R1 + 2 R2) C

ww

The term duty cycle is often used in conjunction with the astable multivibrator. The
duty cycle is the ratio of the time tc during which the output is high to the total time period T.
It is generally expressed in percentage. In equation form,

% duty cycle = [(R1 + R2) / (R1 + 2 R2)] x 100

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PIN DIAGRAM:

m
co
s.
te
CIRCUIT DIAGRAM OF ASTABLE MULTIVIBRATOR:
no
t ar
5s
w.
ww

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DESIGN:

m
Given f= 4 KHz,

co
Therefore, Total time period, T = 1/f = ____________

We know, duty cycle = tc / T

Therefore, tc = ------------------------

s.
and td = ____________

We also know for an astable multivibrator

td = 0.69 (R2) C
Therefore, R2 = _____________

te
tc = 0.69 (R1 + R2) C
Therefore, R1 = _____________

PROCEDURE:
no
1. Connections are given as per the circuit diagram.
2. + 5V supply is given to the + Vcc terminal of the timer IC.
ar
3. At pin 3 the output waveform is observed with the help of a CRO
4. At pin 6 the capacitor voltage is obtained in the CRO and the V 0 and Vc voltage
waveforms are plotted in a graph sheet.
t

OBSERVATIONS:
5s

Time period
Amplitude ( No. of div x
( No. of div x Time per div )
S.No Waveforms
Volts per div )
w.

tc td

1. Output Voltage , Vo
ww

2. Capacitor voltage , Vc

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MODEL GRAPH:

m
co
Vcc
voltage
O/p

s.
T (ms)

te
2/3 Vcc
Capacitor
voltage

1/3 Vcc

TON
no TOFF
t ar
5s
w.
ww

RESULT:

The design of the Astable multivibrator circuit was done and the output voltage and
capacitor voltage waveforms were obtained.

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15(b) TIMER IC APPLICATIONS –II

m
(MONOSTABLE MULTIVIBRATOR)

co
AIM:

To design a monostable multivibrator for the given specifications using 555 Timer IC.

s.
APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity

1. Function Generator 3 MHz, Analog 1
2. CRO 30 MHz 1

te
3. Dual RPS 0 – 30 V 1
4. Timer IC IC 555 1
5. Bread Board 1
6. Resistors no
7. Capacitors
8. Connecting wires and probes As required

THEORY:
ar
A monostable multivibrator often called a one-shot multivibrator is a pulse generating
circuit in which the duration of the pulse is determined by the RC network connected
externally to the 555 timer. In a stable or stand-by state the output of the circuit is
approximately zero or at logic low level. When an external trigger pulse is applied, the output
is forced to go high (approx. Vcc). The time during which the output remains high is given by,
t

tp = 1.1 R1 C
5s

At the end of the timing interval, the output automatically reverts back to its logic low
state. The output stays low until a trigger pulse is applied again. Then the cycle repeats.
Thus the monostable state has only one stable state hence the name monostable.
w.

PIN DIAGRAM:
ww

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CIRCUIT DIAGRAM OF MONOSTABLE MULTIVIBRATOR:

m
co
s.
te
DESIGN:

Given tp = 0.616 ms = 1.1 R1 C no

Therefore, R1 = _____________

PROCEDURE:
ar

1. Connections are given as per the circuit diagram.

2. + 5V supply is given to the + Vcc terminal of the timer IC.
3. A negative trigger pulse of 5V, 2 KHz is applied to pin 2 of the 555 IC
t

4. At pin 3 the output waveform is observed with the help of a CRO

5. At pin 6 the capacitor voltage is obtained in the CRO and the V 0 and Vc voltage
waveforms are plotted in a graph sheet.
5s

OBSERVATIONS:

Time period
Amplitude
w.

( No. of div x
( No. of div x
S.No Time per div )
Volts per div )
ton toff
ww

1. Trigger input

2. Output Voltage , Vo

3. Capacitor voltage , Vc

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m
MODEL GRAPH:

co
s.
te
no
t ar
5s
w.
ww

RESULT:

The design of the Monostable multivibrator circuit was done and the input and output
waveforms were obtained.

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